JPH02184114A - Clock generator - Google Patents

Abstract

PURPOSE:To decrease the time required for phase synchronization and to set a phase difference between an input sinusoidal wave and a clock signal to a desired phase difference accurately by controlling the phase of an oscillator output in response to an output of an arithmetic means so as to apply fine adjustment of the phase. CONSTITUTION:A clock signal S12 to be outputted is synchronized with a sinusoidal wave S11 with a phase difference close to a desired phase difference with respect to the input sinusoidal wave S11 with the selection of a sampling clock signal by a selector 5, and the fine adjustment of the phase is executed by controlling the phase of the output of the oscillator 3 in response to an output of an arithmetic means 20. Thus, the time required for phase synchronization is reduced and the phase difference between the input sinusoidal wave S11 and the clock signal S12 is set accurately to the desired phase difference.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock generation device using automatic phase control.

[Conventional technology]

A typical prior art is shown in FIG.

This clock generator is for obtaining at an output terminal 42 a clock signal S2 whose phase is synchronized with a sine wave S1 inputted from an input terminal 41. Voltage controlled j'8 type oscillator (
The output of VCO) 43 is phase-shifted by π/2 by phase shifter 44 and input to multiplier 45 . The sine wave Sl is input to this multiplier 45, and the sine wave Sl is multiplied by the phase-shifted output of the voltage controlled oscillator 43.

From this multiplier 45 output, a low pass filter (LPF) 4
6 removes harmonic components, and an active filter 47 creates a control voltage for controlling the voltage controlled oscillator 43. In this way, a phase-locked loop is formed, and the voltage-controlled oscillator 43 is controlled so that the output of the multiplier 45 becomes 0, and in this way, the output of the voltage-controlled oscillator 43 is phase-locked to the sine wave S1. The clock signal S2 is obtained using the following clock signal S2.

[Problem to be solved by the invention]

In the above-mentioned prior art, the multiplier 45 operates only under the condition that the output of the multiplier 45 becomes 0, and moreover, the multiplier 45 operates under the condition that the phase difference between the input sine wave S1 and the output of the phase shifter 44 is π/2 or 3π/2. The output becomes 0 when . However, when the phase difference slightly deviates from 3π/2, the active filter 47 sends a control signal to the voltage controlled oscillator 43 to control the phase difference to π/2 based on the output of the multiplier 45. give. In this way, the difference of 4 stitches in the previous position is 3π
/2, the voltage controlled oscillator 4
The phase of the three outputs must be shifted by approximately π,
For this reason, phase locking takes time. Furthermore, since the above-mentioned prior art uses the phase shifter 44, there is a problem that the accuracy of phase synchronization of the output signal S2 with respect to the input sine wave S1 is controlled by the phase shifter 44.

An object of the present invention is to provide a clock generation device capable of outputting a clock signal that is phase-synchronized at high speed with respect to an input sine wave and in which a desired phase difference with respect to the input sine wave is set with high precision. It is to be.

[Means to solve the problem]

A clock generating device of the present invention is a clock generating device that generates a clock signal that is phase-synchronized with a sine wave having a constant frequency and having a predetermined phase difference, and has an oscillation frequency that is four times the frequency of the sine wave. an oscillator; a frequency divider that divides the oscillator output into 1/4 to create a four-phase sampling clock signal whose phase is shifted by π72; a selector that selects the two-phase sampling clock signals from the selector; and first and second analog/digital converters that sample the sine wave in synchronization with the two-phase sampling clock signals from the selector. , From the outputs of the first and second analog/digital converters, it is determined that the phase of the sine wave at the time of sampling in the first analog/digital converter is a phase region that divides one period of the sine wave into four. It is determined which phase region the sampling clock signal belongs to among the four phases of the sampling clock signal.
area discriminating means for supplying to the selector a selection control signal that causes the sampling clock signal whose phase difference with the sine wave is closest to the predetermined phase difference to be selected as the sampling clock signal of the first analog/digital converter; From the outputs of the first and second analog/digital converters, a signal is detected between the sampling clock signal and the sine wave whose phase difference with the sine wave among the four-phase sampling clock signals is closest to the predetermined phase difference. a calculation means for calculating a phase error with respect to the predetermined phase difference, and in response to the output of the calculation means, controls the phase of the oscillator output so as to reduce the phase error; The present invention is characterized in that the sampling clock signal given to the first analog/digital converter is output as a clock signal.

(Function) According to the configuration of the present invention, the oscillator has an oscillation frequency four times that of the sine wave to be phase-synchronized, and therefore, the frequency divider that divides the oscillator output by 1/4 outputs four phases. The sampling clock signal has a frequency equal to the frequency of the sine wave.

Since these four-phase sampling clock signals are phase-shifted by π/2, any one of the sampling clock signals has a desired phase difference between the clock signal to be output and the sine wave with respect to the sine wave. It has a phase difference closest to .

Of the four-phase sampling clock signals, two-phase sampling clock signals having a phase difference of π/2 are selected by a sorter, and these two-phase sampling clock signals are divided into first and second analog/digital signals, respectively. given to the converter.

The first and second analog/digital converters each sample the sine wave in synchronization with the sampling clock signal, and provide their outputs to the area determining means and the calculating means.

The region determining means determines to which phase region the phase of the sine wave at the time of sampling in the first analog/digital converter belongs to a phase region obtained by dividing one period of the sine wave into four by π/2. Ru.

The area discriminating means applies a sorting control signal to the sorter, and determines whether the phase difference with respect to the sine wave among the four-phase sampling clock signals from the frequency divider is a desired one between the sine wave and the clock signal. control is performed so that the phase difference closest to the phase difference is applied to the first analog/digital converter. The sampling clock signal applied to this first analog/digital converter is output as a clock signal. This sampling clock signal is phase-synchronized with the input sine wave with a phase difference close to a desired phase difference by selection of the frequency divider output by the selection device.

The arithmetic means calculates the phase difference between the sampling clock signal and the sine wave, of which the phase difference between the sine wave and the sine wave among the four-phase sampling clock signals is closest to the desired phase difference, with respect to the desired phase difference. A phase error is calculated. In response to this arithmetic means output, the phase of the oscillator output is controlled so as to reduce the phase error, thus increasing the phase of the sampling clock signal applied to the first analog-to-digital converter. Adjustments will be made. In this way, a clock signal phase-synchronized with the input sine wave having a desired phase difference can be obtained as the sampling clock signal given to the first analog/digital converter.

As described above, the output clock signal is synchronized with the input sine wave with a phase difference close to the desired phase difference with respect to the input sine wave by screening the sampling clock signal by the selector, and the phase is finely adjusted. This is done by controlling the phase of the oscillator output in response to the output of the arithmetic means, so the time required for phase synchronization is shortened, and since a phase shifter is not used as in the conventional case, it can be easily compared to a human-powered sine wave. The phase difference with the clock signal can be accurately set to the desired phase difference.

〔Example〕

FIG. 1 is a block diagram showing the basic configuration of a clock generator according to an embodiment of the present invention. This clock generator is configured to obtain at an output terminal 2 a clock signal S12 that is phase-synchronized with a sine wave Sll having a constant frequency fc input to an input terminal 1 with a predetermined phase difference (for example, π/2). A voltage-controlled oscillator 3 (hereinafter referred to as "oscillator 3") and a frequency divider that outputs a four-phase sampling clock signal whose frequency is divided by 1/4 and whose phase is shifted by π/2. 4, and two-phase sampling clock signals φ1 . A selector 5 that selects φ2, and first and second analog/digital converters (hereinafter referred to as rA/D converters) that sample the input sine wave 311 in synchronization with the sampling clock signals φ1 and φ2, respectively. )6.7, and outputs the sampling clock signal φ1 input to the first A/D converter 6 as a clock signal S12.

The outputs of the first and second analog/digital converters 6.7 are commonly input to the area discriminator 8 and the arithmetic unit 9. In the area discriminator 8, the phase of the input sine wave Sll during sampling in the first A/D converter 6 is π/
It is determined which of the two phase regions it belongs to, and its output is given as a control signal to the selector 5 via the delay device 10, and the selector 5 selects the four phases based on this control signal. Two phases are selected from the sampling clock signal of.

The calculator 9 performs four types of calculations, which will be described later, and the output thereof is input to the switch 11. The output of the region discriminator 8 is applied to this switch 11 via a line 12,
Using the output of the region discriminator 8 as a switching control signal, the above four types of calculation results are selectively led out to the line 13. In this embodiment, a calculation means 20 includes the calculation unit 9 and the switch 11, and the output of the switch 11 becomes a phase error signal.

The phase error signal from line 13 is input to a control section 14 which creates a control voltage for the oscillator 3.

This control unit 14 includes a counter 16 that divides the output of the oscillator 3 from the line 15 to create a reference frequency signal, and outputs the output of the counter 16 by performing pulse width modulation based on the phase error signal from the line 13. The pulse generator 1 is composed of a pulse generator 17, a low-pass filter, etc.
7 output into a DC voltage to create a control voltage for the oscillator 3. Then, the oscillator 3 is caused to oscillate at a frequency of 4fc, which is four times the frequency of the human-powered sine wave Sll. Therefore, the four-phase sampling clock signal that the frequency divider 4 provides to the selector 5 has a frequency equal to the input sine wave 311.

The input sine wave 311 is set to the same level as the input range of the A/D converters 6 and 7. For example, when the A/D converters 6 and 7 are 8-pin, the input sine wave S
The maximum value of ll is 11111111,! +, the minimum value is 0000000On+, the average value is 10000000
(t.

is encoded as However, the subscript (2) indicates that it is a binary number. This situation is shown in FIG.

FIG. 3 is a waveform diagram for explaining the operation of the area discriminator 8 and the like. In the region discriminator 8, the first
The phase at the time of sampling in the A/D converter 6 is divided into a phase region A (π/2), which is not shown in FIG.
/4~3π/4), B(3π/4~5π/4), C(5
It is determined which of D(7π/4 to π/4) it belongs to. For example, the first and second A/
The sub-ring of the input sine wave Sll in the D converters 6 and 7 is the sampling clock signal φ1. When this is performed in synchronization with the rise of φ2, the third A/D converter 6, 7
Sampling clock signal φ shown in Figures (2) and (3)
1. When φ2 is given, the discrimination result in the area discriminator 8 becomes "phase area A." Also, Figure 3 (4)
and sampling clock signal φ1. shown in (5). φ
2 is the first. When applied to the second A/D converter 6.7, the discrimination result of the region discriminator 8 is “phase region B”.
”.

Such region discrimination by the region discriminator 8 is performed based on the outputs of the first and second A/D converters 6.7. That is, for example, the output of the first A/D converter 6 is 110,000.
When it is 00 us or more, it is determined to be "phase region A", and when the output of the second A/D converter 7 is 00111111°, it is determined to be "phase region B", etc.

For example, in order to obtain the clock signal 512 (that is, the sampling clock signal φ1) whose phase is shifted by π/2 with respect to the input sine wave Sll, the selector 5 is provided with a clock signal 512 whose phase is shifted by π/2 with respect to the input sine wave Sll. A control signal that causes the sampling clock signal to be selected as the sampling clock signal φl of the first A/D converter 6 is input. That is, for example, the sampling clock signals φ1 and φ2 shown in FIGS. 3(4) and 3(5) are the first . Second A
When the sampling clock signal φ1 is applied to the A/D converter 6.7, the sampling clock signal φ1 is set as the sampling clock signal φ2 to be applied to the second A/D converter 7, and the first A/D converter 6.
A control signal for providing a sampling clock signal whose phase is delayed by π/2 from the sampling clock signal φ1 shown in FIG. be done.

Next, the operation of the calculation means 20 will be explained. In the computing unit 9, the outputs of the first and second A/D converters 6.7 and these A/D converters are
Center value of output of Da converters 6 and 7 10000000 t
The difference with u is calculated, and four types of signals with positive and negative signs attached to the values are given to the switch 11. The switch ALL selects one type of signal from these four types of signals based on the area discrimination result provided from the area discriminator 8 via the line 12, and outputs this as a phase error signal.

For example, when the region discriminator 8 determines "phase region A", (second A/D converter 7 output) 10000000
tx> as the phase error signal, and when the region discriminator 8 makes a determination of "phase region B", 10000000 (!+ (output of the first A/D converter 6)) is the phase error signal.

Each of the phase error signals has a phase error Δ1. Δ
Corresponds to 2. In FIG. 3, ΔφO is a desired phase difference (π/2), and Δφ11 is a phase difference between the sampling clock signal φ1 and the input sine wave S11. Further, Δφ12 is the phase difference between the sampling clock signal whose phase difference with the input sine wave Sll is closest to the desired phase difference ΔφO among the four-phase sampling clock signals from the frequency divider 4, and the input sine wave Sll. corresponds to

That is, the switch 11 selects the sampling clock signal whose phase difference with the input sine wave Sll is closest to the desired phase difference ΔφO among the four-phase sampling clock signals output by the frequency divider 4, and the human input sine wave. A phase error signal corresponding to the error of the phase difference with Sll with respect to the desired phase difference Δφ0 is output.

If the control unit 14 controls the oscillator 3 based on the phase error signal created in this way, the
It is possible to accurately shift the phase of one of the phase sampling clock signals by π/2 from the input sine wave Sll to obtain a sampling clock signal phase-synchronized with this sine wave Sll.

This phase-synchronized sampling clock signal is selected by the selector 5 in response to a control signal from the area discriminator 8 via the delay device IO.

As described above, according to this embodiment, from the four-phase sampling clock signal having the same frequency as the input sine wave Sll, the signal corresponding to the phase region of the sine wave Sll at the time of sampling in the first A/D converter 6 is obtained. to select the two-phase sampling clock signals, and the sampling clock signal φl given to the first A/D converter 6 has an input sine of 1.
The phase difference with respect to 311 is taken to be the sampling clock signal closest to the desired phase difference. Then, the sampling clock signal φ2 whose phase is shifted by π/2 with respect to the sampling clock signal φ1 is input to the second A/D converter 7, and the first and second A/D converters 6, 7 The phase difference between the sampling clock signal having the phase difference closest to the desired phase difference with respect to the input sine wave Sll among the four-phase sampling clock signals from the output and the input sine wave Sll with respect to the desired phase difference. Calculate the error and calculate the phase of the oscillator 3 output based on this phase error signal.
I'm trying to make adjustments. In this way, π/of the clock signal S12 (sampling clock signal φ1)
The phase is adjusted in units of 2, and the phase of the oscillator 3 output is finely adjusted (adjustment within the maximum range of π/2), so the oscillator 3 output is quickly adjusted and the clock signal 312 can be phase-synchronized at high speed with respect to the input sine wave Sll. Also, a desired phase difference (in this example, π/
In order to obtain 2), the desired phase difference can be achieved with high precision because phase thick is not used as in the conventional method.

In the above-mentioned embodiment, the control unit 14 that obtains the control voltage of the oscillator 3 from the output of the switch 11 performs pulse width modulation on the reference frequency signal from the counter 16 using the output of the switch 11, and applies this to a low-pass filter or the like. Although the DC voltage is converted to a DC voltage by the DC converter 18, the configuration for creating the control voltage of the oscillator 3 may be a configuration in which the output of the switch 11 is converted from digital to analog.

Further, instead of the oscillator 3, a digital oscillator may be used, and this digital oscillator may be controlled by digital data from the switch 11.

〔Effect of the invention〕

According to the clock generator of the present invention, the phase of the output clock signal is synchronized with the sine wave with a phase difference close to a desired phase difference with respect to the human-powered sine wave by screening the sampling clock signal by the screener. Since the phase of the oscillator is finely adjusted by controlling the phase of the oscillator output in response to the output of the calculation means, the time required for phase synchronization is shortened, and it is not necessary to use a phase shifter as in the conventional method. said input obtained by sampling the phase error with a clock signal (sampling clock signal given to the first analog-to-digital converter) and a sampling clock signal whose phase is shifted by π/2 with respect to this clock signal. Since the calculation is performed using the digital value of the sine wave, the phase difference between the manually generated sine wave and the clock signal can be accurately set to the desired phase difference.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a clock generator according to an embodiment of the present invention, and FIG. 2 is a digital value of an input sine wave 311 in the first and second Δ/D converters 6 and 7. FIG. 3 is an explanatory diagram showing the manner of conversion to
The fourth waveform diagram is a block diagram showing the basic configuration of a typical prior art. 3... Oscillator, 4... Frequency divider, 5... Selector, 6
...First A/D converter, 7... Second A/D converter, 8... Area discriminator, 20... Calculating means Fig. 4 Fig. 1

Claims (1)

[Scope of Claims] A clock generation device that generates a clock signal that is phase-synchronized with a sine wave having a constant frequency and having a predetermined phase difference, comprising: an oscillator having an oscillation frequency four times the frequency of the sine wave; , a frequency divider that divides this oscillator output by 1/4 to create a four-phase sampling clock signal whose phase is shifted by π/2; a selector that selects the two-phase sampling clock signals from the selector; and first and second analog/digital converters that sample the sine wave in synchronization with the two-phase sampling clock signals from the selector. From the outputs of the first and second analog/digital converters, it is determined that the phase of the sine wave at the time of sampling in the first analog/digital converter is within a phase region obtained by dividing one period of the sine wave into four. among the four-phase sampling clock signals, the sampling clock signal whose phase difference with the sine wave is closest to the predetermined phase difference is selected by the first analog/digital converter. area discriminating means for supplying a sorting control signal to the sorter for sorting out the four-phase sampling clock signals; a calculation means for calculating a phase error between the sampling clock signal and the sine wave, the phase difference of which is closest to the predetermined phase difference, and in response to the output of the calculation means, The phase of the oscillator output is controlled to reduce the phase error, and the sampling clock signal given from the selector to the first analog/digital converter is output as a clock signal. Clock generator.