JPH02183536A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a fine multilayer wiring and realize high degree of integration by a method wherein extracting outside is enabled by making the size of an interlayer connection hole larger than the width of a lower layer wiring. CONSTITUTION:The upper surface of a first aluminum wiring 3 and a part of a side surface connecting with the upper surface of the wiring 3 are exposed, and an interlayer connection hole 8 is formed in a silicon oxide film 4. A tungsten film 5 as a conductor film for connection use which covers the exposed part of the first aluminum wiring 3 and connects it with a second aluminum wiring 7 is buried in the interlayer connection hole 8 and turned into a connection between wirings. By using a silica coating oxide film 6 formed by filling the gap between the tungsten film 5 and the interlayer connection hole 8, the surface on which a second aluminum wiring 7 is formed is flattened. As a result, the interlayer connection hole 8 is larger than the width of the lower wiring 3, that is, enabling outside-extraction. Thereby, a sufficient size wherein alignment deviation is considered can be set, and the width of the lower wiring can be made small, so that the wiring pitch can be reduced and high density integration is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a semiconductor device having a multilayer wiring structure, and in particular,
The present invention relates to a semiconductor device that enables fine multilayer wiring.

〔overview〕

The present invention provides an interlayer connection in a semiconductor device having multilayer wiring, in which a conductive film for connection between a lower layer wiring and an upper layer wiring is formed by exposing an upper surface of the lower layer wiring and a part of a side surface portion continuous to the upper surface. By providing the inter-wiring connection portion formed by filling the hole, there is no need to increase the width of the lower layer wiring in the inter-wiring connection portion, and high integration is achieved.

[Conventional technology]

Conventionally, this type of semiconductor device is shown in FIGS. 4(a) and 4(b).
) It had a wiring structure as shown in ( ). In the same figure,
1 is a silicon substrate, 2 is a silicon oxide film, 3 is a first aluminum wiring, 4 is a bias ECR (Ble-ctron C
y'clotron Re5onance) Blaz 7C
A silicon oxide film is formed by a VD method or the like, 7 is a second aluminum wiring, and 8 is an interlayer connection hole.

In this conventional example, the width of the first aluminum wiring 2 is increased at the connection portion between the first aluminum wiring 2 and the second aluminum wiring 4. For this reason, for example, the first aluminum wiring width is 1.0 μm, the wiring interval is 1.0 μm, and the interlayer connection hole 8 is 1.0 μm. Oitm% interlayer connection hole 8 and first aluminum wiring 3
If the margin is 0.5 μm, the first aluminum wiring pitch will be 2.5 μm.

[Problem that the invention seeks to solve]

In the conventional semiconductor device described above, in order to prevent the interlayer connection hole from shifting relative to the lower layer wiring and cutting out, the wiring width is increased in consideration of the wiring margin in the lower layer wiring portion where the interlayer connection hole is opened. was. This means that the wiring pitch is larger in areas where interlayer connection holes are installed than in areas where they are not installed, which is a drawback that is a major impediment to higher integration of semiconductor integrated circuits. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can achieve high integration by eliminating the above-mentioned drawbacks and which allows interlayer connections to be made without increasing the wiring pitch of the lower layer wiring.

[Means for solving problems]

The present invention provides a semiconductor device having multiple layers of wiring formed on one principal surface of a semiconductor substrate with an insulating film sandwiched therebetween, in which the upper surface of the lower wiring and a part of the side surface connected thereto are exposed, and the insulating film is exposed. In the interlayer connection hole formed in a part,
It is characterized by having an inter-wiring connection portion in which a connecting conductive film formed to cover the exposed portion of the lower-layer wiring and connected to the upper-layer wiring is embedded.

[Effect]

A conductive film for connection, such as a tungsten film, is formed by filling an interlayer connection hole formed by exposing the upper surface of the lower layer wiring and a part of the side surface connected thereto, and between the side surface portion and the upper surface of the lower layer wiring. The structure has an interlayer insulating film interposed therebetween.

Therefore, the interlayer connection hole is larger than the width of the lower layer wiring, that is, it is cut out, and can be set to a size sufficient to take into account misalignment. Moreover, the width of the lower layer wiring can be left as is, and as a result, it is possible to reduce the wiring pitch and achieve high integration.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a plan view showing one embodiment of the present invention, and FIG. 1(a) is a sectional view taken along line AA'.

In this embodiment, a first aluminum wiring 3 and a second aluminum wiring 7 are formed as two-layer wiring, which are formed on one principal surface of a silicon substrate 1 with silicon oxide films 2 and 4 as insulating films sandwiched therebetween. In the semiconductor device having the above, the upper surface of the first aluminum interconnect 3 and a part of the side surface connected thereto are exposed, and an interlayer connection hole 8 is formed in the silicon oxide film 4 to cover the exposed portion of the first aluminum interconnect 3. It has an inter-wiring connection portion in which a tungsten film 5 as a connection conductive film connected to the second aluminum wiring 7 is embedded.

In FIGS. 1(a) and (b), 6 is a silica-coated oxide film formed by filling the gap between the tungsten film 5 and the interlayer connection hole 8, which is a gap caused by misalignment when forming the interlayer connection hole. Fill in the recesses caused by the second aluminum wiring 7.
The material is not limited to silica, but may be any material that can fill the gap and form an insulator.

The feature of the present invention is that in FIGS. 1(a) and (b),
The size of the wiring connection hole 8 is set larger than the width of the lower layer wiring 3, and the tungsten film 5 is provided as a connection conductor film by filling it.

Next, regarding the manufacturing method of this example, please refer to the plan view and the AA' cross-sectional view of the main steps shown in FIGS. 2(a) and (b) and 3(a) and (b). I will explain.

First, as shown in FIGS. 2(a) and 2(a), aluminum with a thickness of about 0.5 μm is deposited on the silicon oxide film 2 on the silicon substrate 1 to form a first aluminum wiring 3. .

Next, as shown in FIGS. 3(a) and 3(b), after forming a silicon oxide film 4 with a thickness of about 0.9 μm on the first aluminum wiring 3 by bias ECR plasma CVD method, the first aluminum wiring 3 Selectively expose the top surface and some sides of the
A tungsten film 5 having a thickness of about 0.4 μm is formed by a tungsten selective CVD method. and tungsten film 5
The gap between the silicon oxide film 4 and the silicon oxide film 4 is coated with silica by an etch-back method, and then filled with a silica-coated oxide film 6 by heat treatment.

Finally, as shown in Fig. 1(a) and et al., the film thickness is 1
．． Aluminum with a thickness of about 0 μm is deposited and patterned to form a second aluminum wiring 7 electrically connected to the tungsten film 5.

In this example, the first aluminum wiring width is 1.0 μm, the wiring spacing is 1.0 μm, and the interlayer connection hole 8 is 1.0 μm×2.0 μm.
-, the first aluminum wiring pitch is 2.0 μm.

In this embodiment, aluminum is used as the wiring material for the first wiring and the second wiring, but a high melting point metal such as tungsten can also be used instead of aluminum. In this case, there is an advantage that the migration resistance of the wiring is greatly improved. Further, the same applies when using other conductive materials such as highly conductive polycrystalline silicon as the wiring material.

〔Effect of the invention〕

As explained above, the present invention has the effect that fine multilayer wiring can be realized and high integration can be achieved by making the size of the interlayer connection hole larger than the width of the lower layer wiring, that is, by making it possible to cut out the outer layer. There is.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and an AA' cross-sectional view showing an embodiment of the present invention. FIGS. 2(a) and 2(b) are a plan view and an AA' sectional view of the main manufacturing process. FIGS. 3(a) and 3(a) are a plan view and a sectional view taken along the line AA' of the main manufacturing process. FIGS. 4(a) and 4(b) are a plan view and a BB' sectional view showing a conventional example. 1... Silicon substrate, 2.4... Silicon oxide film,
3... First aluminum wiring, 5... Tungsten film, 6
...Silica-coated oxide film, 7.Near aluminum wiring, and...Interlayer connection hole.

Claims (1)

[Claims] 1. In a semiconductor device having multiple layers of wiring formed on one main surface of a semiconductor substrate with an insulating film in between, the upper surface of the lower wiring and a part of the side surface connected thereto are exposed. The interlayer connection hole formed in a part of the insulating film has an inter-wiring connection part in which a connecting conductive film formed to cover the exposed portion of the lower-layer wiring and connected to the upper-layer wiring is embedded. semiconductor device.