JPH02178802A - Data processor - Google Patents

Abstract

PURPOSE:To execute the control of a continuous pulse output by processing the interrupt for setting (update) of start and end timings of the pulse output. CONSTITUTION:When accepting the timing signal of the start and the end of the pulse output from an INTC (interrupt occurrence request circuit) 112 as an interrupt request signal, a CPU 100 does not refer to a vector table to execute a prescribed data processing, namely, the micro service based on processing mode information preliminarily set in a specific address of a data memory 114. Consequently, start and end timings of the pulse output in the next cycle are set based on data preliminarily set in a prescribed address without saving contents of a PC (program counter) 107 and a PSW (program execution state holding register) 108 in a stack space. Thus, the continuous pulse output is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to pulse output in machine control, particularly to a method of continuously outputting pulses.

[Conventional technology]

Microcomputers are now being used for machine control. Basically, PWM output pulses output from a microcomputer are generally used to directly open and close valves, drive motors, etc.

FIG. 5 shows an example of a pulse output pattern when performing pulse output according to the conventional technique.

Hereinafter, a conventional pulse generator will be explained with reference to FIGS. 6 and 7. FIG. 6 is a block diagram of a conventional pulse generator, and FIG. 7 is a block diagram of conventional peripheral hardware. The device shown in FIG. 8 includes a CPU 800. data bus 1
10. Address bus 111, INTC (interrupt generation request circuit) 112. Program memory 113. It is composed of a data memory 1141 and peripheral hardware 115.

The CPU 800 includes an arithmetic logic unit (hereinafter referred to as ALU) 101. Temporary register 102° General purpose register 103. Address buffer 104 (represented by AB in the figure), micro address (hereinafter referred to as μ address) generation unit 105. μROMI 06. It is composed of a PC (program counter) 107 degrees, a PSW (program execution state holding register) 108 degrees, and a timing control section 109.

The INTC 112 also has an interrupt request flag 116 and outputs an interrupt request signal 117 to the timing control section 109. When the timing control unit 109 accepts the interrupt request, it outputs an interrupt request clear signal 118 to the INTC 112 .

The INTCl 12 accepts several interrupt signals from external hardware, determines the priority assigned to each interrupt source, selects the one interrupt source with the highest priority, and The interrupt request flag 116 corresponding to the interrupt source is set. The interrupt request flag 116 indicates that when there are n interrupt requests,
Although n pieces are set, only one is shown in the figure.

Furthermore, interrupt signals from external hardware, a priority level determination unit, and the like are not particularly shown.

Conventional interrupt processing is usually called vectored interrupt, and a vector table space is set in advance in a memory space, and this space stores entry addresses of interrupt processing programs corresponding to each interrupt source.

When a vectored interrupt occurs, a branch is made to the entry address corresponding to the interrupt source.

Next, the configuration of the peripheral hardware 115 will be explained using FIG. 7.

Peripheral hardware 115 includes timer 901 . There are three conveyor registers (hereinafter referred to as CO) that perform a comparison operation with the value of timer 901 and control the output pulse.
MPT, COMPS, COMPR)902,903,9
04, a set/reset type flip-flop (hereinafter referred to as output F/F) 905 that holds the level of the output pulse, and a baud P that outputs the value of the output F/F' to the outside.

COMPT902 is a conveyor register that defines the period of the output pulse, and a value corresponding to the period TO of the output pulse is set in advance by the CPU 800. Also, C
The OMPT 902 always performs a comparison operation with the timer 901, and when the value held in the register matches the value of the timer 901,
A match signal 912 is output. Similarly, COMPS903
．． COMPR904 is a conveyor register that specifies the pulse output start timing and pulse output end timing of each output pulse, and always performs a comparison operation with the timer 901, and when the value of the timer 901 and the value held in each register match, a match is determined. Outputs signals 913 and 914. All these conveyor registers are CPU80
It is possible to read and write from 0.

The coincidence signal 912 is input to the timer 901, and the timer 90
1 is cleared to all "0" when this signal is input. As a result, the timer 901 changes from the count value 0 to T.
It functions as an interval timer that continuously counts up to 0.

Next, the pulse output control operation in this example will be explained with reference to FIGS. 5 to 7. However, the explanation will start when the output F/F 905 is set and the output from the baud P is at low level.

In normal instruction processing, the program address stored in the PC 107 is transferred to the address buffer 104, the address bus 111 is transferred to the address bus 111, and the program address stored in the program memory 11 is transferred to the address buffer 104.
3, the next instruction to be executed is fetched.

The fetched instruction is transferred to the μ address generation unit 105 via the data bus 110. μ address generation unit 1
05 generates the address of μROM 106 from the instruction code. Thereafter, the instruction is processed by manipulating the ALUIOI, temporary register 102, general-purpose register 103, etc. according to the instructions of the μ program for the instruction stored in the μROM 106.

INTCl 12 independently of the processing of the CPU 800,
It constantly samples whether or not an interrupt request is generated from peripheral hardware, and if a request is generated, the request is set to 1.
Interrupt request flag 1 corresponding to that source
Set 16.

Now, when the value of COMPS903 and the value of timer 901 match, COMPS903 outputs a match signal 913,
By setting the output F/F 905 with this signal, the output from P is set to high level. (Figure 5 - Timing tl, t4.t7) Also, the coincidence signal 913 is I
The interrupt request signal 117 is input to the NTC 112 and generates an interrupt request to the INTCl 12. If the NTC 112 accepts the request and the interrupt request flag 116 is set, an interrupt request signal 117 is output to the timing control unit 109.

The final timing of each instruction execution is the timing to detect whether or not an interrupt has occurred.
At this timing, the timing control unit 109 samples the presence or absence of the interrupt request signal 117. If the interrupt request signal 117 is active, the interrupt request is accepted and the interrupt request clear signal 118 is sent to the INTC11.
2 and clears the interrupt request flag 116.

Next, connect the PC 107 and PSW 108 to the stack pointer (C
It is saved in the stack space pointed to by a register (not shown) set in the PU 800, and corresponds to an interrupt source stored in a vector table set at a specific address in the data memory 14. The entry address of the interrupt processing program is read and set in the PC 107 via the data bus 110. PC
Execution of the interrupt processing program is started from the program address newly set in 107.

The interrupt processing program based on the interrupt processing request by this coincidence signal 913 is an interrupt processing for setting the pulse output start timing of the pulse output from Baud P in the next cycle. In the interrupt processing started at timing t1 of S1,
Setting the timing t4 of the next cycle S2, etc.
The CPU 800 sequentially sets the pulse output start timing of the next cycle. At this time, the CPU 800 stores data corresponding to the period from when the timer 901 is cleared to all "'0" until the pulse output is activated to the COMPS 903.
Set to .

In the processing of the instruction that ends the interrupt processing program, the PC value and PSW value saved in the stack space are restored to the PC 107 and PSW 108, respectively, and processing is restarted from the next instruction at the time when the interrupt occurred.

Next, when the value of COMPR904 and the value of timer 901 match, COMPR904 outputs a match signal 914,
This signal resets the output F/F 905, thereby setting the pulse output from port P to a low level.

(Figure 5 - Timing t2゜t5.t8) Also, the coincidence signal 914 is input to the INTC 112, and the I
Generates an interrupt request to NTC112, and INTC1
12 accepts the request and the interrupt request flag 116 is set, an interrupt request signal 117 is output to the timing control section 109.

At the final timing of instruction execution, the timing control unit 1
09 samples the presence or absence of the interrupt request signal 117.

If the interrupt request signal 117 is active, similar to the interrupt processing activated by the match signal 913,
An interrupt request clear signal 117 is output to the INTCI 12, and the interrupt request flag 116 is cleared.

Next, it is saved to the stack space of the PC 107 and PSW 108, and branches to the entry address of the interrupt processing program corresponding to the interrupt source stored in the vector table set at a specific address in the data memory 114, and the interrupt processing program starts execution.

The interrupt processing program based on the interrupt processing request by this coincidence signal 914 is an interrupt processing for setting the pulse output end timing of the pulse output from Baud P in the next cycle. S
The pulse output end timing of the next cycle is sequentially set, such as by setting the timing t5 of the next cycle S2 in the interrupt process activated at timing t2 of the first cycle. At this time, the CPU 800 sets the timer 901 to the COMPR 904.
The data corresponding to the period from when is cleared to all "0" until the pulse output is reset is stored in COMPR90.
By setting it to 4, the pulse width of the output pulse is set.

In the processing of the instruction to terminate the interrupt processing program, the PC value saved in the stack space.

Each psw value is PCI 07. By returning to PSWI 08, processing is resumed from the next instruction at the time when the interrupt occurred.

As mentioned above, COMPS 903, COMPR90
The coincidence signals 913 and 914 output from the ports 4 directly control the pulse output from the port P, and the interrupt processing activated by these signals determines the pulse output start timing of the pulse output to be output in the next cycle. The pulse output end timing is set. Therefore, by repeating this operation, the pulse output from the boat P and the control of the pulse output can be continuously performed. The above explanation shows one example of various pulse output control methods, but control is basically performed using the same processing method.

[Problem to be solved by the invention]

As mentioned above, the conventional pulse generator generates a signal to start pulse output and a signal to end pulse output.
It is accepted as an interrupt signal, and the interrupt processing program sets the start timing and end timing of the pulse output to be output in the next cycle. When returning from the program to main processing, the process of restoring the contents of the stack to the PC and PSW occurs frequently, so the higher the frequency of the output pulse, the greater the proportion of CPU time divided into saving and returning. Become.

Moreover, in addition to pulse control, the CPU also executes various programs such as other data processing, and if interrupt processing for pulse output control takes a large amount of time, the CPU time divided into these main processes will be wasted. In some cases, processing that cannot be performed at all may occur.

Furthermore, in FIG. 7, if the value set as the pulse output start timing (timing t7) of the next cycle S3 by the interrupt processing of the cycle S2 is larger than the current timer count value, then Even if the setting is made with the intention of specifying the pulse output timing, the current cycle S
A coincidence signal for starting pulse output is generated again within 2 (timing tX). Therefore, the current period S
If the second pulse output has been completed, an event occurs in which the pulse output is started without waiting for the next cycle S3. The pulse output at this time is from timing tX to t6 to t.
This results in a pulse output that spans two periods with a period of 7 to t8.

The above pulse output is different from the originally intended start and end timing of the pulse output, and a pulse with an unintended pulse width is output.For example, if the pulse output width is the control amount itself, In such a case, a serious problem arises in that incorrect control is executed on the controlled object.

Moreover, in order to prevent and correct this, dedicated program processing is required, and if this processing is added to the interrupt processing that sets the start and end timing of pulse output, the time required for interrupt processing for pulse output control will be reduced. , will continue to increase as a whole.

[Means to solve the problem]

The present invention provides a processing device having a CPU including a PC, a PSW, a general-purpose register, and a μROM, an INTO that asynchronously generates an interrupt processing request to the CPU, a program memory, a data memory, and a peripheral circuit, wherein the peripheral circuit is a timer. , a plurality of conveyor registers for comparison with a timer, and a port for pulse output. A mode specifying means for identifying a request for predetermined data processing is provided, processing mode information specifying a processing mode for the predetermined data processing is stored in the data memory, and INT
When a request for predetermined data processing is issued from O to the CPU, if the CPU detects that the format instruction means is instructing predetermined data processing, the CPU interrupts the instruction execution process and changes the processing format. According to the information, the predetermined data in the data memory is compared with the timer value t or the value of the conveyor register at the timing, and when the comparison result meets the predetermined condition, the data is transferred to the predetermined conveyor register. It has a feature of controlling pulse generation from the output port.

In this way, the present invention enables the PC to receive pulse output start and end timing signals as interrupt request signals.
, Continuous pulse output control from ports can be performed by setting the start and end timing of the next cycle of pulse output based on data set in advance at a predetermined address without saving the PSW to the stack space. Furthermore, if the data set in the conveyor register that defines the start and end of pulse output has the possibility of generating an erroneous pulse output, this is detected and a vectored interrupt is generated. Notifies the CPU of the need for special processing.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a pulse generator showing a first embodiment.

The pulse generator of the present invention includes a CPU 100 and a data bus 110. address bus 111. INTC112, program memory 113. It is composed of a data memory 114 and peripheral hardware 115.

The CPU 100 has ALUIOI, temporary register 1
02. General purpose register 103. Address buffer 104 (
(Represented by AB in the figure).

μ address generation unit 105. μROMI O6, PCl
07, PSWI 08. It is composed of a timing control section 109.

The INTC 112 also includes an interrupt request flag 116 and a format designation flag 119.
09, interrupt request signal 117 and form specification signal 1
Outputs 20. The timing control unit 109 is an INTC
A form change signal 121 of the interrupt request clear signal 118 is output to the interrupt request clear signal 112 .

INTCl 12 accepts several interrupt signals from external hardware, determines the priority assigned to each interrupt source, selects the one interrupt source with the highest priority, and The corresponding interrupt request flag 116 is set. Although n interrupt request flags 116 and mode specification flags 119 are each set when there are n interrupt requests, only one set is shown in the figure. Further, interrupt signals from external hardware, a priority order determining section, and the like are not particularly illustrated because they are not directly related to the gist of the present invention.

The CPU 100 can process an interrupt request from the INTC 112 in two ways.

One is traditional vectored interrupt processing, and the other is
In the processing mode that is the gist of the present invention, when an interrupt occurs, the vector table is not referenced and the data memory 1 is
This is a form in which predetermined data processing is executed based on processing form information preset to a specific address in 14.

Below, this predetermined data processing will be referred to as a microservice.

Specifying whether a vectored interrupt is a microservice is done using the type specification flag 119. When the CPU 100 sets the type specification flag 119 to 1 "0", it is considered a vectored interrupt, and when it is set to ``1'', it is considered a microservice. It is specified.

It should be noted that the peripheral hardware configuration and its operation in this embodiment are the same as the peripheral hardware configuration shown in FIG. 9 in the conventional example and the operation described above, and therefore the description thereof will be omitted here.

Next, processing form information that specifies the processing form of a microservice according to the present invention will be explained. FIG. 2 shows the structure of processing mode information. The processing mode information is placed at a specific address in the data memory 114, and the processing mode information in this example is composed of a 1-byte header section having a channel pointer and a 2-word microservice channel pointed to by the channel pointer. Ru.

The microservice channel in this example is configured to output one pulse, and is composed of word data 1 that specifies the output start timing of the output pulse, and word data 2 that specifies the output end timing of the output pulse. ing.

Word data 1 is the word data corresponding to the period of the pulse output output from the timer 9010 count value 0 to the count value at which pulse output is started, and word data 2 is the period from the timer 9010 count value 0 to the count value that starts pulse output. , word data corresponding to the period up to the count value at which the pulse output ends, that is, word data for defining the pulse width of the output pulse, is stored by the CPU 100.

The microservice in this example is COMPS903゜COM
It is activated by match signals 913 and 914 from PR904. Before the microservice is started, the CPU
100 initializes the microservice channel and hardware.

FIGS. 3(a) and 3(b) are flowcharts showing the microservice of this example, which is actually controlled by the μ program. Further, FIG. 4 shows an example of a pulse output pattern in this embodiment.

The microservice and pulse output control operations will be explained below with reference to FIGS. 1 to 4. However, the explanation will start from a time when the output F/F 905 has been reset and the pulse output from port P is at a low level.

First, the timer 901 receives the match signal 912 of COMPT902.
All the bits are cleared to "0-" and the counting operation starts from the initial value 0. (Figure 4 - Timing tO, t3
．． t6. t9) Next, when the held value of COMPS 903 matches the count value of timer 901, a match signal 913 is output. Further, the coincidence signal 913 is input to the output F/F 905, and by setting the output F/F 905, the pulse output from the port P is set to the No. 1 level. Furthermore, the coincidence signal 9
13 performs the above operations and also inputs the interrupt request.
Occurs for TCI 12. (Figure 4 - Timing t
l, t4. t7) INTCl 12 is the match signal 91
When the 30 interrupt request is accepted, the interrupt request flag 116 corresponding to this source is set and the interrupt request signal 117 is activated.

The timing control unit 109 samples the interrupt request signal 117 at the end of instruction processing and is active.
The form indicating means 120 is sampled. Form indicating means 12
When detecting that 0 is 1''' indicating a microservice, the PC 107 generates a microservice processing entry address in the μROM 106 while retaining the information in the PSW 108, and starts the microservice.

Hereinafter, the processing flow of the microservice according to the μ program command will be explained along the flowchart of FIG. 3(a).

First, the header of the microservice using the match signal 913 as an interrupt source is read from a specific address in the data memory 114, and the address of the microservice channel is detected.

Next, the contents of the timer 901 are read, and the count value of the timer read at this time is compared with word data 1 in the microservice channel corresponding to this microservice processing. (Hereinafter, this read data will be used as TMO
That's what it means. ) As a result of the comparison, if word data 1 is smaller than TMO, word data 1 is set in COMPS 903.

Next, in response to a command from the μ program, the timing control unit 109 outputs an interrupt request clear signal 118 to the INTC 112, and ends the microservice processing with the interrupt request flag 116 reset.

When the microservice processing is completed, the timing control unit 109 updates the held PCI 07. Normal instruction processing is resumed from the value of PSW108.

Alternatively, as a result of the comparison, if word data 1 is better than TMO, the timing control unit 109 does not set word data 1 to COMPS 903, and instead sets the form change signal 121 according to the μ program command. INTC11
2, reset the form specification flag 119,
Terminate the microservice.

Since the interrupt request 116 flag is set and the format specification flag 119 is reset, the INTCl 12 sends a normal vectored interrupt request to the CPU 100.
, and starts the vectored interrupt processing described above.

In the interrupt processing executed here, COMPS903
In the processing when the setting (updating) of word data 1 to COMPS 903 is not performed, special processing such as storing that the setting of word data 1 to COMPS 903 is incomplete is performed.

After this, the timer 901 continues counting operation and COMP
When the value held in R904 matches the count value of timer 9010, a match signal 914 is output.

The match signal 914 is input to the output F/F 905, and by resetting the output F/F 905, the pulse output from the port P is set to a low level. Furthermore, the arrival signal 91
4 performs the above operations and also issues an interrupt request INTC.
Occurs for I l 2. (Figure 4 - Timing t2
．． t5. t8) When the INTC 112 accepts the match signal 9140 interrupt request, the interrupt request flag 1 corresponding to this source is set.
16 and activates the interrupt request signal 117.

The timing control unit 109 samples the interrupt request signal 117 at the end of instruction processing and is active.
The form indicating means 120 is sampled. Form indicating means 12
When it detects that 0 is 1” indicating a microservice, hold PC107゜PSWI 08 and press μR.
Generates a microphone service processing entry address for the OM 106 and starts the microservice.

Thereafter, processing is performed according to the μ program instructions of the microservice. Explanation of the processing step 4 will proceed along the flowchart of FIG. 2(b).

First, the header of the microservice whose interrupt source is the match signal 914 is read from a specific address in the data memory 114, and after detecting the position of the microphone 0 service channel, the microservice channel corresponding to this microservice processing is read. CO word data 2 of
Store in MPR904.

Next, in response to a command from the μ program, the timing control unit 109 outputs an interrupt request clear signal 118 to the INTC 112, resets the interrupt request flag 116, and ends the microservice processing.

When the microservice processing is completed, the timing control unit 109 resumes normal instruction processing from the values held in the tater PC 107 and P5W 108.

After this, the timer 901 continues counting and the CO
When the held value of MPT 902 matches the count value of timer 901, COMPT 901 outputs a match signal 912. This coincidence signal 912 is input to the timer 901,
The count value of the timer 901 is initialized to all "0". Furthermore, the coincidence signal 912 is input to the INTO 112t, m, and requests the INTC 112 to perform interrupt processing (Fig. 4 - timing t3.t6.t9).When the INTCl 12 accepts the coincidence signal 9120 interrupt request, this Interrupt request flag 11 corresponding to the source
6 and activates the interrupt request signal 117.

Timing control unit 109 samples interrupt request signal 117 at the end of instruction processing, and since it is active, samples format indicating means 120.

Here, since the format indicating means 120 is "0", the above-mentioned vector interrupt processing is activated.

In the interrupt processing started here, first, based on the information of the interrupt processing by the microservice based on the match signal 913, if the data update to the COMPS 903 is not completed, this processing is executed.

Next, when executing microservices activated by match signals 913 and 914, COMPS903 and COMPS
The data to be set in R904 is set to word data 1 and word data 2, and the interrupt processing is ended.

By executing this interrupt processing and the interrupt processing using the coincidence signals 913 and 914, control of pulse output for one cycle is completed. Therefore, by repeating this process, continuous pulse output control can be performed.

Additionally, microservices can be used to solve the problem that the next cycle's pulse output starts within the current cycle when the value set in COMPS903 is larger than the current timer count value. Determine this,
By generating a vector interrupt, it is possible to always correct the correct pulse output start timing through software processing.

Therefore, in the conventional pulse output pattern example shown in FIG. 7, the erroneous pulse generation part shown at period S2+83, that is, the period from timing tX-t6 to t7 to t8, does not appear, and the pulse waveform is as originally intended. A certain period S in Figure 4
A pulse output waveform as shown in 2 is obtained.

As explained above, the pulse generator of the present invention has COMPS903. It is possible to continuously output pulses by setting the output start timing and output end timing of the output pulse to be output in the next cycle using the interrupt process activated by a match of COMP 904.

In this embodiment, control regarding the period of the output pulse, that is, the setting data of COMPT902 is not updated, but COMPT902 is sequentially updated to predetermined word data during interrupt processing by the match signal 912 outputted by COMPT902. If this process is executed, it becomes possible to generate pulse outputs with different cycles for each cycle, so that more accurate control of pulse outputs can be realized in accordance with the application.

Next, a second embodiment of the present invention will be shown.

In this embodiment, the configuration and basic operation of the pulse generator are the same as those in the previous embodiment, so a detailed explanation will be omitted here.

The microservice and pulse output control operations in this embodiment will be explained below with reference to FIGS. 3(a), 3(c), and 4. However, the timer 901 is performing a counting operation, and the output F/F 905
It is assumed that has been reset and the pulse output from port P is at a low level.

Note that the configuration of the microservice channel in this example is the same as that in Example 1, so a description thereof will be omitted.

FIGS. 3(a) and 3(C) are flowcharts showing the microservice of this example, which is actually controlled by the μ program. Moreover, FIG. 4 is an example of a pulse output pattern in this embodiment.

Now, COMPS903 has a held value of timer 901.
When it matches the count value of , it outputs a match signal 913,
This match signal 913 sets the output F/F 905 to cause the pulse output from the boat P to be at a high level, and also generates an interrupt request to the INTC 112 . In response to this request, the INTC 112 outputs an interrupt request signal 117 to the timing control unit 109,
When the timing control unit 109 accepts this request, interrupt processing is activated and processing for updating the COMPS 903 setting data is performed.

(FIG. 4 - Timings tl, t4.t7) However, since this interrupt processing is the same as the interrupt processing activated by the match signal 913 in the first embodiment, the explanation will be omitted here.

(See FIG. 3(a) for the processing flow.) On the other hand, even during the interrupt processing activated by the match signal 913, the timer 904 continues counting,
When the held value of 04 matches the count value of timer 904, COMP 904 outputs a match signal 914 and outputs F.
By resetting /F905, the pulse output from Baud)P is set to low level, and the INTC112
Generates an interrupt request for. With this request I
The NTC 112 outputs an interrupt request signal 117 to the timing control unit 109, and when the timing control unit 109 accepts this request, interrupt processing is activated and the C
Processing for updating the setting data of the OMPR 904 is performed. (Figure 4 - Timings t2, t5, t8) In the interrupt processing started here, a microservice is first started. Hereinafter, the processing flow of the microservice will be explained along the flowchart of FIG. 3(C).

First, the match signal 914 is used as the interrupt source and the header to the microservice is read from a specific address in the data memory 114, the position of the microservice channel is detected, and word data 2 corresponds to this microservice processing. Recognize that

Next, the contents of COMPS 903 are read out, and this read value is compared with word data 2.

As a result of the comparison, if the value of word data 2 is smaller than the value read from COMPS903, word data 2
is stored in the COMPR 904, and then the microservice processing ends. (Timing t1 of period S1 in FIG.
and t2) When the microservice processing is completed, the timing control unit 109 resumes normal instruction processing from the held values of PCI O7 and PSW 108.

Alternatively, as a result of the comparison, the value of word data 2 is COMP
If it is larger than the read value from S 903, C
The microservice is terminated without updating data to the OMPR 904, and normal vector interrupt processing is started this time.

The vectored interrupt processing started here is such that the pulse output end timing of the next cycle to be set is longer than the pulse output start timing of the next cycle (which has already been set in the interrupt processing started by the previous match signal 913). In special processing when the timing is earlier, the content of word data 2 is corrected and the COMPR9 of the corrected data is
04 or, in some cases, COMPS 9
Processing such as data resetting to 03 is executed.

After the above process is executed, the vector interrupt process ends, and all interrupt processes activated by the match signal 914 end.

After this, when the value held in COMP 902 and the count value of timer 901 match, COMP Ta2 902 outputs a match signal 912 and requests interrupt processing, but the interrupt processing performed here is the same as in the first embodiment. Therefore, the explanation here will be omitted.

The pulse output in one cycle can be controlled by the interrupt processing activated by the coincidence signals 912, 913, and 914 as described above. Therefore, by repeatedly performing this operation, continuous pulse output control can be performed.

In addition, the data normally set as word data 1 and word data 2 is generated by program processing based on basic data prepared in advance in the data memory 114 and taking into account information from other peripheral hardware, etc. However, if there is an error in the basic data or the program in the word data generation process, the timing to end pulse output may vary from the timing to start pulse output, i.e. word data 1, to the count value of timer 901. It is possible that a combination of word data is set such that word data 2 has a smaller value.In such a case, the timing to end pulse output may come before the timing to start pulse output. If this happens, the pulse that starts output at the pulse output start timing will not have the timing to end the pulse output within the same cycle, and the pulse output will continue until the pulse output end timing of the next cycle. As described in the first embodiment, such a pulse output may cause serious problems for the controlled object.

In this embodiment, COMP90
In the interrupt processing activated by the coincidence signal 414 outputted by 4, if the above-mentioned pulse is expected to occur, the value of word data 2 to be set as the pulse output end timing of the next cycle is corrected. This prevents the occurrence of defective pulses.

〔Effect of the invention〕

As explained above, the pulse generator of the present invention processes interrupts for setting (updating) the start and end timings of pulse output using microservices and does not generate vectored interrupt requests, so the frequency of pulse output increases. However, the PC and P when transitioning to the interrupt processing program
When saving the SW to the stack or returning from the interrupt processing program to main processing, the contents of the stack are saved to the PC5PSW.
The CPU time is not occupied by the process of returning to .

In addition, if the data that the microservice attempts to set in the conveyor register that controls the start and end of pulse output for the timer count value may cause an incorrect pulse to be generated, By detecting this, activating a vectored interrupt based on the result, and performing special processing, it is possible to always generate normal pulses.

Furthermore, when the number of ports increases in the pulse generator, that is, the number of pulse outputs to be controlled increases,
For one cycle, interrupt processing for all ports can be handled by microservices. Therefore, regarding the increase in interrupt processing time due to an increase in the number of ports, interrupt processing can be executed in a shorter time than when all of this is executed by vector interrupt processing.

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram in the first embodiment of the present invention, Figure 2 is a configuration diagram of microservice processing form information in the embodiment, Figure 3 is an interrupt processing flowchart in the embodiment, and Figure 4 is the implementation Figure 5 is a pulse output cover diagram from port P in the example, Figure 5 is a pulse output diagram from port P in the conventional example, Figure 6 is a system configuration diagram in the conventional example, and Figure 7 is the peripheral hardware configuration in the conventional example. It is a diagram. 100.800...CPU, 101...
・ALU. 102...Temporary register, 103...
. . . General purpose register, 104 . . . Address buffer, 105 . . . μ address generation unit, 106.
...μROM, 107 ...PC, 108
...PSW, 109...marking/retiming control section, 110...data bus, 111...
Address bus, 112...INTC, 113.
...Program memory, 114...Data memory, 115...Peripheral hardware, 11
6... Interrupt request flag, 117...
Interrupt request/signal, 118... Interrupt request clear signal, 119... Form specification flag, 120...
...Form designation signal, 121...Form change signal, 901...Timer, 902,903゜9
04... Conveyor register, 912,913°914... Match signal, 905... Output F/F. Agent Patent attorney Susumu Uchihara = 38- Procedural amendment (method) % formula % Display of the case 1988 Patent Application No. 331527 2゜Name of the invention Data processing device 3゜Relationship to the case by the person making the amendment

Claims (1)

[Claims] a central processing unit including a program counter for holding an execution address of an instruction, a means for holding a program execution state, a general-purpose register, and a microprogram ROM; and an interrupt request generation circuit for asynchronously generating an interrupt processing request to the central processing unit. , a data processing device having a program memory, a data memory, and a peripheral circuit,
The peripheral circuit includes a timer, a plurality of comparison registers for comparing with the timer, and an output port for outputting pulses, and the interrupt request generation circuit generates predetermined data in addition to generating interrupt processing requests. means for generating a request for processing;
a mode specifying means for identifying the interrupt processing request and the predetermined data processing request; processing mode information specifying the processing mode of the predetermined data processing is stored in the data memory; When a request for the predetermined data processing is issued from the interrupt request generation circuit to the central processing unit, the central processing unit detects that the format instruction means is instructing the predetermined data processing; In order to do so, the instruction execution process is interrupted, and according to the processing type information, the predetermined data in the data memory is compared with the value of the timer or the value of the comparison register at the timing, and if the comparison result meets the predetermined condition. A data processing device comprising means for transferring data to said predetermined comparison register when said data processing device controls pulse generation from said output port.