JPS5850367B2 - input/output control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control device that performs input/output transfer of information at regular intervals.

A control device that is connected between a main storage device and an input/output device that requires data transmission and reception in synchronization with the rotation of a storage area, such as a magnetic drum device or a magnetic bubble device, and controls the transmission and reception of data. Broadly speaking, there are two types in terms of time regulations:
Different types of transfer control functions are required.

That is, (1) Data transfer control between the input/output device and the control device: Data transfer is performed periodically, and the processing necessary for unit data transfer needs to be performed within one cycle.

(2) Data transfer control between main storage and control device:
Since this is an asynchronous data transfer using a response confirmation method, some waiting time can be tolerated.

In conventional data transfer control, the above-mentioned functions were realized by wiring logic, so for example, as shown in Figure 1,
The input/output control device CU requires two types of dedicated control circuits MCTL and FCTL for parallel control, which has the drawback of increasing the amount of hardware and complicating the circuit configuration.

Note that MM is a main storage device, IO is an input/output device such as a magnetic bubble device, and data transfer between the input/output device IO and the input/output control device CU is performed using the input/output data buffer IOB under the control of the control circuit FCTL. Data transfer between the main memory device MM and the input/output control device CU was performed using the data buffer DBR under the control of the control circuit MCTL.

The ALU is an arithmetic circuit that performs address calculations, updates of the number of remaining words to be transferred, and the like.

The present invention switches processing routines using periodic interrupts,
The purpose is to provide an economical configuration that enables time-division multiplex processing of microprograms.

Examples will be described in detail below. FIG. 2 is a block diagram of an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same parts, MAR is a memory address register, μCT
L is a microprogram control circuit, TIM is a control timing generation circuit, 21 and 22 are control lines for confirming the data transfer between the input/output control unit CU and the main storage unit MM, and 23 is the input/output control unit CU. This is a control line that instructs the start and end of data transfer between the input/output device IO and the input/output device IO.

FIG. 3 shows a time chart for explaining the operation of the embodiment of the present invention, in which 301 is a periodic interrupt timing, 302 is a sequence of a non-priority processing microprogram, and 303 is a sequence of a priority processing microprogram. be.

The microprogram control circuit μCTL receives an interrupt from the control timing generation circuit TIM at timing 301 at regular intervals, and upon accepting this interrupt, temporarily suspends the microprogram being executed in sequence 302 and writes the program address at that time. It is saved to a stack (not shown), and in order to execute the program of sequence 303, the last address of sequence 303 of the previous cycle is taken out from the saved stack and set as the start address, and the program is executed.

This sequence 303 is a priority processing routine, which is a microprogram sequence that executes data transfer control between the input/output device ■0 and the input/output control device CU, and processes are periodically performed within a specified time based on this sequence. Input/output data buffer IOB and input/output device I that must be
This is executed as a series of sequences such as sending and receiving data to and from O, sending a transfer control command via the control line 23, etc.

When data transmission and reception between the input/output control unit CU and the input/output unit IO is completed, the main The last address of the microprogram for data transmission/reception control between the storage device MM and the input/output control device CU is saved to the stack, and at timing 30 of the previous cycle.
The address of sequence 302 saved to the stack in step 1 is retrieved.

Sequence 302 is a non-priority routine and the arithmetic circuit ALU
Use to update the memory address, update the remaining number of transfers,
Sending and receiving data between main memory device MM and data buffer DBR, sending memory address stored in advance in memory address register MAR to main memory device MM, control line 2
1 and 22, a microprogram is executed to control response confirmation as to whether transfer is possible or not.

In addition to the data transfer control mentioned above, startup of input/output device IO,
Pre-transfer processing (in the case of magnetic bubbles, starting the rotation operation (rotating magnetic field), searching for the access position, etc.), post-transfer processing (in the case of magnetic bubbles, stopping the rotation operation (rotating magnetic field), moving data to the specified position) (e.g., rewriting) can often be normalized to an interval that is an integral multiple of the fixed cycle timing 301. The counter is updated, and when the count of the counter reaches a predetermined value, the previous operation is started.

That is, processes that require a longer time interval than the data transfer cycle can be managed by a microprogram-controlled counter.

Therefore, the configuration can be simplified compared to the conventional method in which a counting circuit and a match circuit are provided and interrupts are applied at predetermined time intervals to operate the control circuit.

Furthermore, fetching of channel control words and the like necessary for the input/output operation startup sequence, termination/reporting sequence, and storing channel status words in memory are executed in sequence 302.

As explained above, according to the present invention, periodic input/output operations with strict time regulations and asynchronous input/output operations can be controlled in a time-sharing manner by a common microprogram control circuit. Since the system is unified, the circuit configuration is simpler than in the conventional example which required each control circuit, and the device can be made more economical.

Therefore, the control time interval can be normalized by a long period and an integral multiple of a predetermined period, such as an input/output control device that controls an input/output device that performs periodic input/output operations such as a magnetic drum device or a magnetic bubble device, and a typewriter device. The present invention can be applied to an input/output control device that controls an input/output device that performs input/output operations to achieve economicalization.

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining data transfer control including a conventional input/output control device, Fig. 2 is a block diagram for an embodiment of the present invention, and Fig. 3 is a time diagram for explaining the operation of the embodiment of the present invention. It is a chart. IO is an input/output device, CU is an input/output control device, MM is a main memory, IOB is an input/output data buffer, DBR is a data buffer, ALU is an arithmetic circuit, MAR is a memory address register, μCTL is a microprogram control circuit,
TIM is a control timing generation circuit.

Claims (1)

[Claims] 1. In an input/output control device that controls an input/output device that inputs/outputs information at regular intervals, an interrupt is received at regular intervals, and the first microcontroller that has been executing At the same time as saving the program address, execution of the second microprogram is resumed from the address specified by the last instruction of the second microprogram started in the previous cycle, and the second microprogram to be processed within the cycle is After the execution of the instruction group of the second microprogram is completed, the start address of the second microprogram to be executed in the next cycle is saved, the saved address of the first microprogram is restored, and the first microprogram is started from this address. An input/output control device characterized by comprising a microprogram control circuit that executes a program.