JPH02164045A - Packaging of solder bump component - Google Patents
Packaging of solder bump componentInfo
- Publication number
- JPH02164045A JPH02164045A JP63321300A JP32130088A JPH02164045A JP H02164045 A JPH02164045 A JP H02164045A JP 63321300 A JP63321300 A JP 63321300A JP 32130088 A JP32130088 A JP 32130088A JP H02164045 A JPH02164045 A JP H02164045A
- Authority
- JP
- Japan
- Prior art keywords
- solder bump
- bump
- positioning
- pad
- printed board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000679 solder Inorganic materials 0.000 title claims description 36
- 238000004806 packaging method and process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims description 14
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000005476 soldering Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
- H01L2224/17051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概 要〕
ＬＳＩ、ＩＣ等の半田バンプ部品をプリント板等に半田
付は実装する際に適用される半田バンプ部品の実装方法
に関し、
位置決め治具等を使用することなく、しかも高精度に半
田バンプ部品をプリント板に実装し得る実装方法の提供
を目的とし、
前記半田バンプ部品側のパッケージにはその下面から上
面に貫通するスルーホールを設け、またプリント板側に
は該スルーホールに対応する位置決め用パッドを設け、
前記半田バンプ部品をプリント板に実装するに際しては
、前記スルーホールと前記位置決め用パッド間に位置決
めバンプを配置し、前記信号端子用パッドと前記プリン
ト板側の配線パッド間には該位置決めバンプよりも小径
の接続用バンプを配置するようにしたことを特徴とする
特
〔産業上の利用分野〕
本発明は、例えばＬＳＩ、ＩＣ等のように、パッケージ
の面に複数個の信号端子用パッドを有して成る半田バン
ブ部品を、プリント板に実装する際に適用される半田バ
ンプ部品の実装方法に関する。[Detailed Description of the Invention] [Summary] Regarding the mounting method of solder bump parts applied when soldering solder bump parts such as LSI, IC, etc. to a printed board etc., the use of a positioning jig etc. The purpose of the present invention is to provide a mounting method that can mount solder bump components on a printed board with high precision without any problems. is provided with a positioning pad corresponding to the through hole,
When mounting the solder bump component on a printed board, a positioning bump is placed between the through hole and the positioning pad, and a distance between the signal terminal pad and the wiring pad on the printed board is larger than the positioning bump. [Industrial application field] The present invention is characterized in that small-diameter connection bumps are arranged. [Industrial application field] The present invention is applicable to a package having a plurality of signal terminal pads on the surface of the package, such as an LSI, an IC, etc. The present invention relates to a method for mounting solder bump components that is applied when mounting solder bump components formed by the above on a printed circuit board.
第４図（ａ）と申）と（Ｃ１は従来の半田バンプ部品の
一構成例を示す図であって、（ａ）は斜視図、（ｂｌは
これを下面から見た平面図、（０）は（ｂｌ図のＢ−Ｂ
線断面図である。また第５図は従来のプリント板の一構
成例を示す要部斜視図であり、第６図は従来の半田バン
プ部品の実装方法の一例を示す要部側断面図である。Figure 4 (a) and (C1) are diagrams showing an example of the configuration of a conventional solder bump component, in which (a) is a perspective view, (bl is a plan view of this from the bottom, and (0 ) is (B-B in bl diagram)
FIG. Further, FIG. 5 is a perspective view of a main part showing an example of the configuration of a conventional printed board, and FIG. 6 is a side sectional view of a main part showing an example of a conventional method for mounting solder bump components.
第４図（ａ）と（ｂ）と（Ｃ）に示すように、従来の半
田バンプ部品２５は、その下面側に複数個の信号端子用
パッド１を備えると共に、該信号端子用パッド１上には
それぞれ接続用バンプ３が配置されている。As shown in FIGS. 4(a), (b), and (C), the conventional solder bump component 25 has a plurality of signal terminal pads 1 on its lower surface side, and also has a plurality of signal terminal pads 1 on its lower surface. Connecting bumps 3 are arranged on each of the connecting bumps 3.
一方、前記半田バンプ部品２５が実装される側のプリン
ト板４０には、第５図に示すようなりフローパッド１８
が前記接続用バンブ３対応に設けられている。On the other hand, as shown in FIG.
is provided corresponding to the connection bump 3.
以下、第６図に基づいて従来の半田バンプ部品の実装方
法（以下実装方法と称する）を説明する。Hereinafter, a conventional method for mounting solder bump components (hereinafter referred to as a mounting method) will be explained based on FIG.
■、プリント板４０上に、半田バンプ部品２５の信号端
子用パッド１をリフローパッド１８上に位置決めするガ
イド治具３０を装着する。(2) A guide jig 30 for positioning the signal terminal pad 1 of the solder bump component 25 on the reflow pad 18 is mounted on the printed board 40.
■、半田バンブ部品２５のパッケージ１０をガイド治具
３０に沿って矢印り方向に挿入する。(2) Insert the package 10 of the solder bump component 25 along the guide jig 30 in the direction of the arrow.
■、これをベーパーリフロー装置（高温度の蒸気で半田
を溶融して半田付けを行う装置）内にセットする。そし
て高温度蒸気によって接続用バンブ３を溶融させ、信号
端子用パッド１とリフローパッド１８とを半田付は接続
する。(2) Set this in a vapor reflow device (a device that performs soldering by melting solder with high-temperature steam). Then, the connecting bump 3 is melted by high-temperature steam, and the signal terminal pad 1 and the reflow pad 18 are connected by soldering.
といった方法で実装を行っていた。It was implemented in such a way.
しかしながら、上記従来の実装方法には下記の問題点が
ある。即ち、
■、半田バンプ部品２５の形状に応じたガイド治具３０
を準備する必要がある。However, the conventional mounting method described above has the following problems. That is, (2) a guide jig 30 according to the shape of the solder bump component 25;
need to be prepared.
■、ガイド治具３０をプリント板４０上に高精度で位置
決めするための二次的な手段が必要である。(2) Secondary means for positioning the guide jig 30 on the printed board 40 with high precision is required.
■、ガイド治具３０で位置決めするためには、半田バン
プ部品２５自体の寸法を高精度化する必要があり、従っ
て半田バンプ部品２５の製造コストがアップする。(2) In order to perform positioning using the guide jig 30, it is necessary to increase the precision of the dimensions of the solder bump component 25 itself, which increases the manufacturing cost of the solder bump component 25.
■、ガイド治具３０によって半田溶融時のセルフアライ
メントが抑制され、リフローパッド１８と信号端子用パ
ッド１間にズレを生じる危険性がある。(2) Self-alignment during solder melting is suppressed by the guide jig 30, and there is a risk of misalignment between the reflow pad 18 and the signal terminal pad 1.
本発明は上記従来の実装方法における問題点を解決する
ためになされたものである。The present invention has been made to solve the problems in the conventional mounting method described above.
本発明による実装方法は第１図、第２図および第３図に
示すように、半田バンブ部品１５例のパッケージ１０に
は当該パッケージ１０の下面から上面に貫通するスルー
ホール５を設け、前記プリント板２０側には該スルーホ
ール５に対応する位置決め用パッド１９を設け、半田バ
ンプ部品１５をプリント板２０に実装するに際しては、
前記スルーホール５と位置決め用パッド１９間に位置決
めバンプ２を配置し、前記信号端子用パッドｌと前記プ
リント板２０側のりフローパッド１８間には前記位置決
めバンプ２よりも小径の接続用バンプ３を配置する構成
になっている。As shown in FIG. 1, FIG. 2, and FIG. 3, the mounting method according to the present invention includes providing a through hole 5 penetrating from the bottom surface of the package 10 to the top surface of the package 10 of 15 solder bump components. A positioning pad 19 corresponding to the through hole 5 is provided on the board 20 side, and when mounting the solder bump component 15 on the printed board 20,
A positioning bump 2 is arranged between the through hole 5 and the positioning pad 19, and a connection bump 3 having a smaller diameter than the positioning bump 2 is arranged between the signal terminal pad 1 and the adhesive flow pad 18 on the printed board 20 side. It is configured to be placed.
このように、本発明による実装方法は、スルーホール５
と位置決め用パッド１９間に配置される位置決めバンプ
２の直径を、信号端子用バンドｌとリフローパッド１８
間に配置される接続用バンプ３の直径よりも大きくしで
あるので、加熱によって溶融した位置決めバンプ２がス
ルーホール５内に侵入してそこにガイド構造が構成され
る。そしてこの位置決めバンプ２の誘導によって信号端
子用パッド１がリフローパッド１８上に位置決めされる
ことになるため、半田バンプ部品１５とプリント板２０
間に位置ズレが発生し難い。In this way, the mounting method according to the present invention provides through-hole 5
The diameter of the positioning bump 2 placed between the signal terminal band l and the reflow pad 18
Since the diameter of the connecting bump 3 is larger than that of the connecting bump 3 disposed between them, the positioning bump 2 melted by heating enters the through hole 5 to form a guide structure there. Since the signal terminal pad 1 is positioned on the reflow pad 18 by the guidance of the positioning bump 2, the solder bump component 15 and the printed board 20 are
Misalignment is unlikely to occur between the two.
以下実施例図に基づいて本発明の詳細な説明する。 EMBODIMENT OF THE INVENTION The present invention will be described in detail below based on embodiment figures.
第１図（ａｌと申）は本発明に用いる半田バンプ部品の
一構成例を示す平面図とそのＡ−Ａ線部の断面形状を示
す要部側断面図、第２図は本発明に用いるプリント板の
一構成例を示す要部斜視図、第３図（ａｌと（ｂｌと（
ｃ＋は本発明による実装方法を示す要部側断面図である
が、前記第４図、第５図及び第６図と同一部分について
は同一符号を付している。FIG. 1 (al and double) is a plan view showing a configuration example of a solder bump component used in the present invention and a side sectional view of the main part showing the cross-sectional shape of the solder bump component used in the present invention, and FIG. FIG. 3 is a perspective view of essential parts showing an example of the configuration of a printed board (al, (bl, ()
c+ is a sectional side view of a main part showing the mounting method according to the present invention, and the same parts as in FIGS. 4, 5, and 6 are given the same reference numerals.
第１図（ａｌと（ｂ）に示すように、本発明に用いる半
田バンプ部品１５は、パッケージｌＯの下面に設けられ
た複数個の信号端子用パッド１の外側に複数個（この例
では４個）のスルーホール５が形成されている。そして
、該スルーホール５上には位置決めバンプ２が配置され
、一方の信号端子用パッド１上には前記位置決めバンプ
２よりも小径の接続用バンプ３が配置されている。なお
、これら位置決めバンプ２と接続用バンプ３は、例えば
半田付は時に使用する周知のフラックス（図示せず）等
を用いて所定の位置に接着配置されている。As shown in FIGS. 1A and 1B, a plurality of solder bump components 15 used in the present invention (in this example, four Through-holes 5 (5) are formed.A positioning bump 2 is arranged on the through-hole 5, and a connection bump 3 having a smaller diameter than the positioning bump 2 is placed on one of the signal terminal pads 1. Note that these positioning bumps 2 and connection bumps 3 are adhesively arranged at predetermined positions using, for example, a well-known flux (not shown) that is sometimes used in soldering.
一方、本発明に用いるプリント板２０は、第２図に示す
ように、前記信号端子用パッド１対応に設けられたりフ
ローパッド１８と、前記スルーホール５対応に設けられ
た位置決め用パッド１９を備えている。On the other hand, the printed board 20 used in the present invention includes a flow pad 18 provided corresponding to the signal terminal pad 1 and a positioning pad 19 provided corresponding to the through hole 5, as shown in FIG. ing.
以下第３図（ａ）と（′ｂ）と（Ｃ）に基づいて本発明
による実装方法を説明する。The mounting method according to the present invention will be explained below based on FIGS. 3(a), ('b), and (C).
■、第３図（ａｌに示すように、プリント板２０の位置
決め用パッド１９上に、半田バンプ部品１５側のスルー
ホール５上に配置された位置決めバンプ２を位置決めす
る。(2) As shown in FIG. 3 (al), the positioning bump 2 placed on the through hole 5 on the solder bump component 15 side is positioned on the positioning pad 19 of the printed board 20.
０１次に位置決めバンプ２にペーパーを吹き付けてこれ
を第３図（ｂ）に示すように溶融させる。これによって
溶けた位置決めバンプ２の一部はスルーホール５内に侵
入する。01 Next, paper is sprayed onto the positioning bump 2 to melt it as shown in FIG. 3(b). As a result, a portion of the melted positioning bump 2 enters the through hole 5.
■０位置決めバンプ２がスルーホール５内に侵入したこ
とによって、半田バンプ部品１５とプリント板２０は互
いに位置決めされる。この時、信号端子用パッド１上に
配置されている小径の接続用バンプ３はプリント板２０
のリフローパッド１８と漸く接触状態になる。(2) As the positioning bump 2 enters the through hole 5, the solder bump component 15 and the printed board 20 are positioned with respect to each other. At this time, the small diameter connection bump 3 placed on the signal terminal pad 1 is connected to the printed board 20.
It finally comes into contact with the reflow pad 18 of.
■、全全体ペーパー加熱する。これによって接続用バン
プ３が溶融し、信号端子用パッド１とリフローパッド１
８とを第３図（Ｃ）に示すように接合する。■Heat the entire paper. As a result, the connection bump 3 is melted, and the signal terminal pad 1 and the reflow pad 1 are melted.
8 and are joined as shown in FIG. 3(C).
なお、接続用バンプ３がこの状態になった時には位置決
めバンプ２はスルーホール５内を完全に満たす位置まで
上昇している。Note that when the connection bump 3 is in this state, the positioning bump 2 has risen to a position that completely fills the inside of the through hole 5.
■、この時点でペーパー加熱を停止し、冷却後にこれを
取り出す。(2) Stop heating the paper at this point and take it out after cooling.
以上の実施例は、位置決めバンプ２と接続用バンプ３の
両方をパッケージ１０側に配置した形にしているが、こ
れらをプリント板２０側に配置するようにしてもかまわ
ない。In the above embodiment, both the positioning bumps 2 and the connection bumps 3 are arranged on the package 10 side, but they may be arranged on the printed board 20 side.
以上の説明から明らかなように本発明によれば、ガイド
治具等の位置決め治具を用いることなしに半田バンプ部
品をプリント板に正確に位置決めできる上、半田付は中
に半田バンプ部品が治具等に影響されてズレルようなこ
とが無いため、作業効率と品質の向上に責するところが
頗る大である。As is clear from the above description, according to the present invention, the solder bump components can be accurately positioned on the printed board without using a positioning jig such as a guide jig, and the solder bump components can be fixed during soldering. Since there is no misalignment due to the influence of ingredients, etc., it has a great deal of responsibility for improving work efficiency and quality.
第１図（ａ）と（ト））は本発明に用いる半田バンプ部
品の一構成例を示す平面図とそのＡ−Ａ線部の断面形状
を示す要部側断面図、
第２図は本発明に用いるプリント板の一構成例を示す要
部斜視図、
第３図（ａ）と（ｂｌと（Ｃ）は本発明による実装方法
を示す要部側断面図、
第４図（ａ）とｆｂ）と（Ｃ）は従来の半田バンプ部品
の構成例を示す斜視図と平面図とそのＢ−Ｂ線部の断面
形状を示す要部側断面図、
第５図従来のプリン１〜板の一構成例を示す要部斜視図
、
第６図は従来の半田バンプ部品の実装方法の一例を示す
要部側断面図である。
図において、■は信号端子用パッド、
２は位置決めバンプ、
３は接続用バンプ、
５はスルーホール、
１０はパッケージ、
１５と２５は半田バンプ部品、
１８はリフローパッド、
１９は位置決め用パッド、
２０と４０はプリント板、
３０はガイド治具、
をそれぞれ示す。
（α）
（Ｃ）
半発朗１；ｊ３寅装方址Ｃイ図
第３図
２１発口耳ｔ；１１翫・１八シク°八”＞７’書Ｐ８１
の−を驚Ｊ久゛づ列閏第１図
ＪｆＥ’Ｊ（＋４１＋・ｓ＞ ソｚｋｚ！＊−ＪＡＲ：
イｆ−ＪＱζ］第２図
ＬＡミＪＩＩＩＩ父ン＞９品ら一蹟へ゛づ列Ｇワ第４図FIGS. 1(a) and (g)) are a plan view showing an example of the configuration of a solder bump component used in the present invention, and a side sectional view of the main part showing the cross-sectional shape of the part taken along line A-A. FIG. FIGS. 3(a) and 3(c) are side sectional views of essential parts showing a mounting method according to the present invention; FIG. 4(a) and fb) and (C) are a perspective view and a plan view showing an example of the configuration of a conventional solder bump component, and a side sectional view of the main part showing the cross-sectional shape of the B-B line. FIG. 6 is a perspective view of a main part showing an example of a configuration. FIG. 6 is a side sectional view of a main part showing an example of a conventional mounting method for solder bump components. In the figure, ■ is a signal terminal pad, 2 is a positioning bump, 3 is a connection bump, 5 is a through hole, 10 is a package, 15 and 25 are solder bump parts, 18 is a reflow pad, 19 is a positioning pad, 20 and 40 indicate a printed board, and 30 indicate a guide jig, respectively. (α) (C) Half fire 1;
I was surprised at the -J long column 1st figureJfE'J(+41+・s> Sozkz!*-JAR:
[F-JQζ] Figure 2 LA Mi JIII Father > 9 items etc. Row G Figure 4
Claims (1)
１）を有して成る半田バンプ部品（１５）をプリント板
（２０）等に実装する際に適用される方法であって、前
記半田バンプ部品（１５）側のパッケージ（１０）には
当該パッケージ（１０）の下面から上面に貫通するスル
ーホール（５）を設け、前記プリント板（２０）側には
該スルーホール（５）に対応する位置決め用パッド（１
９）を設け、前記半田バンプ部品（１５）をプリント板
（２０）に実装するに際しては、前記スルーホール（５
）と位置決め用パッド（１９）間に位置決めバンプ（２
）を配置し、前記信号端子用パッド（１）と前記プリン
ト板（２０）のリフローパッド（１８）間には該位置決
めバンプ（２）よりも小径の接続用バンプ（３）を配置
するようにしたことを特徴とする半田バンプ部品の実装
方法。A plurality of signal terminal pads (
1) is a method applied when mounting a solder bump component (15) having the above described solder bump component (15) on a printed board (20), etc. (10) is provided with a through hole (5) penetrating from the bottom surface to the top surface, and a positioning pad (1) corresponding to the through hole (5) is provided on the printed board (20) side.
9), and when mounting the solder bump component (15) on the printed board (20), the through hole (5) is provided.
) and the positioning bump (2) between the positioning pad (19).
), and a connection bump (3) having a smaller diameter than the positioning bump (2) is arranged between the signal terminal pad (1) and the reflow pad (18) of the printed board (20). A method for mounting solder bump components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63321300A JP2555720B2 (en) | 1988-12-19 | 1988-12-19 | Solder bump component mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63321300A JP2555720B2 (en) | 1988-12-19 | 1988-12-19 | Solder bump component mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02164045A true JPH02164045A (en) | 1990-06-25 |
| JP2555720B2 JP2555720B2 (en) | 1996-11-20 |
Family
ID=18131036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63321300A Expired - Fee Related JP2555720B2 (en) | 1988-12-19 | 1988-12-19 | Solder bump component mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2555720B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04314355A (en) * | 1991-04-12 | 1992-11-05 | Nec Corp | Chip carrier and soldering method thereof |
| EP0651937A4 (en) * | 1992-06-19 | 1995-08-30 | Motorola Inc | Self-aligning electrical contact array. |
| JP2009054611A (en) | 2007-08-23 | 2009-03-12 | Fujitsu Ltd | Mounting structure, method for manufacturing the same, semiconductor device, and method for manufacturing the same |
| US7545044B2 (en) | 2003-02-24 | 2009-06-09 | Hamamatsu Photonics K.K. | Semiconductor device and radiation detector employing it |
| US7663113B2 (en) | 2003-02-27 | 2010-02-16 | Hamamatsu Photonics K.K. | Semiconductor device and radiation detector employing it |
| US7838994B2 (en) | 2003-02-24 | 2010-11-23 | Hamamatsu Photonics K.K. | Semiconductor device and radiation detector employing it |
-
1988
- 1988-12-19 JP JP63321300A patent/JP2555720B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04314355A (en) * | 1991-04-12 | 1992-11-05 | Nec Corp | Chip carrier and soldering method thereof |
| EP0651937A4 (en) * | 1992-06-19 | 1995-08-30 | Motorola Inc | Self-aligning electrical contact array. |
| US7545044B2 (en) | 2003-02-24 | 2009-06-09 | Hamamatsu Photonics K.K. | Semiconductor device and radiation detector employing it |
| US7838994B2 (en) | 2003-02-24 | 2010-11-23 | Hamamatsu Photonics K.K. | Semiconductor device and radiation detector employing it |
| US7663113B2 (en) | 2003-02-27 | 2010-02-16 | Hamamatsu Photonics K.K. | Semiconductor device and radiation detector employing it |
| JP2009054611A (en) | 2007-08-23 | 2009-03-12 | Fujitsu Ltd | Mounting structure, method for manufacturing the same, semiconductor device, and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2555720B2 (en) | 1996-11-20 |
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