JPH02162731A - Thin film element substrate - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to thin film element substrates, and in particular, to interlayer wiring in a liquid crystal device in which a driving element is a TPT (thin film transistor) connected by multilayer wiring on a transparent glass substrate. The present invention relates to a structure suitable for improving the insulation properties of.

[Conventional technology]

For information on flattening technology for wiring and glabellar insulating films in LSIs using semiconductors such as silicon as substrates, see, for example, Nikkan Se.
m1-Conductor World (1987, 3
) discussed in PP36-PP42.

[Problem to be solved by the invention]

On the other hand, there has been active development of liquid crystal display devices in which TPT (thin film transistors) are formed in a matrix on an insulating substrate such as glass to drive liquid crystals to display images.

A cross section of a device according to the prior art is shown in FIG. 2. A source/drain layer 6. is formed on a transparent glass substrate 1. Channel layer 7. Gate insulating film 8. A TPT consisting of gate electrode 9 is formed. After that, the lower layer wiring 2 is used as the lead line of the gate electrode 9.
The upper layer wiring 2b is formed as a lead line of the source/drain layer 6 via the interlayer IHEi3. Also,
This interlayer insulating film 3 also has transparent electrodes 10a and 10b.
It acts as a dielectric capacitor. This capacitance (holding capacitance) is due to the increase in resistivity of the liquid crystal during display operation, TPT
Prevents contrast from decreasing due to increased off-state current, etc. It is desirable that the interlayer insulating film 3 be thick at wiring intersections in order to ensure voltage resistance, but since this results in a decrease in storage capacitance, the maximum value of the thickness is determined from the required minimum value of storage capacitance. Interlayer insulation 11! ! 3, at the wiring intersection, the film thickness t2 at the end of the lower wiring 2a becomes smaller than the film thickness t3 at the flat part due to the step difference in the film thickness to of the lower wiring 2a. As a result, the electric field concentrates at the end of the lower layer wiring 2a, causing dielectric breakdown.

A known example aimed at bringing t2 closer to 8 is given in "Recent Trends in Multilayer Wiring Technology" Monthly Sem1c.
onductor World (1987, 3)
PP36 to PP42. An example of this is shown in FIG. 3, in which an insulating film 12 for wiring embedding is formed on a silicon substrate 11, and the lower wiring 2a is buried in four parts of the insulating film 12 for wiring embedding by tx of the film thickness to, and the steps of the lower wiring are to, thereby bringing the film thickness tz of the living room insulating film at the end of the lower layer wiring closer to 78.

However, in the TPT structure shown in FIG. 2, the structure shown in FIG. 3 is insufficient in order to simultaneously ensure voltage resistance and storage capacity at wiring intersections, and t2≧t8
Must.

An object of the present invention is to provide a thin film element substrate that can prevent dielectric breakdown due to electric field concentration.

[Means to solve the problem]

A structure for achieving the above purpose is shown in FIG.

After forming TPT, a recess 5 is formed in the glass substrate 1,
The depth tl of the recess 5 is formed deeper than the film thickness to of the lower wiring 2a, the lower wiring 2a is selectively buried in the recess 5, and a local interlayer insulating film 3a is formed by spin coating a liquid organic resin in the recess 5. How to do this, or mask areas other than recess 5 before CV
Embed by the method of depositing in step D. Thereafter, the interlayer upper insulating film 3b is CV
It is formed by means such as D. Furthermore, upper layer wiring 2b is formed to obtain the structure shown in FIG.

In the structure shown in FIG. 1, the interlayer insulating film tz at the end of the lower wiring at the wiring intersection shown in FIG.
The above objectives are achieved.

[Effect]

As described above, the important characteristics of the TPT living room insulating film are the insulating properties at the interconnection intersections and the dielectric properties at the storage capacitor sections. In the structure of FIG. 1, by setting t2> to 8, the insulation of the wiring intersection is improved and the capacitance of the storage capacitor section is increased, so that the characteristics of both the wiring intersection and the storage capacitor section are improved.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. A polysilicon layer is deposited on a transparent glass substrate 1.

After patterning, gate insulating film 8. Gates 9 are successively deposited and patterned. P (phosphorous) is implanted from the substrate surface by ion implantation, and the source/drain layer 6. is self-aligned. Forming gate 9 (a) Figure), a
) In the figure, photoresist is formed using photolithography technology in areas other than those where the underlying wiring is to be formed. F(
RIE (React) using fluorine) gas as raw material
ive Ion Etching) A recess 5 is formed to a depth tx=6000 by etching (Figure (b)). b)
In the figure, the film thickness of AQ-8i is o by sputtering.
= 3000 people will be formed. Afl-5i in the recess 5 acts as the lower layer wiring 2a (see figure Q). C) In the figure,
By peeling off the photoresist with adhesive tape,
Unnecessary AQ-8i on the resist is also removed at the same time.

Thereafter, the lower electrode 10a of the storage capacitor is formed and patterned by sputtering, and then liquid polyimide is spin-coated and polymerized by heating, so that it is selectively deposited in the recesses 5 of wiring intersections, the stepped portions of TPT, etc. At wiring intersections, ts
It has the effect of filling in the difference in height between -to. P S G (Ph
Ospho 5ilicate-Glass) at normal pressure C
4,000 people are formed using the VD method, and the thickness t2 of the insulating film between the eyebrows at the wiring intersection is larger than the interlayer insulating film thickness L8 of the storage capacitor part (Fig. d)).
MA Q −
Open a window for contact with the Si wiring, and
Deposit and pattern Q-Si by sputtering (e
)figure).

In the figures b) and c), the lift-off method is used as a means of embedding the lower layer wiring 2a in the recess 5, and sputter etching is performed on the flat surface and the stepped side surface.

A bias sputtering method using a plating speed, a method in which a plating dissolving medium is formed only at the bottom of the recess, and metal is selectively buried in the recess by electroless plating are applicable.

As a method for burying the local interlayer insulating film 3a in the recess 5 where the lower wiring 2a is filled, in addition to the organic resin coating method, an insulating film is deposited so as to completely fill the recess 5, and a flat film such as photoresist is deposited on top of the insulating film to completely fill the recess 5. Etch-back method in which a sacrificial film is applied and the sacrificial film and insulating film are etched at approximately the same etching speed to flatten the surface, selective CVD method in which an insulating film is deposited by CVD while masking areas other than the recessed parts, etc. is applicable.

FIG. 5 shows another embodiment of the present invention in which the depth 4 from the inner bottom of the recess at the wiring intersection to the upper interlayer insulating film 3b is smaller than the recess groove depth tl.

This method cannot be applied to a semiconductor substrate normally used in an LSI or the like because electric leakage occurs at the four side walls, but it is applicable to the substrate 1 used in a TPT because it uses an insulating material such as glass. It is obvious that the deeper the recess, the better the insulation of the wiring intersection.

〔Effect of the invention〕

According to the present invention, it is possible to improve the insulation of the interconnect intersection and increase the capacitance of the storage capacitor section.

Since there is no wiring level difference at the wiring intersection, the step coverage of the glabellar insulating film used can be ignored, and the range of insulating film selection is expanded.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a substrate according to an embodiment of the present invention. FIGS. 2 and 3 are cross-sectional views of conventional substrates. FIGS. 4 and 5 show an embodiment of the present invention. 1... Glass substrate, 2a... Lower layer wiring, 2b...
Upper layer wiring, 3a...Local interlayer insulating film, 3b... Upper interlayer insulating film, 4... Photoresist, 5... Concavity, 6
...source/drain layer, 7...channel layer, 8.
...Gate insulating film, 9...Gate, 10a...Storage capacitor lower layer electrode, 10b...Storage capacitor upper layer electrode, 11.
...Silicon substrate, 12...Insulating film for wiring embedding.

Claims (1)

[Claims] 1. In a thin film element substrate in which two or more layers of conductive wiring are formed on a substrate, and the wirings have overlapping portions while being insulated by an interlayer insulating film on the plane of the substrate, at least the portion where the wirings overlap Some of the lower wiring and interlayer insulation film of
A thin film element substrate characterized by being embedded in an insulating material below a substrate reference plane. 2. The thin film element substrate according to claim 1, wherein the substrate is a transparent insulating substrate. 3. In claim 1, the thin film element substrate includes a capacitive part using an insulating film, for example, an interlayer insulating film as a dielectric, and the thickness of the interlayer insulating film of the capacitive part is at least as large as that of the interlayer insulating film in the portion where the wiring overlaps. A thin film element substrate characterized by being thinner than the thickness. 4. The thin film element substrate according to claim 1, wherein the thin film element is a thin film transistor.