JPH0373531A - Manufacture of semiconductor device provided with multilayer wiring structure - Google Patents
Manufacture of semiconductor device provided with multilayer wiring structureInfo
- Publication number
- JPH0373531A JPH0373531A JP21034389A JP21034389A JPH0373531A JP H0373531 A JPH0373531 A JP H0373531A JP 21034389 A JP21034389 A JP 21034389A JP 21034389 A JP21034389 A JP 21034389A JP H0373531 A JPH0373531 A JP H0373531A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- interlayer insulating
- film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 9
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線構造を有する半導体装置の製造方法に
関し、特に多層配線構造におけ５る下層配線の段差を軽
減させる製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure, and particularly to a manufacturing method for reducing steps in lower layer wiring in a multilayer wiring structure.
従来の多層配線構造を有する半導体装置の製造方法では
、コンタクトホール部などにおいて大きな表面段差を持
つ下層の配線層の上にリン・ボロン等を含んだシリゲー
トガラス等の層間絶縁膜を被着し、熱処理によりこの層
間絶縁膜をリフローした後、上層の配線層を形成してい
た。In conventional manufacturing methods for semiconductor devices with multilayer wiring structures, an interlayer insulating film such as silicate glass containing phosphorus, boron, etc. is deposited on a lower wiring layer that has large surface steps such as in contact holes. After reflowing this interlayer insulating film by heat treatment, the upper wiring layer was formed.
上述した従来の製造方法は配線層間絶縁膜のりフローの
みで段差軽減を図っているので、段差軽減が十分ではな
（、高集積化・微細加工化が進むにつれて配線段切れや
配線間ショートが起こるという欠点がある。The conventional manufacturing method described above attempts to reduce the level difference only by using the flow of the insulating film between wiring layers, so the reduction of the level difference is not sufficient (as higher integration and microfabrication progress, interconnect line breakage and short circuits occur). There is a drawback.
したがって配線下地における段差をより一層緩和させ、
それによって配線の加工精度の向上を計リ、段差におけ
る上層配線の配線切れや段差での層間絶縁層の欠陥にも
とすく配線間ショート、段差でのエツチング残りによる
上層配線間のショートの起りにくい半導体装置の製造方
法を提供する必要がある。Therefore, the level difference in the wiring base is further alleviated,
This improves the processing accuracy of the wiring, making it easier to prevent wiring breaks in the upper layer wiring at steps and defects in the interlayer insulation layer at steps, making shorts between wirings less likely to occur, and shorts between upper layer wirings due to etching residue at steps. There is a need to provide a method for manufacturing a semiconductor device.
本発明による多層配線構造を有する半導体装置の製造方
法は、下部配線層となる導電層をコンタクトホールを有
する絶縁層上に被着し、コンタクトホール部を含む部分
において上記導電層の表面に生じている凹部に絶縁体を
埋め込み、その後で上記導電層をパターニングして下部
配線層を形成し、その上に層間絶縁膜を介して上部配ｍ
層を形成することを特徴とする。A method for manufacturing a semiconductor device having a multilayer wiring structure according to the present invention includes depositing a conductive layer serving as a lower wiring layer on an insulating layer having a contact hole, and forming a conductive layer on the surface of the conductive layer in a portion including the contact hole. After that, the conductive layer is patterned to form a lower wiring layer, and an upper wiring layer is formed on top of the lower wiring layer through an interlayer insulating film.
It is characterized by forming a layer.
本発明のより具体的なりａ！においては、半導体基板上
にＭＯＳ）ランジスタ等の拡散層やフィールド絶縁Ｊｌ
ｌ（場合によってはゲート電極等も）を形成した上に第
１の層間綿Ｉ＆膜を被着する工程と、第１の層間絶縁膜
の所定の場所にコンタクトホールを形成する工程と、第
１の配線層となる第１の導電層をその上に被着する工程
と、リンとボロンを含むシリケートガラス膜やシリカ塗
布膜などのりフロー相線１１１Ｍを第１の導電層の表面
に被着する工程と、熱処理によりリフロー用絶縁膜をリ
フローする工程と、このリフローした絶縁膜を第１の導
電層の凸部表面が露出するまでエッチバックして下地パ
ターンやコンタクトホール等により第１の導電層の表面
に生じた凹部に上記リフローした絶縁膜を第２の層間絶
縁膜として埋め込む工程と、表面凹部に第２の層間絶縁
膜が埋め込まれた状態の第１の導電体を所望のパターン
にパターニングして第１の配線層を形成する工程と、そ
の上に第３の層間絶縁膜を介して第２の配線層を形成す
る工程とを含む製造方法が得られる。More specific details of the present invention! In this case, a diffusion layer such as a MOS transistor or a field insulator is placed on a semiconductor substrate.
A step of depositing a first interlayer cotton I & film on top of the first interlayer insulating film (or gate electrodes etc. in some cases), a step of forming a contact hole at a predetermined location of the first interlayer insulating film, A step of depositing a first conductive layer that will become a wiring layer thereon, and depositing a glue flow phase line 111M such as a silicate glass film containing phosphorus and boron or a silica coating film on the surface of the first conductive layer. a step of reflowing the insulating film for reflow by heat treatment; and a step of etching back the reflowed insulating film until the surface of the convex portion of the first conductive layer is exposed to form the first conductive layer through an underlying pattern, contact hole, etc. embedding the reflowed insulating film as a second interlayer insulating film in the recesses formed on the surface of the first conductor, and patterning the first conductor with the second interlayer insulating film embedded in the surface recesses into a desired pattern. A manufacturing method including the steps of forming a first wiring layer and forming a second wiring layer thereon via a third interlayer insulating film is obtained.
次に本発明について、図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図および第２図は、本発明をｌＭＯＳトランジスタ
／１セル型のＤＲＡＭの製造に適用した一実施例のＤＲ
ＡＭ単位パターン（２セルを含む）部分のビット方向お
よびワード方向の縦断面図である。FIGS. 1 and 2 show a DR of an embodiment in which the present invention is applied to the manufacture of an IMOS transistor/single cell type DRAM.
FIG. 3 is a vertical cross-sectional view of an AM unit pattern (including two cells) in the bit direction and word direction.
まず第１図Ａおよび第２図を参照すると、公知の方法で
セル部分のＭＯＳ）−ランジスタ、キャパシタ構造を形
成する。すなわち、Ｐｆｆｉ半導体基板１のセル部分以
外のフィールド領域表面にフィールド酸化１Ｉ１２を形
成し、トランジスタ部の表面にはゲート酸化膜３を設け
てその上に２つのポリシリコンゲート電極１３を設けく
ワード線となって延在し、隣りの単位パターン部ではキ
ャパシタ上をｆｆ３’として走る）、その間の基板表面
に２つのトランジスタに共通のＮ型ソースドレイン領域
８を形成する。キャパシタ部にはそれぞれ基板１にトレ
ンチをあけ、その基板側にＮ型領域１１を、トレンチ内
部にポリシリコン容量電極１２を設ける０次に第１図Ａ
に示すように第１の層間絶縁膜４〈たとえばＢＰＳＧ膜
〉を全面に被着し、熱処理でリフローした後、所望の場
所（この場合はソースドレイン領域８）にコンタクトホ
ール５を形成する。Referring first to FIGS. 1A and 2, a MOS transistor (MOS)-transistor, capacitor structure of the cell portion is formed by a known method. That is, a field oxide 1I12 is formed on the surface of the field region other than the cell portion of the Pffi semiconductor substrate 1, a gate oxide film 3 is provided on the surface of the transistor portion, and two polysilicon gate electrodes 13 are provided on the word line. (in the adjacent unit pattern section, it runs over the capacitor as ff3'), and an N-type source/drain region 8 common to the two transistors is formed on the substrate surface between them. In each of the capacitor parts, a trench is formed in the substrate 1, an N-type region 11 is provided on the substrate side, and a polysilicon capacitor electrode 12 is provided inside the trench.
As shown in FIG. 2, a first interlayer insulating film 4 (for example, a BPSG film) is deposited over the entire surface, and after reflowing by heat treatment, a contact hole 5 is formed at a desired location (in this case, source/drain region 8).
次に、第１図Ｂに示すように第１の配線層となるタング
ステン・シリサイド導電体６を全表面に約３０００Ａ〜
４０００Ａスパツタで被着し、その上にリンとボワンを
含んだシリゲートガラス（Ｂ Ｐ Ｓ Ｇ膜）７を約１
００００Ａ被着する。Next, as shown in FIG. 1B, a tungsten silicide conductor 6, which will become the first wiring layer, is coated on the entire surface with a thickness of about 3000A~
The siligate glass (BPSG film) 7 containing phosphorus and boan is deposited on it using a 4000A sputter and about 1
0000A deposited.
次に、第１図Ｃに示すようにＢＰＳＧ膜７を熱処理によ
りリフローし、凹部（コンタクトホール５等りこ生じた
もの〉を埋め込む０次いで第１．ＩＩＤに示すようにタ
ングステン・シリサイド膜６の凸部表面が露出する表で
ＢＰＳＧ膜７を異方性プラズマエッチでエッチバックし
て第２の層間絶縁膜１７とし、次に第１図Ｅおよび第２
図に示すようにタングステン・シリサイド膜６をパター
ニングして第１の配線層１６（ビット線）を形成する。Next, as shown in FIG. The BPSG film 7 is etched back by anisotropic plasma etching on the surface where the surface is exposed to form a second interlayer insulating film 17.
As shown in the figure, the tungsten silicide film 6 is patterned to form a first wiring layer 16 (bit line).
そしてその上に第３の層間絶縁膜９（たとえばＢＰＳＧ
ＩＫ）を介して第２の配線層１０を形成する。第２の配
線層１０は例えばアルミニウム配線によるワード線のつ
り上げ配線であり、ポリシリコンワード線１３．１３’
の抵抗を下げるためにワード線１３．１３’に重畳して
配線し、セルアレイ内の適当な部分（図示せず）で第３
の層間絶縁膜９にあけたコンタクトホール（図示せず）
を通して下方のポリシリコンワード線１３．１３’にそ
れぞれコンタクトする。Then, on top of that, a third interlayer insulating film 9 (for example, BPSG
A second wiring layer 10 is formed via IK). The second wiring layer 10 is, for example, a word line lifting wiring made of aluminum wiring, and the polysilicon word line 13.13'
In order to lower the resistance of the word line 13 and 13', the third
A contact hole (not shown) made in the interlayer insulating film 9 of
through which contact the lower polysilicon word lines 13, 13', respectively.
本実施例では、第１の配線層１６〈ビット線〉表面の凹
部がＢＰＳＧ膜１７膜堰７込まれているため、第２の配
線層（Ａｇ配線等）１０の下地が非常になめらかになっ
ており、第２の配線層１０の加工精度が向上する。In this embodiment, since the recesses on the surface of the first wiring layer 16 (bit lines) are filled with the BPSG film 17, the base of the second wiring layer (Ag wiring, etc.) 10 becomes very smooth. Therefore, the processing accuracy of the second wiring layer 10 is improved.
以上説明したように、本発明は多層配線構造における下
部配線となる導電層表面の凹部を絶縁膜で埋め込んだ後
に導電層をパターニングして下部配線を形成し、その上
に層間絶縁膜を介して上部配線を形成する方法であるた
め、上部配線をその上に形成する下地における段差を軽
減し、段差部での上部配線の断線やエツチング残りによ
る短絡等が起こりにくくなり、配線の加工精度を向上す
る事ができるという効果がある。As explained above, the present invention involves filling the recesses on the surface of a conductive layer that will serve as the lower wiring in a multilayer wiring structure with an insulating film, then patterning the conductive layer to form the lower wiring, and then forming a lower wiring on top of the recess through an interlayer insulating film. Since this is a method for forming the upper wiring, it reduces the level difference in the base on which the upper wiring is formed, making it less likely that the upper wiring will break at the stepped part or short circuiting due to etching residue, improving the accuracy of wiring processing. It has the effect of being able to do something.
第１図Ａ〜Ｅは、本発明をｌＭＯＳトランジスタ型ＤＲ
ＡＭ半導体装置の製造に適用した場合の実施例の工程順
縦断面図であり、ＤＲＡＭの単位パターン部をビット線
に直角の方向（ワード線に平行な方向〉に切った断面図
である。第２図は第１図の実施例に従って形成したｌＭ
ＯＳトランジスタ型ＤＲＡＭ半導体装置の単位パターン
部をビット線に平行な方向（ワード線に直角方向）に切
った縦断面図である。第２図は第１図よりも縮小して示
した。第１図Ｅは第２図のＥ−Ｅ’線に沿った断面図に
相当する。
１・・・半導体基板、２・・・フィールド酸化膜、３・
・・ゲート酸化膜、４・・・第１の層間絶縁膜、５・・
・コンタクトホール、６・・・タングステンシリサイド
膜、７・・・ＢＰＳＧ膜、８・・・ソースドレイン領域
５１６・・・第１の配線層、１７・・・第２の層間絶縁
膜、９・・・第３の層間絶縁膜、１０・・・第２の配線
層、１１・・・容量蓄積電荷領域、１２・・・容量電極
、１３゜１３′・・・ゲート電極。FIGS. 1A to 1E show the present invention as an IMOS transistor type DR.
FIG. 3 is a vertical cross-sectional view in the order of steps of an embodiment when applied to manufacturing an AM semiconductor device, and is a cross-sectional view of a unit pattern portion of a DRAM cut in a direction perpendicular to a bit line (a direction parallel to a word line). Figure 2 shows an lM formed according to the embodiment of Figure 1.
FIG. 2 is a longitudinal cross-sectional view of a unit pattern portion of an OS transistor type DRAM semiconductor device taken in a direction parallel to a bit line (perpendicular to a word line). FIG. 2 is shown on a smaller scale than FIG. 1. FIG. 1E corresponds to a sectional view taken along line EE' in FIG. 2. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field oxide film, 3...
...Gate oxide film, 4...First interlayer insulating film, 5...
- Contact hole, 6... Tungsten silicide film, 7... BPSG film, 8... Source/drain region 516... First wiring layer, 17... Second interlayer insulating film, 9... - Third interlayer insulating film, 10... Second wiring layer, 11... Capacitive storage charge region, 12... Capacitive electrode, 13° 13'... Gate electrode.
Claims (1)
膜を被着する工程と、該第１の層間絶縁膜の所定の場所
にコンタクトホールを形成する工程と、該コンタクトホ
ールを含む第１の層間絶縁膜上に第１の配線層となる第
１の導電層を被着する工程と、前記第１の導電層表面の
前記コンタクトホール部を含む部分に生じている凹部に
第２の層間絶縁膜を埋め込む工程と、表面凹部に前記第
２の層間絶縁膜が埋め込まれた状態の前記第１の導電層
を所望のパターンにパターニングして第１の配線層を形
成する工程と、その上に第３の層間絶縁膜を介して第２
の配線層を形成する工程とを含むことを特徴とする多層
配線構造を有する半導体装置の製造方法。A step of depositing a first interlayer insulating film on a semiconductor substrate in which a desired region is formed, a step of forming a contact hole at a predetermined location of the first interlayer insulating film, and a step of forming a contact hole including the contact hole. a step of depositing a first conductive layer to become a first wiring layer on a first interlayer insulating film; and depositing a second conductive layer in a recess formed in a portion of the surface of the first conductive layer including the contact hole portion. a step of embedding an interlayer insulating film; a step of patterning the first conductive layer with the second interlayer insulating film embedded in the surface recesses into a desired pattern to form a first wiring layer; A second layer is formed on top through a third interlayer insulating film.
1. A method for manufacturing a semiconductor device having a multilayer wiring structure, the method comprising: forming a wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21034389A JPH0373531A (en) | 1989-08-14 | 1989-08-14 | Manufacture of semiconductor device provided with multilayer wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21034389A JPH0373531A (en) | 1989-08-14 | 1989-08-14 | Manufacture of semiconductor device provided with multilayer wiring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0373531A true JPH0373531A (en) | 1991-03-28 |
Family
ID=16587835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21034389A Pending JPH0373531A (en) | 1989-08-14 | 1989-08-14 | Manufacture of semiconductor device provided with multilayer wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0373531A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0718879A1 (en) * | 1994-12-22 | 1996-06-26 | STMicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5633196A (en) * | 1994-05-31 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Method of forming a barrier and landing pad structure in an integrated circuit |
| US5719071A (en) * | 1995-12-22 | 1998-02-17 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad sturcture in an integrated circuit |
| US5909636A (en) * | 1994-12-22 | 1999-06-01 | Stmicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5914518A (en) * | 1994-05-31 | 1999-06-22 | Stmicroelectronics, Inc. | Method of forming a metal contact to landing pad structure in an integrated circuit |
| US5945738A (en) * | 1994-05-31 | 1999-08-31 | Stmicroelectronics, Inc. | Dual landing pad structure in an integrated circuit |
| US6093963A (en) * | 1994-12-22 | 2000-07-25 | Stmicroelectronics, Inc. | Dual landing pad structure including dielectric pocket |
| KR100333545B1 (en) * | 1998-12-30 | 2002-06-20 | 박종섭 | Method of forming test pattern structure of semiconductor device |
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| JPS62194647A (en) * | 1986-02-20 | 1987-08-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS62281468A (en) * | 1986-05-30 | 1987-12-07 | Fujitsu Ltd | semiconductor equipment |
| JPS63133550A (en) * | 1986-11-26 | 1988-06-06 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS63289836A (en) * | 1987-05-21 | 1988-11-28 | Sony Corp | Manufacture of semiconductor device |
| JPS6476727A (en) * | 1987-09-17 | 1989-03-22 | Nec Corp | Manufacture of semiconductor device |
Cited By (15)
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|---|---|---|---|---|
| US5945738A (en) * | 1994-05-31 | 1999-08-31 | Stmicroelectronics, Inc. | Dual landing pad structure in an integrated circuit |
| US5956615A (en) * | 1994-05-31 | 1999-09-21 | Stmicroelectronics, Inc. | Method of forming a metal contact to landing pad structure in an integrated circuit |
| US5702979A (en) * | 1994-05-31 | 1997-12-30 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5894160A (en) * | 1994-05-31 | 1999-04-13 | Stmicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5793111A (en) * | 1994-05-31 | 1998-08-11 | Sgs-Thomson Microelectronics, Inc. | Barrier and landing pad structure in an integrated circuit |
| US5914518A (en) * | 1994-05-31 | 1999-06-22 | Stmicroelectronics, Inc. | Method of forming a metal contact to landing pad structure in an integrated circuit |
| US5633196A (en) * | 1994-05-31 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Method of forming a barrier and landing pad structure in an integrated circuit |
| EP0718879A1 (en) * | 1994-12-22 | 1996-06-26 | STMicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5909636A (en) * | 1994-12-22 | 1999-06-01 | Stmicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US6093963A (en) * | 1994-12-22 | 2000-07-25 | Stmicroelectronics, Inc. | Dual landing pad structure including dielectric pocket |
| USRE36938E (en) * | 1994-12-22 | 2000-10-31 | Stmicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5828130A (en) * | 1995-12-22 | 1998-10-27 | Stmicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5719071A (en) * | 1995-12-22 | 1998-02-17 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad sturcture in an integrated circuit |
| US6025265A (en) * | 1995-12-22 | 2000-02-15 | Stmicroelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| KR100333545B1 (en) * | 1998-12-30 | 2002-06-20 | 박종섭 | Method of forming test pattern structure of semiconductor device |
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