JPH02142218A - Dynamic frequency dividing circuit - Google Patents

Abstract

PURPOSE:To enlarge the range of an operating frequency by preparing two types of different transfer gates FETs, for which respectively suitable gate width is set for a high frequency area and a low frequency area, and switching those transfer gates according to a use frequency band. CONSTITUTION:The output of an inverter circuit 1 is connected through transfer gates FETs 3 and 5, which are parallelly connected, to the input of a buffer circuit 2 and further, the output of the buffer circuit 2 is connected through transfer gates FETs 4 and 6, which are parallelly connected, to the input of the inverter circuit 1. Concerning the input signal of the high frequency since the outputs of high-pass filters 11 and 12 are supplied to the gates of the transfer gates FETs 3 and 4, the transfer gate FET of large gate width (Wg) is selected. On the other hand, concerning the input signal of the low frequency, since the outputs of low pass filters 13 and 14 are supplied to the gates of the transfer gates FETs 5 and 6, the transfer gate FET of the small gate width is selected. Thus, the wide operating frequency can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic frequency divider circuit, such as a GaAs dynamic frequency divider circuit, which operates in a high frequency region such as a microwave band.

[Prior Art] Dynamic frequency divider circuits, which can achieve high-speed operation with a simple circuit configuration, have been frequently used in high frequency regions such as microwave bands. FIG. 2 shows the configuration of this dynamic frequency divider circuit. The dynamic frequency divider circuit includes an inverter circuit 21, a first transfer gate 22, a buffer circuit 23, and a second transfer gate 24 connected in a ring. In this circuit, an input signal is given to the first transfer gate 22 as a gate signal, and the second transfer gate 24 is given an input signal as a gate signal.
The input inversion signal from the input inversion circuit 25 is applied as a gate signal to the input inversion circuit 25, and the frequency dividing operation is performed by delaying the feedback signal based on the phase difference between the two signals. In general, in a GaAs integrated circuit, a circuit as shown in FIG. 3 is used as the inverter circuit 21 which operates at high speed, and a circuit as shown in FIG. 4 is used as the buffer circuit 23.

[Problem to be solved by the invention] In order to increase the upper limit operating frequency (fax) of the dynamic frequency divider circuit configured as described above, the gate width (Ilg) of the transfer gate FET must be increased. However, increasing the gate width also increases the leakage current when the transfer gate FET is cut off, shortens the potential holding time of the transfer gate terminal, and increases the lower limit operating frequency (fa+in).

For this reason, there is a drawback that a frequency dividing circuit with a wide operating frequency band cannot be realized.

The present invention has been made in view of such problems, and includes:
The purpose of the present invention is to provide a dynamic frequency divider circuit with a wide operating frequency band.

[Means for Solving the Problems] The present invention provides a first transfer gate FET inserted between an inverter output and a buffer input using a first transfer gate FET with a large gate width and a second transfer gate FET with a small gate width. The second transfer gate is configured by connecting the transfer gate FET in parallel, and the second transfer gate is inserted between the buffer output and the inverter input, and the third transfer gate FET has a large gate width and the fourth transfer gate FET has a small gate width. It is configured by parallel connection with a gate FET. A first high-pass filter and a first low-pass filter are provided for reducing and high-pass filtering the input signal, and a second high-pass filter and a second low-pass filter are for reducing and high-pass filtering the input inverted signal. , giving the output of the first high-pass filter as a gate signal to the first transfer gate FET,
The output of the first low-pass filter is given as the gate signal of the second transfer gate FET, the output of the second high-pass filter is given as the gate signal of the third transfer gate FET, and the output of the second low-pass filter is given as the gate signal of the fourth transfer gate FET. The signal is given as a gate signal to the transfer gate FET.

[Operation] According to the present invention, for input signals with high frequencies, the first. Since the second high-pass filter output is given to the gates of the first and third transfer gate FETs, transfer gate FETs with large gate widths (%l1g)
is selected, and it is possible to increase the upper limit frequency. On the other hand, for input signals with low frequencies, the first. The second low-pass filter output is the second. Since it is given to the gate of the fourth transfer gate FET, the gate width (1'1
g) a small transfer gate FET is selected;
It is possible to lower the lower limit frequency.

In this way, the high-pass filter and the low-pass filter function as switching means for switching between a FET with a large gate width and an FET with a small gate width depending on the frequency of an input signal. Therefore, according to the present invention, a wide operating frequency can be achieved.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of a dynamic frequency divider circuit according to an embodiment of the present invention. The output of the inverter circuit 1 is connected to the input of the buffer circuit 2 via the transfer gate FET 3.5 connected in parallel, and the output of the buffer circuit 2 is connected to the input of the buffer circuit 2 via the transfer gate FET 3.5 connected in parallel.
It is connected to the input of the inverter circuit 1 via T4 and T6.

The transfer gate FETs 3 and 4 are constructed of FETs with a relatively large Wg (for example, 50 μm), and their gate electrode terminals 7 and 8 are made of M I M (Metal Insul).
ator Metal) capacitors 15 and 16, and high-pass filters 11 and 12 consisting of R elements, respectively, to input terminals IN and IN. On the other hand, transfer gates FE75 and FE6 are composed of FETs with relatively small Wg (for example, 10 μm), and their gate electrode terminals 9 and 10 are connected to input terminals IN via low-pass filters 13 and 14, respectively.

Connected to IN.

Now, when an input signal and an input inverted signal are respectively applied to the input terminals (IN, IN), the signals attenuated according to the characteristics of each filter are transferred to the transfer gates FETs 3, 4, 5, .
It will be added to 6.

Here, the cutoff frequencies of the bypass and low-pass filters are determined by, for example, fmax determined from the Wg of the transfer gate FETs 3 and 4, and the cutoff frequency of the transfer gate FE
FETs 3.4, 5, 6 are selected by shifting them with an appropriate overlap between fmin determined from Wg of 75.6, and the cutoff level of the filter is set to transfer.
If the input sensitivity level is set below the input sensitivity level, transfer gates FETs 3 and 4 will operate in the region close to the upper limit operating frequency, transfer gates FE75 and FE6 will not operate, and transfer gates FETs 5 and 4 will operate in the region near the lower limit operating frequency. 6 operates, transfer gate FE73
, 4 can be made inoperative.

As a result, each transfer gate) FET3゜4.5
．． It is possible to expand the operating frequency according to the characteristics of No. 6.

Note that the present invention is not limited to the embodiments described above. In the embodiments described above, the high-pass filters 11 and 12 are
Although the M capacitors 15 and 16 are used, it is also possible to use a diode instead, or to apply a reverse bias to the FET and use it as a capacitor. In this case, it becomes possible to adjust the capacitance value by adjusting the reverse bias value.

[Effects of the Invention] As is clear from the above description, the present invention focuses on the %l1g of the transfer gate FET, which is one of the factors that determines the operating frequency band of the frequency divider circuit, and Two types of transfer gate FETs with Wg settings suitable for each are prepared, and these can be switched depending on the frequency band used, making it possible to raise the maximum operating frequency and lower the minimum operating frequency. This has the effect of expanding the operating frequency range.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a dynamic frequency divider circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional dynamic frequency divider circuit, and FIG. 3 is a circuit diagram of an inverter circuit in FIG. 2. FIG. 4 is a circuit diagram of the buffer circuit in FIG. 2. 1.21, inverter circuit, 2.23; buffer circuit, 3 to 6; transfer gate FET, 7 to 10
; Gate electrode terminal, 11.12; High pass filter, 1
3, 14; low pass filter, 15.16. MIM capacitor, 17; output terminal, IN, IN, input terminal, 22
, 24;) Transfer gate, 25: Input inversion circuit

Claims (1)

[Claims] (1) An inverter, a first transfer gate, a buffer, and a second transfer gate are connected in this order in a ring, and the input signal is used as a gate signal to the first transfer gate, and the input inverted signal is used as a gate signal to the second transfer gate. A dynamic frequency divider circuit in which an input signal is input and an output is taken out from the buffer, a first high-pass filter that high-pass filters the input signal, a first low-pass filter that low-pass filters the input signal, and a first low-pass filter that low-pass filters the input signal; The first transfer gate includes a second high-pass filter that high-pass filters a signal, and a second low-pass filter that low-pass filters the input inverted signal.
A first transfer gate FET with a large gate width into which the output of the high-pass filter is input as a gate signal, and a second transfer gate FET with a small gate width into which the output of the first low-pass filter is input as a gate signal are connected in parallel. The second transfer gate is connected to a third transfer gate FET having a large gate width that inputs the output of the second high-pass filter as a gate signal, and the third transfer gate FET that inputs the output of the second high-pass filter as a gate signal. 1. A dynamic frequency divider circuit, characterized in that it is configured by connecting in parallel a fourth transfer gate with a small gate width that is input as a signal.