JPH03195109A - Differential amplifier circuit - Google Patents
Differential amplifier circuitInfo
- Publication number
- JPH03195109A JPH03195109A JP33391789A JP33391789A JPH03195109A JP H03195109 A JPH03195109 A JP H03195109A JP 33391789 A JP33391789 A JP 33391789A JP 33391789 A JP33391789 A JP 33391789A JP H03195109 A JPH03195109 A JP H03195109A
- Authority
- JP
- Japan
- Prior art keywords
- gain
- differential amplifier
- terminal
- phase compensation
- phase compensating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は入力信号レベルに応じてゲイン切替可能な差
動増幅回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit whose gain can be changed according to the input signal level.
〔従来の技術]
第2図は従来のゲイン切替可能な差動増幅回路の基本回
路図である。図において、(1)は差動増幅器、R1,
R2,R3は抵抗、81.82はMOSトランジスタに
よるスイッチ、IIはインバータである。[Prior Art] FIG. 2 is a basic circuit diagram of a conventional gain-switchable differential amplifier circuit. In the figure, (1) is a differential amplifier, R1,
R2 and R3 are resistors, 81.82 is a MOS transistor switch, and II is an inverter.
差動増幅器(1)の出力V outと接地の間に抵抗R
IR2,R3が直列接続され、差動増幅器(1)の逆相
入力Vin(→と、抵抗R1とR2の接続点との間にス
イッチS1が、同様に逆相入力Via (→と、抵抗R
2とR3との接続点との間にスイッチS2が接続され、
これらのスイッチを構成する−08)ランジスタのゲー
ト入力は、ゲイン切替入力vHLK対し、スイッチ81
へはインバータIIを介して接続され、スイッチS2へ
は直接接続されており、また、位相補償容量CIは差動
増幅器(1)の適当な位置に接続されて構成されている
。A resistor R is connected between the output V out of the differential amplifier (1) and the ground.
IR2 and R3 are connected in series, and a switch S1 is connected between the negative phase input Vin (→ and the connection point of the resistors R1 and R2) of the differential amplifier (1), and the switch S1 is connected between the negative phase input Via (→ and the resistor R
A switch S2 is connected between the connection point of 2 and R3,
The gate input of the -08) transistor constituting these switches is connected to the switch 81 for the gain switching input vHLK.
is connected to via an inverter II, and directly connected to a switch S2, and a phase compensation capacitor CI is connected to an appropriate position of the differential amplifier (1).
次に動作について説明する。ゲイン切替人力VHLがH
の場合、スイッチs1はオフし、スイッチS2はオンす
るため、本差動増幅回路におけるゲインムは。Next, the operation will be explained. Gain switching power VHL is H
In this case, the switch s1 is turned off and the switch S2 is turned on, so the gain in this differential amplifier circuit is.
Vout = fr(Vir+(+)−Win(−)
) (K:アンプのゲイン)次K、ゲイン切替入
力VHLがLの場合、同様にして、
となる。従って、ゲイン切替入力VHLがHの時、ゲイ
ンはA、で高ゲインにな9、VHLがLの時、ゲインA
Lで低ゲインとな9、ゲイン切替が可能となる。Vout = fr(Vir+(+)-Win(-)
) (K: gain of amplifier) When the gain switching input VHL is L, the following is similarly obtained. Therefore, when the gain switching input VHL is H, the gain is A, which is a high gain of 9, and when VHL is L, the gain is A.
When L is set to low gain, gain switching becomes possible.
しかし、位相補償容量c1の値はゲインによらず同じで
あった。However, the value of the phase compensation capacitor c1 was the same regardless of the gain.
[発明が解決しようとする課題]
従来のゲイン切替可能な差動増幅器は以上の様に構成さ
れていたので、ゲインが変わっても位相補償容量値は一
定であるため、低ゲイン時の位相補償のために容量値を
大きくとれば、高ゲイン時には周波数特性(特にスルー
レート)が悪くな抄、逆に、高ゲイン時の位相補償とし
て容量値を小さくとれば、低ゲイン時に位相余裕がなく
発振に至ることが多く、両ゲイン共使用可能な容量値を
選がことになり、この場合、共Kかな抄性能が抑えられ
た特性となってしまうなどの問題があった。[Problem to be solved by the invention] Since the conventional gain-switchable differential amplifier was configured as described above, the phase compensation capacitance value remains constant even when the gain changes, so phase compensation at low gain is not possible. If the capacitance value is set large for this reason, the frequency characteristics (especially slew rate) will be poor at high gain.On the other hand, if the capacitance value is set small for phase compensation at high gain, there will be no phase margin at low gain, resulting in oscillation. In many cases, it becomes necessary to select a capacitance value that can be used for both gains, and in this case, there are problems such as a characteristic in which Kana cutting performance is suppressed for both gains.
さらに、ゲインの差が大きくなると上記の問題点が増大
するため、ゲインの選択幅も狭くなってしまう問題があ
った。その丸め、ゲインを大きく変えた出力を得たい場
合には、高ゲイン及び低ゲインの2種類の差動増幅回路
が必要となり規模が大きくなってしまう問題もあったつ
この発明は上記の様な問題を解消するためになされたも
ので、ゲインの切替えに応じて1位相補償容量値も切替
えることのできる差動増幅回路を得ることを目的とする
う
〔課題を解決するための手段J
この発明に係る差動増幅回路は、ゲイン切替可能な差動
増幅回路において、複数の位相補償容量を並列に接続し
、各容量と、容量間の接続点の間忙スイッチを設けたも
のである。Furthermore, as the gain difference increases, the above-mentioned problem increases, so there is a problem that the gain selection range becomes narrower. If you want to obtain an output with a large change in rounding or gain, you will need two types of differential amplifier circuits, one high gain and one low gain, resulting in an increase in scale. The purpose of this invention is to obtain a differential amplifier circuit that can also switch the value of one-phase compensation capacitance according to the switching of the gain. Such a differential amplifier circuit is a gain-switchable differential amplifier circuit in which a plurality of phase compensation capacitors are connected in parallel, and a switch is provided between each capacitor and a connection point between the capacitors.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図はこの発明の一実施例である差動増幅回路の回路
図である。まず前記従来の第2図と比較して見ると1位
相補償容量CIの一方の端子に第2の位相補償容量C2
を接続し、この第2の位相補償容量C2の他方の端子と
位相補償容量CIの他方の端子との間VC108)ラン
ジスタにょるス、r7+83を接続し、このMOS )
ヲンジヌタのゲートを、インバータ11の出力とスイッ
チ81のゲートとに接続して構成している。FIG. 1 is a circuit diagram of a differential amplifier circuit which is an embodiment of the present invention. First, in comparison with the conventional diagram shown in FIG. 2, a second phase compensation capacitor C2 is connected to one terminal of the first phase compensation capacitor CI.
between the other terminal of this second phase compensation capacitor C2 and the other terminal of the phase compensation capacitor CI, connect VC108) transistor r7+83, and connect this MOS)
The gate of the inverter is connected to the output of the inverter 11 and the gate of the switch 81.
次Kl!If′F、について説明する。ゲイン切替入力
V)ILが■の場合、スイッチs1はオフ、スイッチS
2はオンしているため、本差動増幅回路のゲインAHは
、(1)式より
であり、この時、スイッチS3はオフしているため、位
相補償容量はC1のみとなる。Next Kl! If'F will be explained. When gain switching input V) IL is ■, switch s1 is off, switch S
2 is on, the gain AH of this differential amplifier circuit is based on equation (1). At this time, since the switch S3 is off, the phase compensation capacitor is only C1.
次K、ゲイン切替入力Vl(LがLの場合、スイッチS
lはオン、スイッチS2はオフしているため、本差動増
幅回路のゲインALは、(2)式よりであり、さらにこ
の時、スイッチs3はオンしているため、位相補償容量
(i、clと02が並列に接続されるので合成容量Cは
C=CI +C2・・(3)
となる、
従って、高ゲイン時には位相補償容量はCIのみで小さ
くとることができる九め、周波数特性(特にスルーレー
ト)は良好となる。そして、低ゲイン時には位相補償容
量はC1と02の合成容量となり大きくなるため、位相
余裕を大きくとることができるため、発振することもな
く良好な特性が得られる。Next K, gain switching input Vl (if L is L, switch S
Since l is on and switch S2 is off, the gain AL of this differential amplifier circuit is from equation (2).Furthermore, at this time, since switch s3 is on, the phase compensation capacitor (i, Since cl and 02 are connected in parallel, the combined capacitance C is C=CI +C2...(3) Therefore, at high gain, the phase compensation capacitance can be kept small by using only CI.Ninth, the frequency characteristics (especially When the gain is low, the phase compensation capacitor becomes a combined capacitance of C1 and 02 and becomes large, so a large phase margin can be obtained, and good characteristics can be obtained without oscillation.
なお、上記実施例ではゲイン切替及び位相補償容量の切
替えを2段で行なった場合を示したが、これは数段の場
合でも同様に構成することが可能である。In the above embodiment, the case where the gain switching and the phase compensation capacitance switching are performed in two stages is shown, but this can be similarly configured even in the case of several stages.
〔発明の効果)
以上の様にこの発明によれば、ゲイン切替に応じて位相
補償容量値も切替可能な構成にしたので、各ゲインに応
じた位相補償が可能となり、ゲインにかかわらず優れた
特性が得られる効果がある。[Effects of the Invention] As described above, according to the present invention, the phase compensation capacitance value can also be switched in accordance with gain switching, so phase compensation can be performed in accordance with each gain, and excellent performance can be achieved regardless of the gain. It has the effect of obtaining characteristics.
さらに、位相補償容量の選択により、切替えることので
きるゲインの幅(大きさ)を大きくとることが可能とな
る効果がある、また、それに伴ないゲイン差が大きくて
も、高ゲインと低ゲインの2橋類の差動層@器を用いる
必要がなく、1つの差動増幅器でよいため、回路を小さ
く構成できるなどの効果がある。Furthermore, by selecting the phase compensation capacitor, it is possible to increase the width (size) of the gain that can be switched. Since there is no need to use a two-bridge type differential layer and only one differential amplifier is required, the circuit can be made smaller.
第1図はこの発明の一実施例によるゲイン切替可能な差
動増幅回路の回路図、第2図は従来のゲイン切替可能な
差動増幅回路の基本回路図である。
図において、(1)は差動増幅器、R1ないしR3は第
1ないし第3の抵抗、81ないしS3はfslないし第
3のVO8)ランジスタによるスイッチCI、C2は第
1.第2の位相補償容量、IIはインバータを示す。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a circuit diagram of a gain switchable differential amplifier circuit according to an embodiment of the present invention, and FIG. 2 is a basic circuit diagram of a conventional gain switchable differential amplifier circuit. In the figure, (1) is a differential amplifier, R1 to R3 are first to third resistors, 81 to S3 are fsl to third VO8) transistor switches CI, and C2 is first to third resistors. The second phase compensation capacitor, II, represents an inverter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
抵抗を直列に接続し、前記第1、第2の抵抗の接続点と
前記差動増幅器の逆相入力間に第1、のMOSFETを
接続し、前記第2、第3の抵抗の接続点と前記逆相入力
間に第2のMOSFETを接続し、前記第1、第2のM
OSFETのゲートを各々、インバータの出力及び入力
に接続し、前記インバータの入力をゲイン切替入力端子
とし、前記差動増幅器に第1の位相補償容量を接続し、
前記第1の位相補償容量の一方の端子に第2の位相補償
容量の一方の端子を接続し、他方の端子と前記第1の位
相補償容量の他方の端子の間に第3のMOSFETを接
続し、前記MOSFETのゲートを前記インバータの出
力に接続して構成したことを特徴とする差動増幅回路。A first, a second, and a third resistor are connected in series between the output terminal of the differential amplifier and the ground, and a first resistor is connected between the connection point of the first and second resistors and the negative phase input of the differential amplifier. , a second MOSFET is connected between the connection point of the second and third resistors and the negative phase input, and the second MOSFET is connected between the first and second M
The gates of the OSFETs are respectively connected to the output and input of an inverter, the input of the inverter is used as a gain switching input terminal, and a first phase compensation capacitor is connected to the differential amplifier,
One terminal of a second phase compensation capacitor is connected to one terminal of the first phase compensation capacitor, and a third MOSFET is connected between the other terminal and the other terminal of the first phase compensation capacitor. A differential amplifier circuit characterized in that the gate of the MOSFET is connected to the output of the inverter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33391789A JPH03195109A (en) | 1989-12-22 | 1989-12-22 | Differential amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33391789A JPH03195109A (en) | 1989-12-22 | 1989-12-22 | Differential amplifier circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03195109A true JPH03195109A (en) | 1991-08-26 |
Family
ID=18271412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33391789A Pending JPH03195109A (en) | 1989-12-22 | 1989-12-22 | Differential amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03195109A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1168600A3 (en) * | 2000-06-27 | 2005-09-07 | Infineon Technologies AG | Circuit and method for attenuating and reducing of undesired properties of an operational amplifier |
JP2010232749A (en) * | 2009-03-26 | 2010-10-14 | Tdk Corp | Amplifier circuit, and optical pickup having the same |
-
1989
- 1989-12-22 JP JP33391789A patent/JPH03195109A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1168600A3 (en) * | 2000-06-27 | 2005-09-07 | Infineon Technologies AG | Circuit and method for attenuating and reducing of undesired properties of an operational amplifier |
JP2010232749A (en) * | 2009-03-26 | 2010-10-14 | Tdk Corp | Amplifier circuit, and optical pickup having the same |
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