JPH0213995A - Image processor - Google Patents

Abstract

PURPOSE:To take a hard copy of display data at a high speed and simply by transferring directly image data for a display to a memory for a hard copy. CONSTITUTION:The title processor is provided with image memories (frame memories) 10-12 which has the storage capacity corresponding to a monitor screen 16, and in which display data has been stored. In this state, this processor operates so that display data which has synthesized frame data is transferred to one frame memory, the display data which has been stored in its frame memory is printed to a recording medium and an image is formed. In such a way, a hard copy of the display data which has synthesized plural screens can be taken at a high speed and simply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that combines image data from a plurality of frame memories and transfers the combined image data to at least one frame memory.

[Prior Art] FIG. 6 is a diagram showing a schematic configuration of a conventional image processing device that synthesizes multiple screens to create one display data.
．． 25 and 26 are image memories (frame memories) each having a capacity corresponding to the monitor screen 30 and storing image data for one screen. A mask memory 27 also has a capacity corresponding to the monitor screen 3o and stores mask information corresponding to each pixel. The image data in the image memories 24 and 25 are selected by the selector 28 in accordance with the contents of the mask memory 27, combined, and output to the D/A conversion circuit 29. In this way, it is converted into an analog signal by the D/A conversion circuit 29 and displayed on the monitor 30.

In such a hardware configuration, when printing a hard copy of the image data displayed on the monitor screen 30 using the hard copy device 31, the image memories 24 and 25 are controlled by the CPU connected to the bus 32. Image data is selected according to the contents of the mask memory 27 and transferred to the image memory 26 via the bus 32.
Image data for one screen is created within the computer, and the image data is sequentially transferred to the hard copy device 31.

[Problem to be Solved by the Invention] However, when a hard copy of image data is created in this way, the image data is transferred from a plurality of image memories to an image memory for hard copy, and the image data for display is Since it is necessary to create new image data using two different paths, a special data processing unit and control program are required. Furthermore, since a large amount of image data is transferred from a plurality of image memories to a hard copy image memory, there is a problem in that a large amount of transfer time is required.

The present invention has been made in view of the above conventional example, and provides an image processing device that can quickly and easily take a hard copy of display data by directly transferring the display image data to a hard copy memory. The purpose is to provide.

[Means for Solving the Problems] In order to achieve the above object, an image processing apparatus of the present invention has the following configuration. That is, an image processing device that synthesizes and displays frame data for a plurality of sides, comprising a transfer means that transfers display data obtained by synthesizing the frame data to one frame memory, and display data stored in the frame memory. and an image forming means for printing on a recording medium to form an image.

According to another claim, the transfer means includes a first address means for updating the address of the frame memory in synchronization with a display synchronization signal, and a first address means for updating the address of the frame memory in synchronization with a display synchronization signal; and second address means for outputting a read address for reading data.

[Operation] In the above configuration, display data obtained by combining frame data is transferred to one frame memory, and the display data stored in the frame memory is printed on a recording medium to form an image.

According to the structure of another claim, the transfer means can update the address of the frame memory in synchronization with the display synchronization signal. Furthermore, when recording on the image forming means, a read address for reading display data from the frame memory can be output.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Image Processing Apparatus (Figs. 1 to 5) Fig. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment.

In the figure, 10 to 12 are image memories (frame memories) each having a storage capacity corresponding to the monitor screen 16 and storing display data. A selector 14 selects data from any of the image memories 10 to 12 according to mask information in the mask memory 27 and outputs the selected data to the D/A conversion circuit 15. Like the conventional example, the mask memory 27 stores mask information instructing which image data is to be displayed. Reference numeral 13 designates a memory control circuit of the embodiment whose details are shown in FIG. is being printed. This memory control circuit 13 also controls the monitor 1
A synchronizing signal 202 for display from 6 is input, and this signal 202 causes display data to be stored in the image memory 102, which will be described later.
, the address of the address generator 104 that is outputting that address is updated.

21 is a CPU that controls the image processing apparatus of the embodiment according to the control program stored in the ROM 19;
R that stores PU control programs and various data, etc.
OM, 20 is a RAM used as a work area for the CPU 21.

With the above configuration, the CPU 21 can store image data in the image memories 10 to 12 via the bus 18, read image data from each image memory, and can also change the contents of the mask memory 27 and store the image data in the image memories 10 to 12. The selection information of the display data from 12 to 12 can be changed.

FIG. 5 is a diagram showing a case where a plurality of image data on the monitor screen 16 are superimposed and synthesized, and parts common to FIG. 1 are indicated by the same symbols.

In the figure, image data such as diagonal lines and hatching are stored at 10, 11, and 12, respectively. The mask memory 27 includes portions 1O-1 to 1 that can be displayed on the monitor screen 16.
Mask information indicating 0-3 is stored in correspondence with each image memory, and this mask information is output to the selector 14.

The selector 14 also uses this mask information in the set display priority order (10-2, 10-1, 1O-3 (7
), the data in each image memory is masked and output to the monitor screen 16. As a result, on the monitor screen 16, as shown in the figure, figures are displayed in the following order: a triangle with the image data of the image memory 11 masked, a circle with the image data of the image memory 10 masked, and a rectangle with the image data of the image data 12 masked. is displayed.

[Description of Memory Control Circuit (Fig. 2)] Fig. 2 is a block diagram showing a schematic configuration of the memory control circuit 13 of the embodiment.
Parts common to other drawings are indicated by the same symbols.

In the figure, 180 and 181 are both bus 1 of C:PU2.
8, 180 is a data bus, and 181 is an address bus. 201 is image data output from the selector 14, which is the same data as the data directly displayed on the monitor 16.

100 is a selector that switches input/output in accordance with the contents of the register 103;
2, the image data 2 (1 is the selector 10
0 is temporarily stored in the buffer 101 and then stored in the image memory 102. Since this buffer 100 has an extremely high number of image data 201, the image memory 100
The image data is temporarily stored before being stored in 02.

Further, when outputting the image data in the image memory 102 to the hard copy device 17, the selector IOC selects the buffer 1.
01 data is selected and output to the Bartco 1 Bee device 17.

\ The image memory 102 is a frame memory having the same capacity as the image memories 10 to 12, and is connected to the address bus.
addressed by the generator 104. Therefore,
When the display data is stored, the address generator 2 104
The image data is sequentially read out from address 1 of the image memory 102 addressed by the Bartcoby device 17.
A hard copy of the image data displayed on the monitor screen 16 is taken. In this case, the selector 100 and buffer 101 function as one output buffer and port.

Preferably, the address generator 104 inputs a display synchronization signal 2o2 (including a horizontal synchronization signal (H3YNC) and a vertical synchronization signal (VSYNC)) from the monitor 16, and updates the image memory every time these signals are input. 1
All you have to do is update the address of 02.

By doing this, when the monitor 16 is displaying the image data by interlaced scanning, the solid line part in FIG.
The data can be written to the image memory 102 in the dotted line in /60 seconds. At the time of display, each scanning line of the image data is sequentially read out from above as shown in FIG.
7 and recorded.

[Explanation of CPU Operation] When storing image data in the image memory 102, the CPU 21 sets the selector 100 in the register 103 to store the image data 2.
01 is set to instruct the buffer 101 to function as a power buffer. thus,
When a predetermined amount of image data is stored in the buffer 101,
The address generator 104 outputs the address of the image memory 102, and the image data of the buffer 101 is sequentially stored in the image memory 102.

On the other hand, when taking a hard copy of the image data in the image memory 102, the selector 100 selects the image data from the buffer 101 and outputs it to the hard copy device 17, and the buffer 101 is read out from the image memory 102. Set the mode for inputting image data. Then, the image memory 102 is addressed by an address generator 104 controlled by the CPU 21, and the image data is read out. This read data is transferred to the buffer 101, and the buffer 101 operates to output image data in synchronization with the recording speed of the hard copy device 17.

[Other Embodiments (FIG. 7) FIG. 7 is a block diagram showing a schematic configuration of an image processing apparatus according to a second embodiment.

In the figure, 70 to 73 are image memories, and 74 to 77 are direction control and address control buffers. Image memory 70-7
Each image data of 3 is stored in a corresponding direction control buffer 74 to
77 and is input to the selector 78. Then, the selector 78 assigns priorities and displays them on the monitor screen 80 in a superimposed manner. Here, the image data displayed on the monitor screen is transferred to the image memory 73 through the direction/address control buffer 77 and stored therein. Note that at this time, no image data is written to the image memories 70 to 72, and furthermore, from this point onwards, data in the image memory 73 is displayed. By doing so, the contents of the image memories 70 to 72 can be changed without changing the display contents of the monitor screen 80.

As described above, according to this embodiment, the display data obtained by combining a plurality of screens can be transferred to the memory easily and at high speed, so that a hard copy of the display data can be easily taken.

[Effects of the Invention] As explained above, according to the present invention, by directly transferring display image data to a hard copy memory, it is possible to quickly and easily take a hard copy of display data. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an image processing device according to an embodiment, FIG. 2 is a block diagram showing a schematic configuration of a memory control circuit according to an embodiment, and FIG. 3 shows the order in which display data is stored in an image memory. 4 is a diagram showing the order in which image data is read from the image memory. FIG. 5 is a diagram showing the concept of image memory masking and superimposition/composition processing. FIG. 6 is a diagram showing the configuration of a conventional image processing device. FIG. 7 is a block diagram showing a schematic configuration of an image processing apparatus according to another embodiment. In the figure, 10 to 12... image memory, 13... memory control circuit, 14... selector, 15... D/A conversion circuit, 16... monitor, 17... hard copy output device , 18... bus, 19... ROM, 20...
RAM. 21...CPU, 27...Mask memory, 100...
...Selector, 101...Buffer, 102...Image memory, 103...Register, 104...Address generator, 201...Display data. Patent applicant Canon Co., Ltd. Figure 4 Figure 6

Claims (2)

[Claims] (1) An image processing device that synthesizes and displays frame data for multiple screens, comprising a transfer means that transfers display data obtained by synthesizing the frame data to one frame memory, and a display stored in the frame memory. An image processing apparatus comprising an image forming means for printing data on a recording medium to form an image. (2) The transfer means includes a first address means for updating the address of the frame memory in synchronization with a display synchronization signal, and a read address for reading display data from the frame memory when recording in the image forming means. 2. The image processing apparatus according to claim 1, further comprising a second address means for outputting the second address means.