JPH0213789B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to an image forming apparatus that forms an electrostatic latent image on a recording medium and then develops the image, and particularly relates to an image forming apparatus that can perform variable magnification image formation. [Prior Art] Conventionally, such image forming apparatuses have been designed to detect the surface potential on the recording medium and to optimize process conditions such as the amount of charge and the amount of exposure depending on the detected potential and the target potential. Suggestions have been made. Furthermore,
Devices with a variable magnification image forming function have also been proposed.
In such an apparatus, when variable magnification image formation is performed, the recording medium is driven at a different speed than when forming a magnified image. Therefore, if the same voltage is applied to the charger during both the same magnification and the magnification change, the amount of charge on the recording medium will differ. In order to solve this problem, a device has been proposed that changes the target potential during variable magnification image formation and controls the voltage applied to the charger to be different between the same magnification and the variable magnification (Unexamined Japanese Patent Publication No. Publication No. 142368). However, this method detects the surface potential of the drum while rotating the drum at a speed corresponding to the magnification while operating the charger, and the detected potential converges to the target potential selected according to the magnification. In this configuration, when variable magnification image formation is selected for the first time after the power is turned on or after forming a 1-magnification image, there is no control data for variable magnification image formation. , it is necessary to detect the surface potential and obtain charge amount control data, which increases the time required for the initial variable-magnification image formation. [Objective] The present invention has been made in view of the above points, and an object thereof is to provide an image forming apparatus capable of shortening the time required for image formation during variable magnification image formation. be. That is, the present invention provides an electrostatic latent image forming means that includes a charging means and forms an electrostatic latent image on the recording medium by charging the recording medium and exposing it to light; and an electrostatic latent image formed on the recording medium. a developing means for developing the recording medium, and a driving means for driving the recording medium at a first speed when forming an image of equal magnification, and driving the recording medium at a second speed lower than the first speed when forming a variable magnification image. , a detection means for detecting a surface potential on the recording body, the detection being performed while the recording body is driven at the first speed and the charging means is operated after power is turned on or an image formation start command is generated; control means for determining and storing control data for optimizing the surface potential of the recording medium when forming a 1:1 image based on a surface potential detection output detected by the means; Sometimes, the charging means is operated based on the control data to form a same-size image, and when forming a variable-magnification image, in order to reduce the amount of charge on the recording medium compared to when forming a variable-magnification image, The present invention provides an image forming apparatus characterized in that the charging means is operated to form a variable magnification image based on data obtained by performing predetermined calculations on the control data. [Example] Next, an example of the present invention will be described in detail with reference to FIGS. 1 to 5. (Schematic Description of Image Forming Apparatus) FIG. 1 shows a schematic configuration of an image forming apparatus according to the present invention. The photoreceptor or photosensitive drum 1 is composed of three layers, for example, an insulating layer, a photoconductive layer, and a conductive layer from the surface, and a shaft 1 is attached to the main body (not shown).
It is supported so as to be rotatable in the direction of the arrow around a. Around this photosensitive drum 1, there is a
Secondary charger 2, secondary charger 3, full exposure lamp 4,
A potential sensor 7, a developing roller 5 of a developing device, a transfer charger 28, and a pre-discharging charger 29 are arranged. The entire surface of the photosensitive drum 1 is uniformly charged by the primary charger 2, and the entire surface of the photosensitive drum 1 is pre-neutralized by the charger 29 prior to each process.The original 10 illuminated by the original exposure lamp 11 is then placed on the mirrors 12, 13. After that, the photosensitive drum 1 is exposed to light. At this time, the charge is removed by the secondary charger 3 according to the image of the document, and a latent image is formed. Subsequently, the entire surface is exposed by a full-surface exposure lamp 4, and then toner is developed by a developing roller 5. As will be described later, a bias voltage is applied to the developing roller 5 to improve the gradation of the image. Subsequently, the transfer charger 28 is activated to perform transfer onto recording paper (not shown). The image forming apparatus of this embodiment is capable of forming images of equal magnification and variable magnification, and the photosensitive drum 1 rotates at a first speed when forming an image of equal magnification, and the photosensitive drum 1 rotates at a first speed when forming a variable magnification image. It rotates at a second speed that is lower than the first speed. After power is turned on or when an image formation start command is issued, the photosensitive drum 1 starts rotating at the first speed. Prior to recording an image, the blank exposure lamp 6 is turned on and off to form a dark area potential (hereinafter referred to as _VD ) and a light area potential (hereinafter referred to as _VSL ) on the photosensitive drum 1. Each potential is detected by a surface potential sensor 7 disposed with respect to the photosensitive drum 1 between the entire surface exposure lamp 4 and the developing roller (developing electrode) 5, and is measured as an analog quantity by a potential measuring circuit 8. The surface potential thus measured is converted into a digital quantity by the A/D conversion circuit 9 and processed within the microcomputer (hereinafter referred to as MPC) 15. The MPC 15 outputs control data so that the bright area potential and the dark area potential approach their respective target values. This data is converted into an analog quantity by the D/A conversion circuit 16 and is then converted into an analog quantity by the primary and secondary high voltage control circuits 18 and 19.
is input. 1 by the primary high voltage control circuit 18
The secondary high-voltage transformer 21 is controlled, thereby controlling the amount of charge on the primary charger 2, and the secondary high-voltage control circuit 19 controls the secondary high-voltage transformer 22, thereby controlling the amount of charge on the secondary charger. and each
V _SL and V _D are adjusted so that they approach the target values. Subsequently, a standard white board (not shown) provided outside the image area of the original 10 is irradiated, and the exposure amount of the original exposure lamp 11 is adjusted. For the first irradiation, predetermined data outputted by the MPC 15 is converted into an analog quantity by the D/A conversion circuit 16, and the light quantity control circuit 17
This is done by applying a lighting voltage adjusted by the lamp regulator 14 to the exposure lamp 11 via the lamp regulator 14. The reflected light from the standard white plate due to this first exposure amount is guided onto the photosensitive drum 1 via mirrors 12 and 13, and the potential (V _L1 ) corresponding to the white background formed on the surface is detected by the potential sensor 7, Measurement is performed via the potential measurement circuit 8. This measured potential is A/
After being converted into digital data by the D conversion circuit 9, it is led to the MPC 15, where calculations are performed using an approximation formula indicating the correlation between exposure amount and surface potential set in advance. The calculation result is converted into an analog quantity by the D/A conversion circuit 16, and the lamp regulator 14 is driven via the light quantity control circuit 17 to adjust the exposure quantity of the exposure lamp 11 so that the white ground potential becomes a target value. This measurement of V _L1 and adjustment of the exposure amount based on the measurement output are repeated three times, the determined exposure amount is irradiated onto the photosensitive drum, and the surface potential of the irradiated portion is V _L2
is measured by the potential sensor 7. This measured potential V _L2 is input to the MPC 15 via the A/D conversion circuit 9.
Based on this, the MPC 15 performs calculation processing such as applying +100V to the measured potential V _L2 , for example. The result of this calculation is converted into an analog value by the D/A conversion circuit 16, and then the DC development bias circuit 20 is driven to control the development bias so that an appropriate development bias is obtained. This developing bias control further corrects the original exposure control described above. That is, by controlling the exposure of the original, the white ground potential is converged to, for example, approximately zero V, and then the developing bias is determined, so that an appropriate DC developing bias can be obtained. The output of the developing bias control circuit 20 is led to an AC developing bias control circuit 23, where an AC bias voltage of, for example, 1300 V peak-to-peak and 1 KHz is superimposed thereon. This alternating current bias functions to faithfully reproduce the gradation of an image. The developing bias voltage obtained from the DC developing bias control circuit 20 and the AC developing bias controlling circuit 23 is applied to the electrode of the developing roller 5, and toner development is performed by jumping development. Regarding jumping development using a developing bias, see, for example, Japanese Patent Application Laid-open No. 18656/1983. The above-mentioned control operation is performed by the MPC 15 receiving an instruction from a means for controlling the sequence of the entire apparatus, for example, in accordance with the procedure shown in FIG. 4 (described later). Further, the pre-discharge step prior to the above process and the transfer step after development are each controlled by the MPC 15. That is, after the data processed by the MPC 15 is converted into an analog value by the D/A conversion circuit 16, the transfer high-voltage transformer 26 and the pre-static elimination high-voltage transformer 27 are controlled and charged via the transfer control circuit 24 and the pre-static elimination control circuit 25, respectively. The devices 28 and 29 are adjusted to control the transfer process and the static elimination process at equal magnification and variable magnification. In the present invention, image forming conditions are thus controlled according to the surface potential on the photoreceptor. (Description of Control Circuit) Next, further details of the control circuit shown in FIG. 1 will be explained with reference to FIGS. 2 and 3. The MPC (microcomputer) 15 sends control signals DB0, DB1, DB2, DB according to a predetermined sequence by a microcomputer (sequence controller) 5' that controls the entire sequence.
3. Receive STROB and RESET MPC chip Q
3. The above-mentioned arithmetic processing is performed according to the procedure determined by the built-in ROM. Also, sequence controller 1
From 5', primary high voltage on signal HV-1, secondary high voltage on signal HV-2, AC developing bias on signal
BIAS is supplied to the primary high voltage control circuit 18, the secondary high voltage control circuit 19, and the AC developing bias control circuit 23, respectively, to turn on and off the generation of the respective high voltage and AC developing bias. Note that each signal is connected to a resistor R.
1 and capacitor C1, the signal is inverted and level-shifted by inverter Q10 at the subsequent stage, and is input to the corresponding input of Q3. RESET initializes Q3. DB0~DB3
The combination of "H" and "L" of these signals indicates the content shown in Table 1, which is judged by the MPC and processed. In the past, the input to the potential control microcomputer 15 was not coded in this way, which had the disadvantage that the number of signal lines increased significantly as the control became more complex. In this embodiment, a maximum of 16 states can be specified as 4-bit data, so the number of signal lines can be reduced.

[Table] In Table 1, DBON means turning on the DC developing bias control circuit 20, and FDB
ON indicates that a DC bias voltage of approximately +400V is generated to prevent toner from adhering to the photosensitive drum 1 during non-development, and LSTR ON is data that specifies turning on the weak secondary voltage output during post-rotation. ,
V _D TS is the measurement timing signal indicating that the potential sensor is measuring the dark potential V _D , V _SL TS is the measurement timing signal of the light potential V _SL , and V _L1 TS is the measurement timing signal of the potential V _L1 due to standard white plate irradiation. Measurement timing signal, V
L2TS each indicates a timing signal for measuring the surface potential V _L2 by irradiating a standard white plate with an exposure amount determined according to a predetermined characteristic based on the potential V _L.
Also, ×1 and ×0.7 are specified data for equal magnification and variable magnification. Q3 determines whether the potential currently being measured is the bright area potential (V _SL ), the dark area potential (V _D ), or the potential due to standard white plate irradiation (V L1 ) according to the data in Table 1 input in A10 to _A13 . etc., the surface potential A/D conversion data described below is taken in, predetermined arithmetic processing is performed, and the results are used as the primary high voltage control value, secondary high voltage control value, light amount control value, and DC developing bias control value.
It is output to the D/A converter Q1 of the D/A conversion circuit 16 via DO0 to DO3. Also, pin 1 of J2
2 (CCC), pins 3-4 (HLC), pins 5-6
(DBC), a value that causes a reference current to flow through the primary and secondary chargers 2 and 3 regardless of the above-mentioned control value, and the document illumination lamp 11
It is also possible to output the reference lighting voltage value and the DC developing bias reference value to the D/A converter Q1. (A/D conversion) For example, in detail, the surface potential measured by the surface potential sensor 7 and potential measuring circuit 8 as described in JP-A-55-142363 is
(POTENTIAL) is input. Furthermore, resistance R2
The signal is inputted to the inverting input terminal of the operational amplifier Q2 via the inverter and is inverted and amplified with a gain determined by the ratio of the resistors R1 and R2. A bias of approximately +6V obtained by dividing the +12V power supply voltage by R4, VR1, and R5 is applied to the non-inverting input terminal of Q2 via a resistor R3. The level of the measured potential can be adjusted by VR1. Further, capacitors C3, C4, and C5 are provided for noise removal. A voltage varying from about 9V to 14V appears on the Q2 output depending on the measured surface potential. This low impedance signal is input to an A/D converter section of an A/D converter circuit 9 including operational amplifiers Q4, Q5, Q6, and the like. The A/D start signal from Q3 is output from pin 15 of Q3 and is normally at "H". Therefore, the output of the inverter Q7 becomes "L", the gate and source of the FET Q8 becomes zero bias, the source and drain of the FET Q8 becomes conductive, and the output of the operational amplifier Q6 becomes a predetermined reference value (the voltage at the start of the A/D). Here, the voltage applied to the Q4 output via R6 to the non-inverting input of Q6 is set to be a value obtained by dividing the Q6 output by R7 and R8. Q4 is for generating the reference voltage for that purpose and is 12V.
is divided by R10 and R9 and then buffered by Q4. The non-inverting input terminal of Q5 has a Q
6 outputs are inputted via R11, and a voltage equivalent to the measurement potential is inputted to the inverting input terminal via R12. Q5 constitutes a comparison circuit, and before the start of A/D conversion, the inverting input side is at a higher voltage than the non-inverting input side, so the Q5 output is approximately 0V. The output of Q5 is level-shifted by Z _D1 and input to inverter Q9. In this case, Q9 is turned off and the output is "H". This signal is applied to microcomputer Q3 as an A/D termination pulse. The A/D starts when the STROB signal from the main unit's sequence controller 15' goes from "H" to "L".
When the STROB signal performed by Q3 changes, the combination of DB0 to DB3 at that time also determines what state the potential for A/D conversion is at.
is determined, and the A/D start signal (terminal
EO _p ) is changed from “H” to “L”. Therefore, Q7 is turned off and the Q4 output reference voltage is applied to the Q8 gate via the resistor R.
13, and the source-drain of Q8 is turned off. Since the Q4 output voltage is applied to the non-inverting input of Q6 via the resistor R6, Q8
When turned off, Q6 output, capacitor C8, and resistor R
The A/D start signal is inverted using the predetermined reference voltage as the initial voltage of the Q6 output, and the current flowing through R8 linearly charges the capacitor C8 until Q8 becomes conductive. When Q8 becomes conductive, the charge stored in C8 is discharged via R7,
The Q6 output quickly drops to the reference voltage. Q3 starts counting after a certain period of time after integration is started as described above by the A/D start signal. Counting is performed until the Q6 output rises directly and the non-inverting input of comparator Q5 exceeds the inverting input. When this value is exceeded, the Q5 output reverses its state, inverter Q9 is turned on, and the Q9 output becomes "L".
Q3 determines this state as the end of counting, and the A/D conversion ends. At the end, Q3 inverts the A/D start pulse applied to Q7, makes Q8 conductive, and the Q6 output rapidly drops to the reference voltage as described above. Inside Q3, predetermined processing is performed according to the flowchart described later, using the counted value as A/D conversion data of each measured potential specified by DB0 to DB3. Noise is removed from DB0 to DB3 and STROB by an integrating circuit formed by R1 and C1, respectively, and the signal is input to the microcomputer Q3 via an inverter Q10. (Input/output signals of microcomputer) Q3 uses an NMOS 1-chip 4-bit microcomputer (MN1400) in this embodiment. Signals as shown in Table 2 below are input or output to each terminal of Q3.

【table】

[Table] (DMS mode) As mentioned above, high voltage primary, secondary,
It is possible to switch the light intensity and DC developing bias between the control value and the standard value, and when the terminal B13 is set to "L" during copy operation standby, the combination of "H" and "L" will be changed as shown in Table 3. Generate each display content and send it to terminals CO6 and CO of Q3.
7, CO8, CO9, DO0, DO1, DO2, DO3
Light emitting diode LED2-1,2- connected to
2, 2-3, 2-4, LED1-1, 1-2, 1
Can be displayed in 8 bits of -3, 1-4 (DMS mode). In particular, the primary and secondary current values are LED1-1 to 4, respectively.
It is represented by 4 bits of LED2-1 to 4.
If all the LEDs light up, it indicates that the current value has reached the limiter value.

【table】

[Table] In addition to the display contents during standby, the following contents can also be reported to the user using the LEDs 2-1 to 2-4 during arithmetic processing. In other words, LED2-1 lights up when the primary or secondary current control value reaches the upper limit, LED2-2 lights up when the bright/dark potential difference (contrast) is below 400V, and LED2-3 lights up when the contrast is below 500V. The lit LEDs 2-4 are used to determine whether the data sent from the sequence control 15' via DB0-3 is normal or abnormal. This is done by focusing on mutually complementary data V _D TS and V _SL TS in the combination of 4 bits of data sent as shown in Table 1 above, and when one of the data comes in, the LEDs 2-4 It is programmed to turn off the light. In the normal case, V _SL TS and V _D TS are repeatedly given to Q3 several times due to the overall copy sequence requirement, so LEDs 2 to 4 repeatedly blink. If the data being sent becomes abnormal due to a disconnection of the data line or a defect in the inverter Q10, the normal LED blinking order will be disrupted, making it possible to determine whether it is normal or abnormal. The clock for Q3 is obtained by an oscillation circuit using a transistor Q11 and a ceramic oscillator CR1. The oscillation signal generated at the collector of Q11 is pulse-shaped by the transistor Q12, and in this example,
It is given to Q3 as a 495kHz clock. or,
In the present invention, the above-mentioned DMS
Along with the mode terminal, connect R16 to pin 4 of J3 (measurement potential signal line supplied from the measurement circuit).
with a single touch at the same time as the terminal connected via the
It is configured so that it can be connected to GND. Therefore, it is possible to adjust the level of the A/D converter described above only by using a board equipped with a potential control circuit without any auxiliary means. In other words, if all pins 1 to 4 of J4 are connected, the OV equivalent voltage of the surface potential will be
While being supplied to the converter, in the DMS mode of Table 3, that is, if all terminals of J2 are left open, a display equivalent to Ov will appear on LEDs 1 and 2, so
VR1 may be adjusted so that the predetermined bits are displayed. (D/A Conversion) Q3 and D/A converter Q1 are connected by a total of five lines: a 4-bit data line (DA0 to DA3 input) and a Q1 control line (LDI input). Q3 determines whether the data to be D/A converted to Q1 is primary current control data, secondary current control data, light amount control data, or DC development bias control data at the rise of the signal to the LDI terminal.
Specify using 4 bits of signal given to DA0 to DDA3. Q1 also latches the data to DA0 to DA3 internally as 4 bits of actual control data at the rising edge of the signal to the LDI terminal. For example, if you repeat this operation twice, 8 bits of data will be
It is latched within 1. Q1 is capacitor C19,
4 bits counted by the clock oscillated by C20, C21, resistor R15, and coil L1,
It includes 6-bit and 12-bit binary counters, detects coincidence with the data sent to DA0-DA3, and outputs it to DAC1-4 as a pulse having a duty ratio proportional to the input data. DAC1 is connected to the match detection output with a 12-bit counter, DAC2 is connected to the match detection output with a 6-bit counter, and DAC3 and 4 are connected to the match detection output with a 4-bit counter, so the output of each resolution is can get. Q1 also has an internal expansion port function, and DA0
~Turn the port on/off depending on the data to DA3
can. In this example, we use PO1 of Q1 to
The ON/OFF and DAC3 outputs are combined through the corresponding resistors R13, increasing the resolution from the 4-bit equivalent of the DAC3 output to the equivalent of 5-bit. By doing this, we improved the accuracy of the DC developing bias control circuit connected to the DAC3 output. In addition, by turning PO8 ON/OFF, it is possible to switch the high-voltage output current value for transfer and pre-static neutralization, which will be described later, between full-size copying and variable-magnification copying. Since DAC1-4, PO1, and PO8 are open-drain outputs, they can be output via pull-up resistors.
Pulse output is pulled up to 12V.
DAC1~4 pulses are resistor R13 and capacitor C
It is integrated by an RC integration circuit consisting of 22 and becomes an analog voltage. The output of DAC4 is integrated by R13 and C22,
It appears at terminal P105 as a light amount control voltage. This voltage is applied to the inverting amplifier circuit Q14 of the light amount control circuit 17.
(See Figure 3) as a control voltage to the lamp regulator that varies in a range of approximately 13.6V to 16V.
3, and is led to the lamp regulator 14 shown in FIG. 1 via the 2nd pin of J1 to control the lighting voltage of the document exposure lamp 11. DAC1 output is pulse width modulation type 12-bit D/A
The output is input to the operational amplifier Q15 of the primary high voltage control circuit 18 through the terminal P106, which is integrated by the secondary filter composed of R13, C22 and R17, C23 (see Fig. 3), and is input to the operational amplifier Q15 of the primary high voltage control circuit 18 (see Figure 3).
It is taken out as a primary high voltage control voltage value of a predetermined voltage width through a resistor network by
It is input to the primary high voltage control circuit which is mainly composed of. In this example, the output pulse of DAC1 has a pulse width of about 3 ms per cycle, so in order to improve high-speed response and smoothing efficiency, integration is performed by R13 and C22 and integration by R17 and C23, and the integrator circuit is
It is structured in stages. On the other hand, the DAC2 output is integrated by the corresponding R13 and C22 and passes through the terminal P107 to the operational amplifier Q1.
7 and is taken out as a secondary high voltage control voltage value of a predetermined voltage width through a resistor network consisting of resistors R22 to R25, and is inputted to a secondary high voltage control circuit mainly composed of an operational amplifier Q18. Also, the DAC3 output is the corresponding R13, C22
is integrated and appears at terminal P108. The PO1 output further appears at this terminal via resistor R13,
Both voltages are combined. In this example, this composite voltage is selected to be 1/50 of the white ground potential (V _L2 +100V),
It is taken out as a DC developing bias control voltage and inputted to the non-inverting input of the operational amplifier Q19 of the DC developing bias control circuit 20 via a resistor R70 (FIG. 3). 1/50 of the DC developing bias value by the resistor network of R71 to R74 is applied to the inverting input terminal of Q19 via R27. Q19 is a high gain differential amplifier. DC developing bias control voltage and R of R71
A closed loop is constructed so that the 72 connection points have the same potential, and the DC developing bias voltage follows the control voltage with high precision. The Q19 output is applied to the midpoint of the inverter transformer T1 via a current booster consisting of Q20 and Q21. The above DC developing bias value is obtained by a combination of a variable output inverter whose oscillation output changes according to the output of Q19 and a fixed output inverter section formed by transformer T2. The variable output inverter is transistor Q22, Q2
3, Q22 and Q23 alternately turn on and off, and the stray voltage on the primary side changes to the secondary side determined by the winding ratio of T1 according to the DC developing bias control voltage applied to the midpoint of T1. After being boosted to the side voltage and half-wave rectified by D30, C3
Smoothed with 8 and set as DC development bias value R2
8, it is applied from pin 1 of J5 to the AC developing bias control circuit 23 in FIG. 1 as a DC superimposed component. On the other hand, in the fixed output inverter, a constant value of 24V is applied to the midpoint of the primary side of T2, and by rectifying and smoothing the secondary high voltage output according to the winding ratio of T2 with D31 and C41, a negative high voltage DC voltage is generated. For example -600V
get. This voltage is divided using resistors R30 to R35 and superimposed on the variable output inverter output as a negative DC bias, and the DC developing bias voltage is
It changes linearly from positive to negative in response to the control voltage. In the fixed output inverter section, in addition to the above-mentioned high-voltage fixed output, a single transformer also provides -5V power for the potential control circuit, 24V and 40V floating power for the surface potential side constant circuit, -600V high-voltage output, etc. That's what I do. (High Voltage Control) Next, high voltage control for the chargers 2 and 3 will be described. The above-mentioned primary high voltage control voltage is input to the inverting input of Q16 via R40. Also Q16
The non-inverting input of R4 is the primary high voltage output pulse obtained by sampling the primary high voltage current with resistor RS1.
1, R42, VR3 level-shifted voltage is R
43. These differential voltages are −
It is multiplied by R44/R40 and output from Q16. This output voltage is passed through resistor R45 to transistor Q24.
The current is amplified by the voltage, and is thereby taken out as a primary high-voltage voltage, which is input to the control input of the primary high-voltage transformer 21 via terminal 2 of J6. Terminal P10
The HV-1 signal given to J1 via 1 is “H”
In this case, LED-4 does not light up and diode D
10 is reverse biased, diode D11 is on, and transistor Q36 is on, so 1
The next high voltage transformer 21 does not operate. When the HV-1 signal becomes "L", LED-4 lights up, D10 becomes forward biased, D11 turns off, and Q36 turns off, so the output of Q16 is directly input to the base of Q24, turning on the primary high voltage transformer 21, and turning on the HV-1 signal. Next, it becomes possible to control high voltage transformers. For example, if the current to RS1 decreases due to fluctuations in the high voltage load, the voltage drop across RS1 will decrease, and VR3
The voltage at the midpoint increases. Therefore, the Q16 output increases, increasing the output of the high voltage transformer and increasing the current flowing to RS1. That is R40
Constant current high voltage control is performed according to the voltage applied to the voltage. Similar configurations include secondary charger 3 and transfer charger 2.
8. It is also used for high voltage control of the front static eliminator 29.
Here, when the feedback loop from the primary high voltage transformer becomes open, the output of Q16 becomes the maximum value, and 1
Since the next high voltage reaches the maximum, by turning on the diode D12 when the loop is open, it is possible to turn on the transistor Q36 and prevent the high voltage output. The secondary charging high voltage control voltage is connected to Q18 via R46.
Applied to non-inverting input. A voltage obtained by sampling the secondary high voltage current with the resistor R _S2 and level-shifting the secondary high voltage sample voltage value with R47, R48, and VR4 is applied to the inverting input via R49. These differential voltages are multiplied by R50 to R49 and output from Q18. This output voltage is Q through R51.
25, the current is taken out as a secondary high voltage control voltage, and the terminal 4 of J6 is connected to the secondary high voltage transformer 2.
2 control input. given to J1
When the HV-2 signal is "H", LED-5 is not lit and D9 is reverse biased and inverter Q26 is turned on, so the Q18 output is not transmitted to the high voltage transformer and the high voltage transformer is turned off. When the HV-2 signal becomes "L", LED-5 lights up, D9 becomes forward biased, and Q26 turns off, so the Q18 output is directly applied to the Q25 base, turning on the secondary high voltage transformer 22 and turning on the secondary high voltage. It becomes possible to control the transformer. Regarding the transfer high voltage control, normally in the same size copy mode, Q1 PO8 is set to "H", so Q28 output becomes "L" and connects to the parallel resistance of R52 and R53 via terminal P104. R5
A voltage obtained by dividing 12V by 4 is applied to the inverting input side of Q29 via R55. On the other hand, to the non-inverted side, a voltage obtained by level-shifting the voltage obtained by sampling the transfer current by RS3 by R56 and R57 is applied via R58, and the Q29 output is set so that both are equal. That is, the transfer high voltage transformer 26 is driven through the transistor Q30 and the terminal 6 of J6 to control the transfer high voltage. When changing magnification, PO8 switches to “L”,
Q28 is turned off and R54 and R are connected to the inverting input of Q29.
A voltage obtained by dividing 12V by 53 is applied via R55. This voltage is set to increase in proportion to the rate of change in the transfer current flowing through RS3 from the time of equal magnification to the time of variable magnification, so Q29
The output is reduced, and transfer high voltage control is performed so that a predetermined transfer current at the time of zooming flows into RS3. Regarding the high voltage control for pre-static elimination, during normal copying at the same size, as mentioned above, PO8 of Q1 is set to "H", so the Q31 output becomes "L" via terminal P104, and therefore the Q32 output becomes "H". It's getting old. Therefore, a voltage obtained by dividing 18V by R60 and R61 is applied to the non-inverting input of Q33 via R62. On the other hand, the pre-static elimination current is applied to the inverting input.
A voltage obtained by level-shifting the voltage sampled by RS4 by R63 and R64 is applied via R65. The Q33 output is determined so that both of them are equal, and the transistor Q34 is energized via R66 to control the pre-discharge high voltage. During zooming, PO8 goes to "L" as described above, so Q31 output goes to "H" and Q32 turns on.
Therefore, the parallel resistance of R67 and R62 and the +
A voltage obtained by dividing 18V is applied to the non-inverting input of operational amplifier Q33 via R62. Since this voltage is set to decrease in accordance with the rate of change in the transfer current flowing through RS4 from the time of equal magnification to the time of variable magnification, the output of Q33 decreases and eliminates static electricity before a predetermined period of time of variable magnification. Pre-neutralization high voltage control is performed so that current flows through RS4. The transfer high voltage and the pre-static elimination high voltage are turned on/off in synchronization with the primary high voltage turned on/off. In other words, when the HV-1 signal applied to pin 5 of J1 is “H”, the terminal P1
After passing through 01, D16 becomes reverse biased, D17 is turned on, and Q35 is also turned on. Therefore, D20 and D21 become forward biased, and the bases of Q30 and Q34 are clamped to approximately 0.7V, respectively, so that no control voltage is transmitted to the high voltage transformer, and the transfer/pre-discharge high voltage is turned off. When the HV-1 signal becomes “L”, D1
6 is forward biased, D17 is turned off, and Q35 is also turned off, so the Q29 and Q33 outputs respectively
30, Q34 is driven and transfers. The pre-static elimination high voltage is turned on. Also, for protection in case the feedback loop opens, Q35 is configured to be turned on/off from the feedback loop from the transfer high voltage transformer via D18, so if the loop becomes open, D18 will turn on. , Q35 is turned on, the high voltage output is turned off, and abnormal high pressure can be prevented from occurring. (Surface Potential Control) Next, the potential control sequence will be explained using FIG. 4. (Initial Set Routine) In step 1, S1 of Fig. 4A, first, after the start of 50, the RAM area is cleared by the reset signal (RESET) from the sequence controller (51), and then the primary high voltage control data ( PCCONTROLVALUE; PCV), primary high voltage standard data (PCSTANDARDVALUE; PSV), 2
Next high pressure control data (SCCONTROLVALUE;
SCV), secondary high voltage standard data (SCSTANDARDVALUE; SSV), weak secondary high voltage data (SCLSTRVALUE; SLV) and primary,
Data for each of these secondary magnification changes, exposure control data (HLCONTROLVALUE; HCV), and exposure standard data (HLSTANDARDVALUE;
HSV), development bias control data (DBCONTROLVALUE; DCV), development bias standard data (DBSTANDARDVALUE; DSV),
Development bias maximum value data (FDBVALUE;
FDV), various data necessary for internal arithmetic processing, initial values of various flags, etc. are stored in RAM.
(52). Next, clear each boat (53) and turn off the LEDs connected to the boats. The output port of the D/A converter is also set to the initial state (54). (Data Output Routine) In the following step 2, S2, a flag is determined to determine whether or not it is a post-rotation (55), and if it is a post-rotation, an SLV is output, and the process proceeds to step 3 (56). If there is no post-rotation, primary and secondary high pressures are output. At that time, it is determined whether there is charge control (CCC), and if it is, PCV,
Outputs SCV (57), if not, PSV, SSV
Output (58). (PCV and SCV are data judgment processing routines that will be described later, and are secured in a predetermined RAM area.) Each data value output routine of PCV, SCV, PSV, SSV, and SLV includes the scaling flag judgment inside. If the scaling flag is set (the flag is operated according to the input data in step 8 described later), the calculation is performed in step 12 described later. Outputs the data at the time of scaling that is saved or initially set in RAM (equivalent to the data at the same magnification x 0.7). In step 3, S3, the presence or absence of exposure amount control (HLC) is determined (58'), and if so, HCV (59) is output, and if not, HSV (60) is output. In addition, in step 4, S4, it is determined whether or not there is development bias control (DBC) (61), and if there is no development bias control (DBC), the
Output DSV (62). If yes, if the flag is set depending on the state of the FDB flag (a flag indicating that the maximum developing bias value is output) (the state of the flag is determined by data from the controller in the data discrimination processing routine described later). output) FDV (63, 64). If the flag is not set, check the DB flag (flag indicating that the predetermined developing bias value is output) (65).
If the flag is set, DCV (66) is output, and if it is not set, data corresponding to Ov is output (67). In the following step 5, S5, the scaling flag determined in the data judgment processing routine is checked based on the scaling command data from the controller (68), and if it is the same size (scaling flag off), the image is transferred. Set the static electricity removal control boat to the normal state (69). If the boat is in variable magnification mode, the boat is brought into a variable magnification state (70). In step 6, S6, it is determined whether the mode is DMS mode (a mode for performing various displays) (71), and if it is DMS mode, the process proceeds to a display routine (step 17) to be described later (c). If not in DMS mode, go to step 7. In step 7, S7, the controller
If the STROB signal is off, step 2,
Returning to S2 (72, A), the above steps, that is, the data output routine are repeated. STROB
When the signal turns on, the process moves to the data judgment and processing routine from step 8 (B). (Data Judgment Processing Routine) In steps 8 and S8 of FIG. 4B, the data (DB0 to DB3) from the sequence controller is input (73), and it is first judged whether it is "variable magnification data" according to Table 1 (74). ). For variable magnification (mode x 0.7),
After turning on the variable magnification flag and FDB flag, turn off the rotation flag and proceed to step 16 (75). If the data is not scaled, it is then determined whether it is "same scale data" (76). If it is equal magnification (mode x 1), the variable magnification flag,
Turn off the post-rotation flag (77), turn on the FDB flag, and proceed to step 16. Following the same-size data determination, it is determined whether or not it is "post-rotation (LSTR) data" (78), and if it is post-rotation, the post-rotation LSTR flag is turned on and the process proceeds to step 16 (79). In step 9, S9, if the data from the sequence controller is V _L2 TS (80), A/D conversion is started, and the V _L2 measured potential is converted into a digital value and saved (81). Next, calculate V _L2 +100V as developing bias control data. Save and go to step 16 (82). In step 10, S10, if the data from the sequence controller is V _L1 TS, A/D conversion is started (83), and the measured potential of V _L1 is converted into a digital value and saved (84). Next, it is determined whether or not there is exposure control, and if there is no control, the process directly proceeds to step 16 without changing the output data. If control is present, exposure control data: HCV _o = 1/20 (V _L1o - V _L10 ) + HCV _o-1 (However, the subscript n indicates the n-th control.
Also, V _L10 calculates the target convergence white background potential equivalent data value). Save and go to step 16 (86). In step 11, S11, if the data from the sequence controller is V _SL TS (87), the STRBLED indicating the arrival of the strobe signal is lit,
Start A/D conversion, convert the _VSL measurement potential into a digital value, and save it (88). Next, the portion related to _VSL of the primary and secondary high voltage control data (PCV, SCV) calculation is processed and the process proceeds to step 16 (89). In step 12, S12, if the data from the sequence controller is V _D TS (90),
Turn off the STRBLED, start A/D conversion, convert the V _D measurement potential to a digital value, and save it (91). Next, the presence or absence of charging control (CCC) is determined (92), and if there is no control, the process directly proceeds to step 16. When there is control, the area is bright. Contrast is calculated from the dark potential and the contrast is
If it is lower than 500V, LED2-3 will light up, and if it is lower than 400V, LED2-2 will light up. Next, PCV, SCV
And calculate and save PCV×0.7, SCV×0.7 (93),
If PCV or SCV reaches the upper limit
Lights up LED2-1 and reports an overview of the control status in real time. Also, in step 11 and step 12
STRBLED (LED2-4) lights up. It is determined whether the lights are turned off in a predetermined sequence, making it easier to discover abnormalities in the data line. In step 13 and S13, the data from the sequence controller is the developing bias ON “DBON”.
If (94), set the development bias on flag (DB flag), turn off the FDB flag, and proceed to step 16.
Go to (95). In step 14, S14, the data from the sequence controller is turned off, i.e., the developing bias is turned off.
If it is DBDFF (96), turn off both the DB flag and FDB flag and go to step 16 (97). In step 15, S15, the data from the sequence controller is set to the maximum developing bias value ON, i.e.
If FDBON (98), the DB flag is turned off and FDB
Turn on the flag and go to step 16 (99). In step 16, S16, the program waits until the strobe signal from the sequence controller turns off.
Once turned off, return to the output routine from step 2 (100). (DMS Routine) In step 17, S17, processing from this step is performed in the DMS mode. First, the primary, secondary, and exposure values are standard values (PSV,
SSV, HSV) Outputs the DC developing bias OV (101). In step 18, S18, data for display switching is input (102). Next, it is determined whether it is in DMS mode again (103),
If it is not the DMS mode, the LED display contents are returned to the contents of step 12 and the process returns to the output routine from step 2 (104). In step 19, S19, if the potential display mode (MED) is selected (105), A/D conversion is started, the measured surface potential data is displayed, and the process returns to step 18 (106). If it is not MED, go to the next step. In step 20, S20, if the _VD display mode is designated (107), the _VD data saved in the data judgment processing routine is displayed, and the process returns to step 18 (108). If it is not the _VD display mode, go to the next step (108). In step 21, S21, if the V _SL display mode is specified (109), the saved V _SL
Display the data and return to step 18. If it is not the V _SL display mode, go to the next step (110). In step 22, S22, if the V _L1 display mode is specified (111), the saved V _L1
Display the data and return to step 18. If it is not in V _L1 display mode, proceed to the next step (112). In step 23, S23, if the V _L2 display mode is selected (113), V _L2 is displayed and the process returns to step 18 (115). V If not in _L2 display mode, primary, secondary,
The control data is converted and displayed in 4-bit units and the process returns to step 18 (114). The operation of such an image forming apparatus as a whole will be explained with reference to FIG. First, when the main switch is turned on and the power is turned on, energization to the fixing heater starts. Then, the temperature of the fixing roller is set to the first temperature (150
℃), the photosensitive drum 1 starts rotating at a low speed (second speed). When the temperature of the fixing roller reaches the second temperature (170° C.), the photosensitive drum 1 starts rotating at a high speed (first speed). At the same time, high voltage suitable for high-speed rotation is applied to various chargers based on predetermined standard data, and pre-rotation is performed. Then, shift to potential controlled rotation,
Potential control as described above is performed. First, the flank exposure lamp is turned on and off to form a dark area and a bright area on the photosensitive drum 1, and their surface potentials V _D ,
Measure V _SL . Then, charge amount control data is obtained according to the detected potentials V _D and V _SL , and the obtained control data is stored in the RAM, and the charge amount of the primary charger 2 and secondary charger 3 is determined based on this control data. Adjust. This surface potential measurement and charge amount adjustment are repeated four times. Next, the original exposure lamp 11 is turned on to irradiate the standard white board with a standard amount of light, thereby forming a bright area, and measuring its surface potential V _L1 . Then, exposure amount control data is obtained in accordance with the measured potential V _L and stored in the RAM, and the exposure amount of the document exposure lamp 11 is adjusted based on this control data. This surface potential measurement and exposure amount adjustment are repeated three times. Next, the standard white plate is further irradiated with the adjusted exposure amount, and the surface potential V _L2 of the area formed thereby is measured. And this measured potential
Developing bias voltage control data during image formation is determined according to V _L2 and stored in RAM. After performing a post-rotation to electrostatically clean the photosensitive drum 1, the photosensitive drum 1 is stopped and enters a standby state. Next, the operation during image formation will be explained. In this case, the content of the control operation differs depending on the standing time from when the standby state is entered until the copy button is pressed. First, a case where the leaving time is 1 minute to 2 hours and the same size is selected will be described. When the copy key is turned on, the photosensitive drum 1 is rotated at high speed.
After operating the various chargers based on the charge amount control data stored in the RAM, potential control is performed in the same manner as when the power is turned on. However, in this case, the number of times of potential control is different from when the power is turned on, and the number of times of charge amount control is 2.
exposure amount control is performed once. After controlling the amount of charge and the amount of exposure, the surface potential V _L2 is further measured to obtain development bias control data, and then a same-size image forming operation is performed. In addition, when the leaving time is 1 minute to 2 hours and variable magnification is selected, the photosensitive drum 1 is rotated at high speed as when the same magnification is selected, and charge amount control is performed twice and exposure amount control is performed once. Furthermore, development bias control data is obtained. Then, based on the obtained charge amount control data, exposure amount control data, and development bias control data,
Based on the data obtained by multiplying by 0.7, various chargers, document exposure lamps, and developers are operated to form a variable-magnification image. In addition, if the standing time is less than 1 minute, charge amount control,
Exposure control is not performed. However, only the developing bias control data is obtained, and then the image forming operation is executed. As described above, according to the present invention, data obtained by performing a predetermined calculation on the control data at the same magnification during variable magnification image formation is used as the charge amount control data at the time of variable magnification. Even if variable-magnification image formation is selected for the first time after forming a 1-size image, the control data for variable-magnification is determined from the control data for 1-size magnification obtained when the power is turned on or when an image is formed at 1-size magnification. There is no need to detect the potential and obtain control data based on the process conditions, and it becomes possible to shorten the time required for image formation.

[Brief explanation of drawings]

FIG. 1 is a layout and configuration diagram of an image forming apparatus according to the present invention, FIGS. 2 and 3 are more detailed circuit diagrams of each control circuit in FIG. 1, and FIGS. 4A, B, and C explain various controls. The flowchart shown in FIG. 5 is an explanatory diagram illustrating the entire sequence. 1...Photosensitive drum, 2...Primary charger, 3...
Secondary charger, 4...Full exposure lamp, 5...Developing roller, 6...Blank exposure lamp, 7...Surface potential sensor, 10...Original, 11...Exposure lamp, 12, 13...Mirror, 28...Transfer charger, 29...Pre-static eliminator.

Claims (1)

[Scope of Claims] 1. An electrostatic latent image forming means comprising a charging means and forming an electrostatic latent image on the recording medium by charging the recording medium and exposing it to light; A developing means for developing a latent image, which drives the recording body at a first speed when forming an image of equal magnification, and drives the recording body at a second speed lower than the first speed when forming a variable magnification image. a driving means, a detection means for detecting a surface potential on the recording body, driving the recording body at the first speed after turning on the power or generating an image formation start command, and operating the charging means, control means for determining and storing control data for optimizing the surface potential of the recording medium during the formation of a 1:1 image based on the surface potential detection output detected by the 1:1 magnification image; When forming an image, the charging means is operated based on the control data to form a 1-size image, and when forming a variable-magnification image, the 1-size image is An image forming apparatus characterized in that the charging means is operated to execute variable magnification image formation based on data obtained by performing predetermined calculations on the control data at the time of formation.