JPH02136755A - Estimating method for current consumption - Google Patents
Estimating method for current consumptionInfo
- Publication number
- JPH02136755A JPH02136755A JP63290709A JP29070988A JPH02136755A JP H02136755 A JPH02136755 A JP H02136755A JP 63290709 A JP63290709 A JP 63290709A JP 29070988 A JP29070988 A JP 29070988A JP H02136755 A JPH02136755 A JP H02136755A
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- JP
- Japan
- Prior art keywords
- circuit
- information
- current consumption
- digital
- standard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 19
- 238000004088 simulation Methods 0.000 claims abstract description 16
- 230000033001 locomotion Effects 0.000 abstract 3
- 238000004364 calculation method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は主としてMOSディジタル回路等における消費
電流の見積り方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to a method of estimating current consumption in a MOS digital circuit or the like.
一般にこの種のMOSディジタル回路における消費電流
の見積りには、■アナログ的回路シミュレータを用いる
見積り方法、■人手計算に基づく概略的見積り方法等が
用いられている。Generally, for estimating current consumption in this type of MOS digital circuit, methods such as (1) an estimation method using an analog circuit simulator, and (2) a rough estimation method based on manual calculation, etc. are used.
■ アナログ的回路シミエレータを用いた見積り方法、
第3図は回路シミュレータを用いた見積り方法の主要過
程を示すフローチャートであり、消費電流の見積り対象
回路におけるトランジスタ等の素子レベルの要素及びこ
れらの接続情報21と、これら要素を動作させるアナロ
グ信号等の入力情報22とを、例えばキルヒホッフの方
程式を用いた直流解析、過渡応答解析等の連続的、即ち
アナログ的電気特性(電圧、電流)のシミュレーシヨン
が可能な回路シミュレータに入力して回路シミュレーシ
ョンを行い(S21) 、消費電流波形として結果デー
タ23を得、これに積分等の処理を施して消費電流見積
り値■1.を得る。■ Estimation method using an analog circuit simulator Figure 3 is a flowchart showing the main steps of the estimation method using a circuit simulator, which includes element-level elements such as transistors in the circuit whose current consumption is to be estimated and their connection information. 21 and input information 22 such as analog signals for operating these elements, continuous or analog electrical characteristic (voltage, current) simulation such as DC analysis or transient response analysis using Kirchhoff's equation is performed. A circuit simulation is performed by inputting the data into a possible circuit simulator (S21), and result data 23 is obtained as a current consumption waveform, which is subjected to processing such as integration to obtain an estimated current consumption value (1). get.
■ 人手による概略的見積り方法、
第4図は人手計算による概略的見積り方法の主要過程を
示すフローチャートであり、消費電流の見積り対象回路
の回路図31に基づき消費電流が特に大きいと予測され
る部分を人手によって抽出しく531) 、消費電流の
大きい部分と、その他の部分に分けて見積りを行う、こ
の抽出には、例えばCMOS回路(相補型MOS回路)
の消費電流■、1.は各ディジタル基本回路ユニット(
例えば論理ゲート回路)毎に下記(11式で与えられる
から、これを用いて消費を流の大きいと予測される部分
を推定し、この部分について実験による方法、或いは人
手計算による方法等にて詳細に見積る(S32)。■ Manual rough estimation method Figure 4 is a flowchart showing the main steps of the manual rough estimation method, showing the parts where the current consumption is expected to be especially large based on the circuit diagram 31 of the circuit whose current consumption is to be estimated. When manually extracting 531), estimates are made separately for parts with large current consumption and other parts.
Current consumption ■, 1. is each digital basic circuit unit (
For example, each logic gate circuit is given by Equation 11 below, so use this to estimate the part where the consumption is predicted to be large, and use an experimental method or manual calculation method to calculate the details of this part. Estimate (S32).
1、、、 = f −C・V+ f −1,l−+11
但し f・・・動作周波数
C・・・負荷容量
■・・・電源電圧
rva・・・貫通電流
他の部分については例えば(2)式等を用いて見積る(
S33) 。1,,, = f −C・V+ f −1,l−+11
However, f...Operating frequency C...Load capacity ■...Power supply voltage rva...Through current Other parts are estimated using equation (2), etc. (
S33).
1oss ’ = (f−で・■十下・冨)×論理ゲー
ト数
・・・(2)
但し、 T・・・動作周波数の平均
で・・・負荷装置の平均
I□・・・貫通電流の平均
なお、(2)式中論理ゲート数はディジタル基本回路ユ
ニットを示す。1oss' = (f-de・■10th・Ten)×Number of logic gates...(2) However, T...Average operating frequency...Average I□...of through-current of load device Note that the number of logic gates in equation (2) indicates the digital basic circuit unit.
消費電流の大きい部分について(11式を用いて得た消
費電流と、(2)弐に基づいて得たそれ以外の部分につ
いての消費電流とを加算しく534) 、消費電流見積
り値!。、3を得る。For parts with large current consumption (add the current consumption obtained using formula 11 and the current consumption for other parts obtained based on (2) 2)534), the estimated current consumption value! . , we get 3.
ところで前述した■アナログシミュレータを用いる消費
電流の見積り方法は小規模回路については精度よく見積
ることが出来るが、中、大規模回路については回路規模
の増大に従って大型で高速の計算機を必要とし、しかも
これによっても十分に対処できるとは限らず、経済的制
約が大きいという問題があった。By the way, the above-mentioned method of estimating current consumption using an analog simulator can provide accurate estimates for small-scale circuits, but for medium- to large-scale circuits, as the circuit size increases, a large and high-speed computer is required, and this method is difficult to estimate. However, there was a problem in that it was not always possible to fully deal with the problem, and there were significant economic constraints.
また■人手計算による概略的計算方法は精度が悪く、見
積りに多大の時間を要し、しかも見積る設計者の技術レ
ベルによって見積り精度が大幅にばらつく等の問題があ
った。In addition, the rough calculation method using manual calculations has problems such as poor accuracy, requiring a large amount of time to estimate, and the accuracy of the estimate widely varying depending on the technical level of the designer making the estimate.
本発明はかかる事情に鑑みなされたものであって、その
目的とするところは経済的に安価な計算機での処理が可
能で、しかも適正な精度で見積りが出来る消費電流見積
り方法を提供するにある。The present invention was made in view of the above circumstances, and its purpose is to provide a method for estimating current consumption that can be processed using an economically inexpensive computer and that can estimate with appropriate accuracy. .
本発明に係る消費電流見積り方法は、論理シミュレータ
にディジモル回路ニュットの動作定義情報と共にディジ
タル回路情報、入力情報を入力し、得られた論理シミュ
レーション結果情報である各ディジタル回路ユニット毎
の動作履歴情報と、予め求めである各ディジタル回路の
消費電流見積り一般式とに基づいて消費電流の見積りを
行う。The current consumption estimation method according to the present invention involves inputting digital circuit information and input information together with operation definition information of a DigiMole circuit unit into a logic simulator, and obtaining operation history information for each digital circuit unit, which is the obtained logic simulation result information. The current consumption is estimated based on the general formula for estimating the current consumption of each digital circuit, which is determined in advance.
本発明にあってはこれによって、回路シミュレーション
に代わる論理シミュレーションの結果とディジタル回路
毎の消費電流見積り一般式とを用いて消費xiを適切な
精度で、しかも効率的に消費電流を見積ることが可能と
なる。According to the present invention, it is possible to efficiently estimate the current consumption xi with appropriate accuracy using the results of logic simulation instead of circuit simulation and the general formula for estimating current consumption for each digital circuit. becomes.
以下本発明を図面に基づき具体的に説明する。 The present invention will be specifically explained below based on the drawings.
第1図は本発明に係る消費電流の見積り方法の主要過程
を示すフローチャート、第2図はタイムチャートである
。FIG. 1 is a flowchart showing the main steps of the current consumption estimation method according to the present invention, and FIG. 2 is a time chart.
先ず、論理シミュレーション対象回路の回路情報l、デ
ィジタル人力信号波形からなる入力情報2、各種ディジ
タル基本回路ユニットの動作を定義した動作定義情報3
、論理シミュレーション期間t、。11.内における回
路内の各個別ディジタル基本回路ユニットの動作M歴を
記憶させておくべき期間、即ち記憶スタート時間Cts
)、記憶エンド時間(tl)の設定時間4を論理シミ
ュレータに人力してt、。1m1間にわたって論理シミ
ュレーションを行い(Sl)、第2図(イ)、(ロ)、
(ハ)に示す如き各ディジタル基板回路ユニット毎の動
作履歴情報5を得る。First, circuit information 1 of the logic simulation target circuit, input information 2 consisting of digital human input signal waveforms, and operation definition information 3 that defines the operations of various digital basic circuit units.
, logical simulation period t,. 11. The period during which the operation M history of each individual digital basic circuit unit in the circuit should be stored, that is, the memory start time Cts
), the setting time 4 of the storage end time (tl) is manually entered into the logic simulator, and t. Logic simulation was performed over 1 m1 (Sl), and Figure 2 (a), (b),
Operation history information 5 for each digital board circuit unit as shown in (c) is obtained.
次に得られた動作履歴情報5に基づいて第2図(ニ)に
示す如き1−11間で対象回路内における各個別のディ
ジタル基本回路ユニット毎の発生イベント数6の抽出を
行う(S2)。Next, based on the obtained operation history information 5, the number of occurrence events 6 for each individual digital basic circuit unit in the target circuit is extracted between 1 and 11 as shown in FIG. 2 (D) (S2). .
なお、ここに1イベントとはディジタル基本回路のユニ
ット出力状態が、例えばローレベルーノ\イレベル→ロ
ーレベル、或いはハイレベル−ローレベル−ハイレベル
の如(2度変化した状態をいう。Note that one event here refers to a state in which the unit output state of the digital basic circuit changes twice, for example, from low level to low level to low level, or from high level to low level to high level.
またデータベースとして保持されている対象回路におけ
るLSIの平面的な構成であるパターン情117及び前
記パターン情報から寄生素子情報を抽出するうえでの抽
出ルール情報8に基づいて、対象回路内の寄生素子情t
1(主に負荷容量)の抽出を行い(S3)、各個別ディ
ジタル基本回路ユニット毎の寄生素子情報9を求める。In addition, parasitic element information in the target circuit is determined based on pattern information 117, which is a planar configuration of the LSI in the target circuit held as a database, and extraction rule information 8 for extracting parasitic element information from the pattern information. t
1 (mainly load capacitance) (S3), and parasitic element information 9 for each individual digital basic circuit unit is obtained.
一方予め、各種ディジタル基本回路ユニットの1イベン
ト当りの消費電流を与える一般式(負荷容量の関数)1
0、例えばインバータについての一般式(+Hv =
f +nv (C) 2人力NOR回路の一般式I2.
4゜、=f工。I (C)等を求めてお(。On the other hand, in advance, general formula (function of load capacity) 1 gives the current consumption per event of various basic digital circuit units.
0, for example, the general formula for an inverter (+Hv =
f +nv (C) General formula for two-person NOR circuit I2.
4°, = f-work. I (C) etc. (.
そして次に先に求めた各個別ディジタル基本回路ユニッ
ト毎のイベント数6.負荷容量9及び負荷容量の関数で
表わした消費電流を与える一般式10に基づき対象回路
内における各同種のディジタル基本回路ユニット群毎に
下記(3)、 (4)式に従って1、−1.間における
消費電流を計算する(S4)。Next, the number of events for each individual digital basic circuit unit obtained earlier is 6. Based on the load capacitance 9 and the general formula 10 which gives the current consumption expressed as a function of the load capacitance, 1, -1. The current consumption during the period is calculated (S4).
対象回路内における全てのインバータ(例えばn個)で
消費される電流の和11NV群は一般化して下記(3)
式で与えられる。The sum of the currents consumed by all the inverters (for example, n inverters) in the target circuit (11NV group) is generalized as follows (3)
It is given by Eq.
1++J’¥v=Σ(インバータにのイベント数)f
+Hv (CI+ )・・・(3)但し f INV
(Cm ) =インバータK(K=1−n)のイベント
当りの消費電流
また対象回路内における全ての2人力NOR回路(例え
ばm個)で消費される電流の和12NOR群は一般化し
て下記(4)式で与えられる。1++J'\v=Σ(number of events to inverter) f
+Hv (CI+)...(3) However, f INV
(Cm) = Current consumption per event of inverter K (K=1-n) and sum of current consumed by all two-person NOR circuits (for example, m) in the target circuit 12 The NOR group can be generalized as follows ( 4) Given by Eq.
1 gH01群=Σ(2NORKのイベント数) ・
fzNom(Cx )・・・(4)
但し f isog(Cm )−NOR回路回路K=1
−m)の1イベント当りの消費
電流
同様にして見積り対象回路内に存在する他の各種ディジ
タル基本回路ユニットについても、その各種回路毎に期
間1.−1.における消費電流を計算する。1 gH01 group = Σ (number of events in 2NORK) ・
fzNom(Cx)...(4) However, f isog(Cm) - NOR circuit K=1
-m) Current consumption per event Similarly, for various other digital basic circuit units existing in the circuit to be estimated, each circuit has a period of 1. -1. Calculate the current consumption at .
そして見積り対象回路における1、−1,間の総消費電
流I O12を下記(5)式に従って算出する(S5)
。Then, the total current consumption I O12 between 1 and -1 in the circuit to be estimated is calculated according to the following formula (5) (S5)
.
1、 −1゜
見積り対象回路内に、例えば発振回路等の特殊回路が存
在する場合には第3図に示す従来方法と同様に当該回路
についての回路シミュレーションを行って上記した各消
費電流とは別個にその消費電流11の見積り (見積り
値r、、lを行い、これらを(5)弐においてその分子
側に加算する。1. -1゜If there is a special circuit such as an oscillation circuit in the circuit to be estimated, perform a circuit simulation of the circuit in the same manner as the conventional method shown in Figure 3 and calculate the above-mentioned current consumption. Separately estimate the current consumption 11 (estimate values r, , l) and add these to the numerator side in (5) 2.
以上の如く本発明方法にあっては、従来の回路シミュレ
ーションに代えて論理シミュレーションを用いるから、
大規模なディジタル回路についても見積り値にばらつき
がなく適正な精度で、しかも効率的に消費電流の見積も
りが可能となるなど、本発明は優れた効果を奏するもの
である。As described above, in the method of the present invention, logic simulation is used instead of conventional circuit simulation.
The present invention has excellent effects, such as making it possible to efficiently estimate current consumption with appropriate accuracy and with no variation in estimated values even for large-scale digital circuits.
第1図は本発明方法の主要過程を示すフローチャート、
第2図はタイムチャート、第3.4図は夫々従来におけ
る消費電流見積り方法の主要過程を示すフローチャート
である。
1・・・回路情報 2・・・入力情報 3・・・各種デ
ィジタル基本回路ユニットの動作定義情報 4・・・動
作履歴情報を求める設定時間 5・・・動作履歴情報6
・・・各個別ディジタル基本回路ユニット毎のイベント
数 lO・・・各個別ディジタル基本回路ユニット毎の
消費電流一般式
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a flowchart showing the main steps of the method of the present invention;
FIG. 2 is a time chart, and FIG. 3.4 is a flowchart showing the main steps of the conventional current consumption estimation method. 1...Circuit information 2...Input information 3...Operation definition information of various digital basic circuit units 4...Setting time for obtaining operation history information 5...Operation history information 6
. . . Number of events for each individual digital basic circuit unit lO . . . General formula for current consumption for each individual digital basic circuit unit. In the drawings, the same reference numerals indicate the same or equivalent parts.
Claims (1)
の見積り対象回路における前記要素及びこれらの接続情
報を含む回路情報、前記各要素のディジタル動作定義情
報及び前記各要素を動作させるに必要なディジタル入力
情報に基づき論理シミュレーションを行い、前記各要素
夫々のディジタル動作履歴情報を求める過程と、 これらのディジタル動作履歴情報と、予め 求めた各要素毎の消費電流見積り一般式とに基づき見積
り対象回路の総消費電流の見積り値を算出する過程と、 を含むことを特徴とする消費電流見積り方 法。(1) Circuit information including the elements and their connection information in the target circuit for estimating current consumption including elements such as digital circuit units, digital operation definition information of each element, and digital input necessary to operate each element. A process of performing logical simulation based on the information and obtaining digital operation history information of each element, and calculating the total amount of the circuit to be estimated based on this digital operation history information and the general formula for estimating current consumption for each element obtained in advance. A method for estimating current consumption, comprising: a step of calculating an estimated value of current consumption.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63290709A JPH0682136B2 (en) | 1988-11-16 | 1988-11-16 | Current consumption estimation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63290709A JPH0682136B2 (en) | 1988-11-16 | 1988-11-16 | Current consumption estimation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02136755A true JPH02136755A (en) | 1990-05-25 |
JPH0682136B2 JPH0682136B2 (en) | 1994-10-19 |
Family
ID=17759504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63290709A Expired - Lifetime JPH0682136B2 (en) | 1988-11-16 | 1988-11-16 | Current consumption estimation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0682136B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6042613A (en) * | 1996-12-26 | 2000-03-28 | Ricoh Company, Ltd. | LSI design aiding apparatus |
US6493659B1 (en) | 1998-05-29 | 2002-12-10 | Nec Corporation | Power consumption calculating apparatus and method of the same |
JP2009237700A (en) * | 2008-03-26 | 2009-10-15 | Fujitsu Ltd | Method for estimating electric power of system lsi and method for generating electric power library of designed block used for the same |
US7900172B2 (en) | 2005-09-29 | 2011-03-01 | Fujitsu Limited | Method and apparatus for analyzing power consumption |
US8095354B2 (en) | 2006-09-06 | 2012-01-10 | Fujitsu Limited | Power consumption peak estimation program for LSI and device therefor |
-
1988
- 1988-11-16 JP JP63290709A patent/JPH0682136B2/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6042613A (en) * | 1996-12-26 | 2000-03-28 | Ricoh Company, Ltd. | LSI design aiding apparatus |
US6493659B1 (en) | 1998-05-29 | 2002-12-10 | Nec Corporation | Power consumption calculating apparatus and method of the same |
US7900172B2 (en) | 2005-09-29 | 2011-03-01 | Fujitsu Limited | Method and apparatus for analyzing power consumption |
US8095354B2 (en) | 2006-09-06 | 2012-01-10 | Fujitsu Limited | Power consumption peak estimation program for LSI and device therefor |
JP2009237700A (en) * | 2008-03-26 | 2009-10-15 | Fujitsu Ltd | Method for estimating electric power of system lsi and method for generating electric power library of designed block used for the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0682136B2 (en) | 1994-10-19 |
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