JPH0213274B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ultrasonic detection and display device for fish finders, depth sounders, and the like.

[Conventional technology]

For example, in a fish finder, information from a single detection is displayed as a vertical line on one end of the display screen of a cathode ray tube display, and older information is displayed as a vertical line on the other end of the display screen. Recording is performed in a format similar to display using recording paper, by displaying information and sequentially erasing the oldest information so that new information is always displayed at one end of the display surface.

By using a cathode ray tube, this display method can display more information than recording paper, and in particular uses a color cathode ray tube to display different colors depending on the level of the detection signal. When used and displayed, a large amount of information is displayed. By making the colors displayed stand out even when there are differences in level, it becomes possible to distinguish them, which greatly increases the readability, and it is convenient that enlarged display can be easily performed.

In such a fish finder, interference noise is removed by storing detection information for one display screen, and in the process of reading out the stored contents and obtaining a display signal, by correlating adjacent signals in the detection signal. A device with means for obtaining
55632 and has already been patented.

[Problem to be solved by the invention]

The above-mentioned device with interference removal means is particularly effective when the fishing ground is a sea area where small fishing boats are targeted and where fishing boats are crowded, so it is possible to provide a device that is easily and inexpensively configured for small fishing boats. There is an issue with the expectation that

[Means to solve the problem]

The present invention converts ultrasonic detection information obtained with a detection period into a digital signal with a plurality of digital values, and stores the stored contents of a main memory for one screen of a cathode ray tube display device on the display screen. The display signal obtained based on the readout signal read out according to the display period of is made such that the distance from the reference position of the display surface corresponds to the detection distance, so that the display signal corresponds to the digital signal within one detection period of the detection period. This is an ultrasonic detection and display device in which display signals are displayed in a single line in one scanning direction of a display screen on a display surface, and are arranged and displayed in descending order of detection period, In an apparatus for obtaining a display signal from which interference noise has been removed using a signal obtained by correlation processing of the signal, an adjacent signal extraction means obtains each adjacent digital signal in the read signal as an adjacent digital signal by applying the above read signal to a shift register. By applying each adjacent digital signal to a ROM that stores the processing contents for performing the above-mentioned correlation processing, a signal read out based on each digital value of each adjacent digital signal (hereinafter referred to as ROM read signal) is subjected to correlation processing. a correlation means that obtains a signal as a signal; and for each of the digital values, the ROM read signal is set to 0 only when both values of each digital value are 0 or 1, and when either value is 0 or 1. In other cases, the value obtained by removing the fraction of the average value of each digital value is stored in ROM.
The above-mentioned problem can be solved by a ROM means provided with the ROM storing the storage contents to be outputted as a read signal.

〔Example〕

Next, an embodiment of the cathode ray tube display and detection device according to the present invention will be described with reference to the drawings. This example is applied to a fish finder, in which a carrier wave pulse of an ultrasonic frequency is emitted from a transmitter 11 into the sea via a transducer 12, and is emitted from a seabed 13 or a school of fish 14 on the way. The reflected wave is received by the transducer 12. The received signal is converted into an electrical signal and amplified and detected by the receiver 15.

The transmission trigger that drives the transmitter 11 is transmitted at a cycle of _T1 and radiated into the water as shown in FIG. Reflected wave 17
is received as shown in FIG. 2B.

This detection information is transmitted to the receiver 1 for each ultrasonic pulse.
5, which is converted by the AD converter 19 into, for example, a 4-bit digital signal, that is, a signal of a plurality of digit digital values, according to its level, and stored in the buffer memory 21, for example, 256
sampling points are stored. That is, the buffer memory 21 contains the receiver 1 from the beginning of the trigger pulse.
5 outputs are sampled, and as shown in FIG. 2, the period _T2 , which is shorter than _T1 , is taken as, for example, 256 samplings. buffer memory 2
The digital information of No. 1 in the main memory 21 is transferred to the main memory section 22 and stored therein. The main memory section 22 has a storage capacity for displaying one screen of the cathode ray tube display device 23, and is read out periodically and displayed on the cathode ray tube display device 23.
For example, the display is shown on the display screen 2 as shown in FIG.
4, for example, the main scanning display line 25 is scanned from the left end to the right end, that is, main scanned in the horizontal direction, and sub-scanned from top to bottom, that is, sub-scanned in the vertical direction. Detection information is displayed up and down on the right edge. Therefore, since the number of sampling points for one detection information time _T2 is 256 in this example, the number of display lines 25 is also 256.

The newest detection information is displayed on the right edge of the display screen 24, the oldest information is displayed on the left edge,
As the display gets older, it moves to the left side and shows on the display screen 24 a transmission line 26 showing the transmission pulse 16 which is a leakage of the transmission pulse, a display 27 showing the reflected wave 17 from a school of fish, and a display showing the reflected wave 18 from the seabed. 28 are displayed respectively.

In this example, a color cathode ray tube is used as the cathode ray tube 23, and the signals are displayed in different colors depending on the input signal level.For example, the zero level, in this case, reflected waves from underwater are displayed in blue, and the largest level, for example, the ocean floor, etc. The reflected waves can be displayed in red. The trigger pulse period T ₁ is changed depending on the detection distance range, so-called range. The output of the reference oscillator 29, such as a crystal oscillator, is frequency-divided by a dividing period 31, and this frequency-divided output is supplied to a variable frequency dividing circuit 33. Variable frequency divider circuit 3
One of the three different frequency division ratio outputs is selected by the range selector switch 34, and the frequency divider 35
The frequency is divided by

The output of the frequency divider 35 is given to the transmitter 11 as a trigger pulse, and is also given to the buffer memory 21 as a data acquisition start signal. For example, the range selector switch 34 has eight ranges from 0 to 20 m,
0~40m, 0~80m, 0~160m, 0~320m, 0
The detection ranges are initially changed to ~640 m, 0 ~ 1280 m, and 0 ~ 2560 m, and as this range is increased, the period _T1 of the transmission pulse is lengthened. Since the number of samplings for one detection information is constant (256 in this example), as the range is lengthened, the clock frequency for loading data into the buffer memory 21 is also lowered. Therefore, the division period 3
The output of 1 is also given to a frequency divider 37, and as the output of this frequency divider 37, eight different frequency division ratio outputs are obtained. Information is given from the command circuit 39 to the selection circuit 38 according to each set value of the detection range, and the selection circuit 38 selects one signal from the eight outputs of the frequency dividing circuit 37, and this selects the data into the buffer memory 21. Provided as a clock for reading.

In order to control the cathode ray tube display 23, the output of the reference clock oscillator 29 is frequency-divided by a frequency divider circuit 41 and a frequency divider circuit 42 to produce a horizontal synchronization signal, and this horizontal synchronization signal is then applied to a frequency divider circuit 44. The vertical synchronization signal is created by dividing the frequency by .

These horizontal synchronizing signals and vertical synchronizing signals are applied to the cathode ray tube display 23 to control the electron beam of the display 23, so that the display screen is main-scanned and sub-scanned by the electron beam.

Furthermore, the output obtained by dividing the output of the reference oscillator by the frequency dividing circuit 41 is supplied to the transfer control circuit 43 in order to transfer the stored information of the buffer memory 21 to the main memory section 22, and the output is stopped after the period _T2 in FIG. The information in the buffer memory 21 is controlled to be written into the main memory section 22 during the retrace period of the vertical synchronization signal.

The output of the frequency dividing circuit 41 is also directly supplied to the main memory section 22 as a reading clock, and the information in the main memory section 22 is sequentially read out, passed through a signal processing circuit 48, a code conversion circuit 45, and then further to a decoder 47. The signal is converted into an analog signal and supplied to the cathode ray tube display device 23.

As a result, the display shown in FIG. 3 is always obtained as a still image, and when the detection information is obtained in the buffer memory 21, the information in the buffer memory 21 is transferred to the main memory during the retrace period of the next vertical synchronization signal. 22. As a result, as described above, the display contents of the display screen 24 are moved from the right end to the left end. The number of detection information lines displayed as vertical lines on the display screen 24 is determined by the capacity of the main memory section 22, and is set to 256 in this example. That is, the number of pixels displayed on the display screen 24 is 256 in both the vertical and horizontal directions, so the number is 65,536.

In this invention, as shown in FIG. 3, the display line 25 of the cathode ray tube display device 23 is displayed in the horizontal direction, whereas the one detection information line is displayed in the vertical direction. If the part indicated by is shown in more detail, it is constructed as surrounded by a dotted line 22 in FIG.

A signal is applied to the terminal 22e in order to transfer and write information from the buffer memory 21 to the main memory section 22. In this example, a RAM (random access memory) 75 is used as a storage element, and address counters 73 and 74 are provided corresponding to addresses A ₀ to _{A 15} to specify storage addresses. When writing the information in the buffer memory 21 to the RAM 75, the vertical synchronizer 6 is connected to the terminal 22b as shown in FIG. 6A.
3 signal is added, while AND gate 67
and 70 are opened and AND gates 68 and 71 are closed.

At this time, 256 clock pulses shown in FIG. 6B from the transfer control circuit 43 are applied to the address counter 73 through the terminal 22c and the AND gate 67 and the OR gate 69 for counting. When the address counter 73 counts 256 pulses, one carry pulse is output from the counter 73 and the address counter 74 counts 1 through the AND gate 70 and the OR gate 72.

While the address counter is operating in this manner, information from the buffer memory 21 is added to the RAM 75 through the terminal 22e, and further to the inverter 66.
A write operation is performed because the negative output of is applied to the read/write control terminal of the RAM 75.

Next, during a read operation, the terminal 22b becomes low level, AND gates 67 and 70 are closed, and AND gates 68 and 71 are opened. On the other hand, inverter 6
The positive output of 6 is applied to the RAM 75 and switched to read control.

The read address clock is gated from the terminal 22d with the horizontal (main scanning) synchronizing signal 60 by the AND gate 76. The signal shown enlarged in FIG. 6E is as follows.
Since the address is added to the address counter 74 through the AND gate 71 and the OR gate 72, the address
The dependent order of A ₈ to _{A 15} and addresses A ₀ to _{A 7} is reversed from that at the time of writing. and address counter 74
Instead of the carry pulse, a main scanning synchronization signal is applied to the address counter 73 from the terminal 22a through an AND gate 68 and an OR gate 69. That is, since the outputs A ₈ to _{A 15} of the address counter 74 take the value of a certain address at the beginning of reading, a carry pulse is generated in the middle while the address counter 74 counts 256 (during one main scan). is output, but the address counter 73 counts by 1 at the end point (or start point) of the main scan, and when the address counter 73 counts 256, scanning for one screen is completed.

Writing and reading of this situation and address A ₀ ~
The relationship of _A15 is shown in Figure 7. buffer memory 2
The first write to transfer 1 256-bit information to the RAM 75 changes the addresses _A0 to _A7 and writes from address 0 to address 255, and then moves to address 256 and enters the standby state for reading. . Next, during the first scanning line of reading, A ₀ to A ₇ are all 0, addresses A ₈ to _{A 15} change, and addresses A ₀ to _{A 7} change corresponding to the second scanning line and third scanning line. They are added one by one one by one.

Further, the second write is performed from address 256 to address 511, and the next read is performed from address 512.
By doing this, the shallowest information of the first detection information is written to address 0, and the 256th information of the first scanning line,
That is, the information at the next shallowest address 1 is displayed at the upper right corner of the display screen 24 and is displayed at the 256th position of the second scanning line. Also, the second written information is 256
The address information is displayed at the 256th position on the next first scanning line, at the upper right corner, in the same way as the first write information.
The first writing information at address 0 is displayed at the 255th position on the next main scanning line.

In this way, the address counters 73 and 74 are simply up counters, and by simply changing the input/output connections through write and read control, the oldest information on the display screen 24 can be rewritten to the latest information. Display information can be sent to the left on the display screen 24, and the latest information can be displayed on the right end.

The differentiating circuit 77 differentiates the vertical (sub-scanning) synchronizing signal and resets the address counter 73. Under normal operation, the reset circuit is not required, but if for some reason the address counter 73 is reset.
This is provided to prevent this from occurring if the relative positions in the depth direction on the display screen 24 are miscounted. The signal processing circuit 48 includes a 2-bit shift register 79 and a 2-bit shift register 79 as shown in FIG.
It is composed of a ROM 78, and a shift pulse is applied from a terminal 48a. The information read from the RAM 75 passes through the shift register 79 and is applied to the ROM 78 as the D ₁ output of the shift register 79 and the D 2 output that is delayed by one bit, that is, the readout is adjacent to the D ₂ output. ROM78 is a code converter and D ₁ ,
The two pieces of information in D ₂ are converted into another piece of information.

As an example, shown in FIG. 8, a value from 0 to 7 is output for each value from 0 to 15 for _D1 and _D2 . As can be seen from the figure, 0 is output only when the values of both D ₁ and D ₂ are 0 or 1, and when either D ₁ or D ₂ is 0 or 1, and other In this case, the stored contents are such that the fractions of the average values of D ₁ and D ₂ are removed and output, so that the following interference removal effect can be obtained.

In other words, in a fish finder, the normal reflected reception signal does not have an extreme difference between one detection information and the next detection information, so it is unlikely that the previous detection information will be received with no signal and the current one will be received at a strong level. . On the other hand, interference noise caused by the direct reception of signals transmitted by other fish finders is generally strong, so if either D ₁ or D ₂ has no signal, forcing it to have no signal will effectively eliminate interference. be. In the example of Figure 8, RAM75 has
As mentioned above, it is stored at a level of 0 to 15 converted into a digital value of multiple digits, and it is displayed at half the level of 0 to 7, which seems to be a waste, but the characteristics By changing the address of the ROM 78 with the changeover switch 49, a different numerical value based on the combination of D ₁ and D ₂ is outputted from the ROM 78, so that effective display characteristics depending on the purpose can be obtained. Although the shift register 79 may have a 1-bit register, a 2-bit register is used to also serve as waveform shaping.

This cathode ray tube display detector further includes a distance scale on the display screen 24, as shown in FIG. The counter 80 in FIG. 1 is reset by the vertical synchronizing signal 63 and counts the horizontal synchronizing signal 60 which is the output of the frequency dividing circuit 42, as shown in FIG. 9C. The counter 80 in this example is composed of six stages, and its outputs are _Q1 to _Q6 .

The decoder 92 receives the outputs Q ₁ to _{Q 4} of the counter 80.
are connected to the decoder 91, and the outputs _Q1 to _Q6 of the counter 80 are connected to the decoder 91, and the outputs of both decoders appear when all inputs become 0. Therefore, the output of the decoder 91 is output during the reset period of the counter 80 and for one cycle of the horizontal synchronizing signal every time the counter 80 counts 64 horizontal synchronizing signals, as shown in FIG. 9E.

Similarly, the output of the decoder 92 is determined by the reset period of the counter 80 and the reset period of the counter 80 as shown in FIG. 9D.
is output for one cycle of the horizontal synchronizing signal every time the horizontal synchronizing signal is counted 16 times. The output of decoder 91 is led to code conversion circuit 45 via OR gate 94 and AND gate 89. On the other hand, decoder 9
The output of 2 is controlled by an AND gate 93 and then similarly led to an OR gate 94.

A horizontal synchronizing signal 60 shown in FIG. 10F is applied to the one-shot multivibrator 83, and the one-shot multivibrator 83 operates for a period _T3 as shown in FIG. 10G. This operating period T ₃ is designed to be arbitrarily changed by a variable resistor 84.

Since the output of the one-shot multivibrator 83 resets the frequency divider 86, the frequency divider 86 becomes ready for operation after the _T3 period ends. At this time, the output of the frequency divider 86 is positive as shown in FIG. 10J, so the output of the frequency divider circuit 41 is applied to the frequency divider 86 through the AND gate 85 and is frequency-divided. When the output of the frequency divider 86 becomes negative, the AND gate 85 is closed and the operation is stopped. During this period, the Qm output of the frequency divider 86 becomes as shown in FIG. 10H, and since this output controls the AND gate 93, the signal for dividing the display screen 24 into 16 shown in FIG. As shown in FIG. 4, it appears as a broken line. The code conversion circuit 45 is an AND gate 8
9 is output, the circuit forcibly converts it into a specific code regardless of the information content of the signal processing circuit 48, for example, the distance scale 5 on the display screen 24.
When 1 and 52 are displayed in white, they are converted into a code compatible with white display. Scale connection/disconnection switch 88
If the contact point is set to the b side, the output of the AND gate 89 is suppressed, and the display is instantly turned off. Also, by changing the division ratio with the output Qm of the frequency divider 86, the fine scale display 52 in FIG.
Needless to say, the number and width of broken lines can be changed.

〔Effect of the invention〕

According to the present invention, as described above, the shift register 79 extracts adjacent digital value signals from the readout signal from the main memory 22 and supplies them to the ROM 78 for correlation processing. The signal given to the ROM 78 is waveform-shaped and its operation is stabilized.
Since correlation processing is performed only by reading out the ROM 78, processing time can be shortened and processing can be performed quickly.

In addition, the stored contents of the ROM 78 output 0 only when both values of each digital value are 0 or 1, or when either value is 0 or 1, and in other cases, the average value of each digital value is output. Since we are trying to output the value with the fraction removed,
Since the number of digits of the digital value stored in the main memory 22 can be nearly twice as large as the number of digits of the display signal, the fish school signal is not affected by small noise such as interference noise or underwater noise. Shift registers and
It has the advantage of being able to be provided simply and inexpensively by simply installing a ROM.

[Brief explanation of drawings]

The drawings show an embodiment: FIG. 1 is a block diagram, FIGS. 2, 6, 9, and 10 are waveform diagrams for explaining the present invention, and FIGS. 3 and 4 are display screens. FIG. 5 is a partially detailed view of an embodiment of the present invention, and FIGS. 7 and 8 are tables for explaining the present invention. 11...Transmitter, 12...Transducer, 13...Seafloor,
14...Fish school, 15...Receiver, 16...Leakage of transmitted pulse, 17...Reflected wave from fish school, 18...Reflected wave from seabed, 19...AD converter, 21...Buffer memory,
22... Main memory section, 23... Cathode ray tube display device, 2
4... Display screen, 25... Display line, 26... Display transmission line, 27... Display fish school, 28... Seabed display, 29
...Reference oscillator, 31... Frequency divider, 33... Variable frequency divider circuit, 34... Range selection switch, 35... Frequency divider,
37... Frequency divider, 38... Selection circuit, 39... Command circuit, 41... Frequency division circuit, 42... Frequency division circuit, 43... Transfer control circuit, 44... Frequency division circuit, 45... Code conversion circuit, 46... Signal processing Circuit, 47...Decoder, 4
8...Signal processing circuit, 49...Characteristics changeover switch, 5
1...Coarse scale display, 52...Fine scale display, 60...Horizontal synchronization signal, 61...Coarse scale signal, 62...Fine scale signal, 63...Vertical synchronization signal, 66...Inverter, 6
7...and gate, 68...and gate, 69...
OR gate, 70...AND gate, 71...AND gate, 72...OR gate, 73...address counter, 74...address counter, 75...RAM,
76...AND gate, 77...differentiation circuit, 78...
ROM, 79...Shift register, 80...Counter, 81...Switching circuit, 82...Differential circuit, 83...One-shot multivibrator, 84...Variable resistor, 85...And gate, 86...Frequency divider, 87...
Display position determination circuit, 88...Scale connection/disconnection switch, 8
9... Inverter, 90... Frequency divider, 91... Decoder, 92... Decoder, 93... AND gate, 94
…orgate.

Claims (1)

[Scope of Claims] 1. Storage contents of a main memory that stores one screen of a cathode ray tube display device by converting ultrasonic detection information obtained over a detection period into a digital signal based on a plurality of digital values. The display signal obtained based on the read signal read out according to the display period of the display surface is set such that the distance from the reference position of the display surface corresponds to the detection distance, and one detection period of the detection period. The display signals corresponding to the digital signals in the display screen are displayed in one line in one scanning direction of the display scan of the display surface, and are arranged in descending order of the detection period. The detection and display device is a device for obtaining the display signal from which interference noise has been removed using a correlation-processed signal of the readout signal, comprising the steps of: (a) supplying the readout signal to a shift register to detect each adjacent signal in the readout signal; Adjacent signal extraction means for obtaining a digital signal as an adjacent digital signal; b. Based on each digital value of each adjacent digital signal by providing each of the adjacent digital signals to a ROM that stores processing contents for performing the correlation processing. The read signal (hereinafter,
ROM correlation processing means for obtaining a ROM read signal (referred to as a ROM read signal) as the correlation-processed signal. 2. The device according to claim 1, wherein: (a) for each of the digital values, only when both values of each digital value are 0 or 1 and only when either value is 0 or 1; Said ROM
The ROM is provided with storage contents for outputting a read signal by setting it to 0 and, in other cases, outputting a value obtained by deleting a fraction of the average value of each digital value as the ROM read signal.
An apparatus characterized by comprising ROM correlation processing means.