JPH02125540A - Data transmitting equipment - Google Patents

Abstract

PURPOSE:To prevent the ineffective selection of an insert signal by outputting an insert timing from an insert timing generating circuit to a selection circuit when an insert request signal from a transmission interface circuit represents as effective. CONSTITUTION:A transmission interface circuit 50 outputs an insert request signal (j) representing effective/ineffective state of an insert signal (g) to other input terminal of an AND gate 33. When the insert signal (g) is effective, the AND gate 33 is set and an output signal (i) from an insert timing generating circuit 31 passes through the AND gate 33. A selection circuit 32 based on an insert timing of the inputted output signal (i) outputs the insert signal (g) inputted to an input terminal B from an output terminal Y as a transmission frame (h). Moreover, when the insert signal (g) inputted to the selection circuit 32 is ineffective, the output signal (i) from the insert timing generating circuit 31 is not outputted to the selection circuit 32 and the transmission frame (h) outputted from the selection circuit 32 is a signal of a reception frame (a).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drop insert type data transmission device used in the information communication field.

[Conventional technology]

When this type of drop insert type data transmission device receives a received frame related to data transmission, it converts this received frame into a drop signal, further converts this drop signal, and outputs received data. Further, this data transmission device converts input transmission data into an insert signal, and inserts this insert signal into the above-mentioned reception frame to use it as a transmission frame related to data transmission.

An example of such a data transmission device is shown in FIG.

The conventional data transmission device shown in FIG. 2 receives a synchronization detection circuit 60 for received frame a, a drop circuit 70 for received frame a, a drop signal from the drop circuit 70, and a received clock C. A reception interface circuit 90 that converts a drop signal S into reception data d, a transmission interface circuit 100 that converts transmission data e into an insert signal g, a selection circuit 82 that inserts an insert signal g into a reception frame a, and a transmission interface circuit. 100 and an insert timing generation circuit 81 that outputs a transmission clock f to a selection circuit 82 and an output signal i to a selection circuit 82. Further, the insert section 80 includes an insert timing generation circuit 81 and a selection circuit 82.

Such a conventional data transmission device inserts an insert signal g into a received frame a, based on an output signal i from the insert timing generation circuit 81, as a transmitted frame h. That is, the output signal i of the insert timing generation circuit 81 is used as the selection input of the selection circuit 82.

[Problem to be solved by the invention]

The conventional data transmission device described above uses the output signal of the insert timing generation circuit as the selection input of the selection circuit. Therefore, when the transmission interface circuit is out of order,
or when the transmission interface circuit is removed.
There is a drawback that an invalid insert signal is selectively output by the selection circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission device that can eliminate such drawbacks and prevent selection of invalid insert signals.

[Means to solve the problem]

The present invention provides an insert signal into which transmission data has been converted.
When converting the transmitted data and outputting the insert signal in the data transmission device that inserts it into the received frame,
a transmission interface circuit that outputs an insert signal indicating the validity of this insert signal; an insert timing generation circuit in which the insert timing of the insert signal is set in advance; and a a selection circuit that inserts an insert signal from the transmission interface circuit into a received frame at an insert timing of the circuit; and a selection circuit that selects the insert timing from the insert timing generation circuit when the insert request signal from the transmission interface circuit indicates validity. It is characterized by having a gate that outputs to the circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This data transmission device includes a synchronization detection circuit 10, a drop circuit 20, an insert section 30, a reception interface circuit 40, and a transmission interface circuit 50. Further, the insert section 30 includes an insert timing generation circuit 31, a selection circuit 32, and an AND gate 33.

In the data transmission device having such a configuration, the synchronization detection circuit 10 is connected to the drop circuit 20 and the insert timing generation circuit 31 of the insert section 30, and uses the received frame a as an input signal.

The drop circuit 20 uses the output signal output from the synchronization detection circuit 10 as a timing trigger.

Then, the reception clock C and the drop signal S obtained by converting the reception frame a are outputted to the reception interface circuit 40.

The reception interface circuit 40 converts the drop signal from the drop circuit 20 and outputs reception data d.

The transmission interface circuit 50 receives the received data e and the transmission clock f from the insert timing generation circuit 31.
is input, converts the received data e, and outputs the insert signal g to the selection circuit 32. At the same time, the transmission interface circuit 50 outputs an insert request signal j indicating whether the insert signal g is valid or invalid to the AND gate 33.

Insert timing generation circuit 31 of insert section 30
uses the output signal from the synchronization detection circuit 10 as a timing trigger. Furthermore, the insert timing of the insert signal g is set in advance in the insert timing generation circuit 31. Then, the insert timing generation circuit 31 outputs an output signal i related to this insert timing.

The AND gate 33 receives an output signal i from the insert timing generation circuit B31, which is manually input to one input terminal, and
A logical product is performed with the insert request signal j from the transmission interface circuit 50, which is input to the other input terminal. This determines whether the output signal i is output to the selection circuit 32 or not. That is, when the insert signal g input to the selection circuit 32 is valid, the insert request signal j indicates that the insert signal g is valid. This insert request signal j turns the AND gate 33 into the "on" state,
Output signal i is output to selection circuit 32. Further, when the insert signal g is invalid, the insert request signal j indicates that the insert signal g is invalid. This insert request signal j
As a result, the AND gate 33 becomes "off" and the output signal i is not output.

When the output signal i is input to the selection input terminal S, the selection 0 path 32 outputs the insert signal g input to the input terminal B.
It is output as a transmission frame h from output terminal Y at the insert timing indicated by output signal i. Furthermore, when the output signal i is not input, the selection circuit 32 outputs the reception frame a input to the input terminal A as a signal of the transmission frame h.

Next, the operation of this embodiment will be explained.

When a received frame a is manually input to the data transmission apparatus of this embodiment, this received frame a is input to the synchronization detection circuit 10, the drop circuit 20, and the insert section 30.

A drop circuit 20 uses the signal output from the synchronization detection circuit 10 as a timing trigger to detect the reception clock C.
Then, a drop signal obtained by converting the received frame a is output to the receiving interface circuit 40. A reception interface circuit 40 converts this drop signal d and outputs reception data d.

On the other hand, the transmission interface circuit 50 receives the transmission data e.
and a transmission clock f from the insert timing generation circuit 31. The transmission interface circuit 50
The transmission data e is converted into an insert signal g and outputted to the selection circuit 32. At the same time, the transmission interface circuit 50
outputs an insert request signal j indicating whether the insert signal g is valid or invalid to the other input terminal of the AND gate 33. Further, the insert timing generation circuit 31 outputs an output signal i related to the insert timing of the insert signal g to one input terminal of the AND gate 33.

As described above, the received frame a input to the insert section 30 is input to the input terminal A of the selection circuit 32.

The insert signal g is input to the input terminal B of the selection circuit 32. When this insert signal g is valid, the insert request signal j indicates that the insert signal g is valid. When this insert request signal j is input to the other input terminal of the AND gate 33, the AND gate 33 is turned on.

That is, the output signal i from the insert timing generation circuit 31 passes through the AND gate 33. Then, the output signal i is input to the selection input terminal S of the selection circuit 32.

The selection circuit 32 outputs the insert signal g inputted to the input terminal B from the output terminal Y as a transmission frame h based on the insert timing of the inputted output signal i.

Furthermore, when the insert signal g input to the selection circuit 32 is invalid, the AND gate 33 is turned off by the insert request signal j indicating invalidity.

As a result, the output signal i from the insert timing generation circuit 31 is not output to the selection circuit 32, and the transmission frame h output from the selection circuit 32 becomes the signal of the reception frame a.

In this way, the transmission frame becomes an insert signal only at the timing preset in the insert timing generation circuit and when the insert signal from the transmission interface circuit is valid, that is, the insert request signal from the transmission interface circuit is valid. , otherwise, it becomes a received frame signal. In other words, when the insert signal from the transmission interface circuit is invalid, that is, when the insert request signal from the transmission interface circuit indicates invalidity, the transmission frame becomes the signal of the reception frame even at the insert timing.

Note that I:N using the data transmission device according to this embodiment
Alternatively, when performing N:N communication, it is possible to prevent a malfunctioning data transmission device from inserting an invalid insert signal.

〔Effect of the invention〕

As explained above, according to the present invention, when the transmission interface circuit is out of order or when the transmission interface circuit is removed, the selection circuit does not selectively output an invalid insert signal, and the signal of the received frame is There is an effect that can be used as the output of the selection circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional data transmission device. 10... Synchronization detection circuit 20... Drop circuit 30... Insert section 31... Insert timing generation circuit 32, 33, 40, 50, Selection circuit, AND gate, Reception interface circuit/transmission interface circuit

Claims (1)

[Claims] (1) In a data transmission device that inserts an insert signal obtained by converting transmission data into a reception frame, when converting transmission data and outputting an insert signal, a transmission that outputs an insert request signal indicating the validity of this insert signal. an interface circuit; an insert timing generation circuit in which an insert timing of an insert signal is set in advance; and an insert timing generation circuit that generates an insert signal from the transmission interface circuit at an insert timing of the insert timing generation circuit when a received frame is output as a transmission frame; and a gate that outputs the insert timing from the insert timing generation circuit to the selection circuit when the insert request signal from the transmission interface circuit indicates validity. Data transmission equipment.