JPH02119266A - Solid-state image sensing device of vertical type overflow drain structure - Google Patents

Abstract

PURPOSE:To set a reverse bias voltage actuating an operation of an electronic shutter to a low voltage by a method wherein a low-concentration epitaxial layer of a first conductivity type is formed on a semiconductor substrate of the first conductivity type and a well, of a second conductivity type, composed of a first region whose bottom is shallow and of a second region whose bottom is deep is formed on the epitaxial layer. CONSTITUTION:A well, of a second conductivity type, composed of a first region 16 whose bottom is shallow and a second region 17 whose bottom is deep is formed on a low- concentration epitaxial layer 30, of a first conductivity type, of a semiconductor chip where the epitaxial layer 30 of the first conductivity type has been formed on a semiconductor substrate 15 of the first conductivity type. A photoelectric conversion region 18 is formed on a main face of the first region 16; a signal readout means receiving an electric charge from the photoelectric conversion region 18 is formed on a main face of the second region 17. For example, it is desirable that an impurity concentration in the epitaxial layer 30 is by one digit lower than the impurity concentration of at least the substrate 15. Thereby, when a substrate bias to be applied between the first region and the second region 16, 17 and the substrate 15 is changed while optical information is stored in the photoelectric conversion region 18, a shutter can function at a low voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an imaging device with a vertical overflow drain structure using a charge transfer device.

[Conventional technology]

As an imaging device using a charge transfer device, a method called an incline transfer method has rapidly developed. In particular, since a pixel structure called a vertical overflow drain structure that suppresses blooming was proposed, the density has increased and it has become possible to obtain characteristics that exceed those of image pickup tubes. Furthermore, by taking advantage of the features of the vertical overflow drain structure, electronic shutter operation has become possible, making it possible to obtain an imaging device with new functions.

FIG. 5 is a block diagram of an imaging device with a vertical overflow drain structure using an interline transfer method, which includes a plurality of columns of vertical shift registers 10 driven by the same charge transfer electrode group, and adjacent vertical shift registers 10 on one side of each vertical shift register. A photoelectric conversion section 11 electrically isolated from each other, a transfer gate region 12 for reading signal charges stored in the photoelectric conversion section to a vertical shift register, a horizontal shift register 13 provided at one end of each vertical shift register, and It consists of a device 14 for detecting signal charges.

FIG. 6 is a longitudinal sectional view of the semiconductor chip, taken along the line AA' in the imaging device of FIG. 5. FIG.

A P-well is formed in an N-type semiconductor substrate 15 made of silicon, consisting of a first region with a shallow junction and a second region with a deep junction. An N-type region is formed in the first region 16 and acts as a photoelectric conversion region 18 .

In the deep second region 17, there is a vertical shift register (one buried channel, transfer electrode 21) consisting of a buried channel CCD.
> is formed, and its main surface is covered with an insulating layer 20 such as S f 02.
A transfer electrode 21 is arranged via the. A vertical shift register (
19) are separated by a channel stop region 22 made of a highly P-type impurity layer. In addition, the photoelectric conversion area 18
A transfer gate region 23 is arranged between the vertical shift register 19 and the corresponding vertical shift register 19. Further, parts other than the photoelectric conversion section 18 are shielded from light by a metal layer 24 such as A1, for example.

Blooming can be suppressed by connecting the N-type semiconductor substrate 15 and the P-well (
16 and 17) to completely deplete the shallow portion of the P-well directly below the photoelectric conversion section 18.

FIG. 7 schematically shows a potential distribution diagram in the depth direction indicated by the broken line in FIG.

When the transfer gate region 23 is turned on, the voltage of the N-type region of the photoelectric conversion section 18 is set as shown by a curve 25. At this time, a substrate voltage 28 is applied so that the first region of the P-well is completely depleted. When optical information is stored in the photoelectric conversion region 18, the transfer gate region 23 is turned off. The N region potential of the photoelectric conversion region 18 becomes shallow as shown by a curve 26 due to the accumulated electrons. However, even if strong light is irradiated, if the state of curve 27 is reached, the photoelectric conversion area 1
8 (N type) and the first region 16 are in the forward direction, all the generated signals are swept out to the substrate and blooming is suppressed.

That is, in the vertical overflow cell structure, blooming can be suppressed by the substrate voltage. If the substrate voltage 28 is further increased, it becomes possible to sweep out all the generated charges to the substrate as shown in the two curves. Using this phenomenon, an electronic shutter function that electrically controls the storage time becomes possible.

[Problem to be solved by the invention]

In the conventional solid-state imaging device with the vertical overflow drain structure described above, in order to provide an electronic shutter function, the reverse bias voltage applied to the P well and the substrate must be 30V to 100V.
This requires a high voltage on the order of V, which requires the drive circuit and the imaging device to have high voltage resistance, which has the drawback of poor reliability.

An object of the present invention is to reduce the reverse bias voltage to enable electronic shutter operation in a solid-state imaging device having a vertical overflow drain structure.

[Means to solve the problem]

A solid-state imaging device having a vertical overflow drain-drain structure according to the present invention includes a semiconductor chip having a first conductivity type epitaxial layer formed on a first conductivity type semiconductor substrate.
It has a second conductivity type well formed in a conductivity type epitaxial layer and consisting of a first region with a shallow bottom and a second region with a deep bottom, and a photoelectric conversion region provided on the main surface of the first region and the second region with a deep bottom. and signal readout means provided on the main surfaces of the two regions and receiving charges from the photoelectric conversion region.

〔Example〕

Next, the present invention will be explained using the drawings.

Hereinafter, an N-channel solid-state imaging device according to an embodiment of the present invention will be described.

FIG. 1 is a longitudinal cross-sectional view of a semiconductor chip showing an embodiment of the present invention, and similar to FIG. 6 described in the conventional example, the interline transfer type charge transfer imaging device shown in FIG. It shows a cross section above the edge line.

In FIG. 1, areas having the same functions as those in FIG. 6 are indicated by the same symbols. The difference between the conventional example shown in FIG. 6 and the present invention is that an N-type epitaxial layer W30 with a low impurity concentration is formed on an N-type semiconductor substrate 15.

FIG. 2 schematically shows the impurity concentration distribution in the depth direction indicated by the broken line in FIG. The density corresponds to the area marked with the symbol at the top of Figure 2. Also, the concentrations in FIG. 2 are relative.

In an actual device, the concentration of impurities (curve 31) in the N-type semiconductor substrate 15 is preferably 1015 to 1018/h. It is desirable that the impurity concentration of the epitaxial layer 30 (curve 32) is at least an order of magnitude lower than the substrate concentration. The actual value is 1014 ~
1016/- is appropriate. The density (curves 33 and 34) of the first region 16 and the N region 18 of the photoelectric conversion region may be set to a value commensurate with the blooming suppression voltage and the saturation signal amount.

FIG. 3 shows the potential distribution in the depth direction indicated by the broken line in FIGS. 1 and 2. FIG. Curve 35. ．． 36.37 schematically shows the potential distribution when the substrate voltage is increased, and the first region 16 and the N-type epitaxial layer 713 are
When the depletion layer of 0 expands and reaches the N-type semiconductor substrate 15 with a high impurity concentration, the width of the depletion layer hardly increases and the substrate bias is mostly used to deepen the potential of the first region. Therefore, by selecting the width of the N-type epitaxial layer and the substrate concentration, the signal charges generated in the photoelectric conversion section can be swept out to the substrate with a low substrate bias as shown by the curve 36. Therefore, by arbitrarily selecting the time ratio for returning the substrate bias from curve 37 to curve 35 or 36 during the period when optical information is accumulated in the photoelectric conversion section, it is possible to provide an electronic shutter function with a low voltage.

FIG. 4 is a vertical cross-sectional view of a semiconductor chip showing a second embodiment of the present invention, FIG.
It corresponds to the figure.

The difference between FIG. 4 and FIG. 1 is that the main surface of the N-type region of the photoelectric conversion section 18 is covered with a P" layer 38 having a high concentration of P-type impurities, similar to the channel stop region 22, so that the photoelectric conversion section The capacitance increases, and a large amount of signal charge can be swept out to the substrate with a small substrate bias.

〔Effect of the invention〕

As explained above, the present invention forms an epitaxial layer having the same conductivity type as that of the substrate and having a low impurity concentration on the main surface of a semiconductor substrate, and forms a bonding epitaxial layer having a conductivity type opposite to that of the substrate on the main surface of the epitaxial layer. A well of opposite conductivity type consisting of a shallow first region and a deep second region is provided, a photoelectric conversion region is formed on the main surface of the first region, and a signal readout means for receiving charges from the photoelectric conversion region is provided in the second region. Therefore, during the period when optical information is being accumulated in the photoelectric conversion region, the first.
By changing the substrate bias applied between the second region and the substrate, a shutter function can be achieved with a low voltage.

In the present invention, an N-channel imaging device has been described, but a P-channel imaging device can also be implemented using the same idea. Also p-
It goes without saying that the present invention can be applied to other solid-state imaging devices that use n-junctions as photoelectric conversion regions.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a cell portion of a semiconductor chip of a solid-state imaging device showing a first embodiment of the present invention, FIG. 2 is an impurity concentration distribution diagram in the depth direction indicated by the broken line in FIG. 1, and FIG. is a potential distribution diagram corresponding to FIG. 2, FIG. 4 is a sectional view of a cell portion of a semiconductor chip showing a second embodiment of the present invention, and FIG. 5 is a block diagram showing a conventional interline charge transfer imaging device. FIG. 6 is a cross-sectional view of the semiconductor chip taken along the line AA' in FIG. 5, and FIG. 7 is a depthwise impurity concentration distribution diagram indicated by the broken line in FIG. 6. 15... N-type semiconductor substrate, 16... first region, 17
...Second region, 18...Photoelectric conversion region, 19...
Buried channel, 20... Insulating layer, 21... Transfer electrode, 22... Channel stop region, 23... Transfer gate region, 24... Metal layer, 25, 26.
27... Potential distribution curve, 28... Substrate voltage, two...
...Curve of potential distribution, 30...N-type epitaxial layer, 31-34...Curve of impurity concentration distribution, 35-37
...Potential distribution curve. Figure 1 Figure 2 Figure 5 M3 Figure 7 Concave

Claims (1)

[Claims] A shallow first region and a deep second region provided in the first conductivity type epitaxial layer of a semiconductor chip formed by forming a first conductivity type epitaxial layer with a low concentration on a first conductivity type semiconductor substrate. a photoelectric conversion region provided on the main surface of the first region;
What is claimed is: 1. A solid-state imaging device having a vertical overflow drain structure, comprising signal readout means provided on a main surface of a region and receiving charges from the photoelectric conversion region.