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JPS6216599B2 - - Google Patents

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Publication number
JPS6216599B2
JPS6216599B2 JP55130517A JP13051780A JPS6216599B2 JP S6216599 B2 JPS6216599 B2 JP S6216599B2 JP 55130517 A JP55130517 A JP 55130517A JP 13051780 A JP13051780 A JP 13051780A JP S6216599 B2 JPS6216599 B2 JP S6216599B2
Authority
JP
Japan
Prior art keywords
region
photoelectric conversion
shift register
vertical
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55130517A
Other languages
Japanese (ja)
Other versions
JPS5755672A (en
Inventor
Yasuo Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55130517A priority Critical patent/JPS5755672A/en
Priority to DE8181107482T priority patent/DE3168333D1/en
Priority to EP81107482A priority patent/EP0048480B1/en
Priority to US06/304,301 priority patent/US4527182A/en
Publication of JPS5755672A publication Critical patent/JPS5755672A/en
Publication of JPS6216599B2 publication Critical patent/JPS6216599B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/15Charge-coupled device [CCD] image sensors
    • H10F39/158Charge-coupled device [CCD] image sensors having arrangements for blooming suppression
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/18Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/186Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors having arrangements for blooming suppression

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 本発明は電荷転送装置を用いた撮像装置に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an imaging device using a charge transfer device.

電荷転送装置を用いた撮像装置はフレーム転送
方式、インターライン転送方式と呼ばれる方式が
開発されており、固体装置の特徴である小型、軽
量、低消費電力、高信頼性を柱に急速に発展して
いる。しかし撮像装置として電荷転送撮像装置の
利害得失を考えると、先に述べた固体装置の利点
の外、雑音、残像、焼き付き、等では現在使用さ
れている撮像管より優れているがブルーミング、
スミア現象(クロストーク)に大きな問題を残し
ている。
Imaging devices using charge transfer devices have been developed using methods called the frame transfer method and the interline transfer method, which are rapidly developing based on the characteristics of solid-state devices: small size, light weight, low power consumption, and high reliability. ing. However, when considering the advantages and disadvantages of charge transfer imaging devices as imaging devices, in addition to the advantages of solid-state devices mentioned above, they are superior to currently used image pickup tubes in terms of noise, afterimages, burn-in, etc., but blooming,
A major problem remains with the smear phenomenon (crosstalk).

従来のインターライン転送方式による電荷転送
撮像装置は第1図に示すように同一電荷転送電極
群で駆動する複数列の垂直シフトレジスタ10
と、各垂直シフトレジスタの一側に隣接し、且つ
互いに電気的に分離された光電変換部11と、垂
直シフトレジスタと光電変換部間の信号電荷転送
を制御するトランスフアゲート電極12と、各垂
直シフトレジスタの一端に電気的結合した電荷転
送水平シフトレジスタ13と、水平シフトレジス
タの一端に信号電荷を検出する装置14が設けら
れている。第2図aは第1図に示す撮像装置にお
ける−線上における断面を模式的に示したも
のである。半導体基板15の主面に絶縁層16を
介して垂直シフトレジスタの電荷転送電極17、
光電変換部から垂直シフトレジスタへの信号電荷
転送を制御するトランスフアゲート電極18、基
板半導体と異つた導電型層19(P−n接合)で
構成される光電変換部が形成されており、光電変
換部は隣接する垂直シフトレジスタと、例えば基
板不純物濃度より高い不純物層をもつチヤネルス
トツプ領域20によつて分離されている。また、
光電変換部以外は例えば金属層21で光遮蔽され
ている。
As shown in FIG. 1, a conventional charge transfer imaging device using an interline transfer method has multiple columns of vertical shift registers 10 driven by the same charge transfer electrode group.
, a photoelectric conversion section 11 adjacent to one side of each vertical shift register and electrically isolated from each other, a transfer gate electrode 12 for controlling signal charge transfer between the vertical shift register and the photoelectric conversion section, A charge transfer horizontal shift register 13 electrically coupled to one end of the shift register and a device 14 for detecting signal charges are provided at one end of the horizontal shift register. FIG. 2a schematically shows a cross section of the imaging device shown in FIG. 1 taken along the - line. A charge transfer electrode 17 of a vertical shift register is provided on the main surface of the semiconductor substrate 15 via an insulating layer 16,
A photoelectric conversion section is formed of a transfer gate electrode 18 that controls signal charge transfer from the photoelectric conversion section to the vertical shift register, and a layer 19 of a conductivity type different from the substrate semiconductor (P-n junction). The sections are separated from adjacent vertical shift registers by a channel stop region 20 having, for example, an impurity layer higher than the substrate impurity concentration. Also,
The parts other than the photoelectric conversion section are shielded from light by, for example, a metal layer 21.

このようなインターライン転送方式による撮像
装置は、光電変換部11で入射光量に応じて蓄積
した信号電荷を、例えばトランスフアゲート12
を介してそれぞれ対応する垂直シフトレジスタ1
0へ転送する。垂直シフトレジスタへ信号電荷を
転送した後、トランスフアゲートが閉じられ、光
電変換部11は次の周期の信号電荷を蓄積する。
一方、垂直シフトレジスタ10へ転送された信号
電荷は並列に垂直方向に転送し、各垂直シフトレ
ジスタの一水平ライン毎に、水平シフトレジスタ
13に転送される。水平シフトレジスタへ送られ
た電荷は次の垂直シフトレジスタから信号が転送
されて来る間に水平方向に信号電荷を転送し電荷
検出部14から信号として外部に取り出される。
An imaging device using such an interline transfer method transfers signal charges accumulated in the photoelectric conversion unit 11 according to the amount of incident light to the transfer gate 12, for example.
through the corresponding vertical shift register 1
Transfer to 0. After transferring the signal charge to the vertical shift register, the transfer gate is closed, and the photoelectric conversion unit 11 accumulates the signal charge for the next cycle.
On the other hand, the signal charges transferred to the vertical shift register 10 are transferred in parallel in the vertical direction, and transferred to the horizontal shift register 13 for each horizontal line of each vertical shift register. The charge sent to the horizontal shift register is transferred in the horizontal direction while a signal is transferred from the next vertical shift register, and is taken out as a signal from the charge detection section 14 to the outside.

この様な従来の電荷転送撮像装置では、第2図
bの電位分布図で示すように光電変換部11以外
のチヤネルストツプ領域20、またはトランスフ
アゲート電極との境界に照射された光22は第2
図bに示すように一部隣接する垂直シフトレジス
タへ流れ込む。
In such a conventional charge transfer imaging device, as shown in the potential distribution diagram of FIG.
As shown in FIG. b, a portion flows into the adjacent vertical shift register.

光電変換部の電位井戸23外で信号電荷を発生
した電荷の一部は隣接する垂直シフトレジスタ2
4または光電変換部に対応する垂直シフトレジス
タ25に流れ込む。また光電変換部の主面に対し
て角度をもつて入射する光は半導体基板表面で反
射し絶縁層、多結晶シリコン等で形成された電極
層の中を多重反射しながら第2図aで示す断面の
横方向に伝播してゆき、隣接する垂直シフトレジ
スタ、及び各光電変換部に対応する垂直シフトレ
ジスタ内で吸収され電荷群を発生させる。
A portion of the signal charges generated outside the potential well 23 of the photoelectric conversion section is transferred to the adjacent vertical shift register 2.
4 or the vertical shift register 25 corresponding to the photoelectric conversion section. In addition, the light incident at an angle to the main surface of the photoelectric conversion section is reflected on the surface of the semiconductor substrate and is reflected multiple times through the insulating layer and the electrode layer formed of polycrystalline silicon, etc., as shown in Figure 2a. The charges propagate in the lateral direction of the cross section and are absorbed in the adjacent vertical shift registers and the vertical shift registers corresponding to each photoelectric conversion unit, generating a group of charges.

この様な現象が、垂直シフトレジスタで信号電
荷を転送している期間に起ると、各垂直ラインに
照射されている光量に応じて各垂直シフトレジス
タに漏れる電荷の量が異るため、各垂直ラインの
平均光量差が、暗出力レベルの差となつて現わ
れ、一般にスミアと呼ばれる現象がみられる。も
う一つの問題として第2図cに示す電位分布図の
ように光電変換部に強い光が入射し光電変換部で
蓄えられる最大電荷量以上の電荷が発生した場
合、その電荷は光電変換部の電位井戸23からあ
ふれ出し隣接する垂直シフトレジスタの電位井戸
24または光電変換部に対応する垂直シフトレジ
スタの電位井戸25に流れ込む。この現象は一般
にブルーミング現象と呼ばれ、撮像画像では白い
線状のパターンになる。
If such a phenomenon occurs during the period when signal charges are being transferred in the vertical shift register, the amount of charge leaking to each vertical shift register will differ depending on the amount of light irradiated to each vertical line. The difference in the average light intensity of the vertical lines appears as a difference in the dark output level, and a phenomenon generally called smear is observed. Another problem is that, as shown in the potential distribution diagram shown in Figure 2c, if strong light is incident on the photoelectric conversion unit and a charge greater than the maximum amount of charge that can be stored in the photoelectric conversion unit is generated, that charge will be transferred to the photoelectric conversion unit. It overflows from the potential well 23 and flows into the potential well 24 of the adjacent vertical shift register or the potential well 25 of the vertical shift register corresponding to the photoelectric conversion section. This phenomenon is generally called a blooming phenomenon, and appears as a white linear pattern in the captured image.

本発明は上記の欠点を無くした新しい構造の固
体撮像装置とその駆動方法を提供するものであ
る。
The present invention provides a solid-state imaging device with a new structure that eliminates the above-mentioned drawbacks and a method for driving the same.

本発明によれば半導体基板の主面に、前記基板
と反対の導電型を形成してなる接合領域で、前記
接合深さが浅い第1の領域と、前記接合深さが深
い第2の領域を設け、前記第1の領域の主面に光
電変換素子群を形成し、前記第2の領域の主面に
前記光電変換素子群からの信号を読み出す装置を
形成してなることを特徴とする固体撮像装置と、
上記の固体撮像装置で、少くとも前記第1の領域
が完全に空乏化するのに必要な逆バイアス電圧
を、前記第1の領域及び第2の領域と前記半導体
基板間に印加することを特徴とする固体撮像装置
の駆動方法が得られる。
According to the present invention, the junction region is formed on the main surface of a semiconductor substrate and has a conductivity type opposite to that of the substrate, the first region having the shallow junction depth and the second region having the deep junction depth. , a group of photoelectric conversion elements is formed on the main surface of the first region, and a device for reading signals from the group of photoelectric conversion elements is formed on the main surface of the second region. a solid-state imaging device;
The solid-state imaging device described above is characterized in that a reverse bias voltage necessary for at least the first region to be completely depleted is applied between the first region, the second region, and the semiconductor substrate. A method for driving a solid-state imaging device is obtained.

次に本発明の実施例について図面を用いて説明
する。以後本発明の実施例については説明を簡単
にするためNチヤネルの半導体装置について述べ
ることにする。
Next, embodiments of the present invention will be described using the drawings. Hereinafter, in the embodiments of the present invention, an N-channel semiconductor device will be described to simplify the explanation.

第3図は本発明の一実施例を示すもので、従来
例で説明した第2図aと同様に、第1図に示す電
荷転送撮像装置の−線上の断面を模式的に示
したものである。第3図において第2図と同一機
能をもつ領域は同一記号で示してある。この第3
図に示す実施例と第2図aに示した従来例との違
いは、基板半導体26とP−n接合を形成し且
つ、接合深さが異る二つのP型領域27,28が
形成されていることにある。N型半導体26上に
接合深さが異るP型領域27,28を形成する方
法の一例を、第4図を用いて説明する。まず基板
半導体26上に通常の写真食刻技術を用い領域2
8に該当する部分にイオン注入法、または熱拡散
法によつてP型不純物を拡散する。その後第4図
aのように不活性ガス中あるいは濃度の薄い酸素
分囲気で不純物の再分布拡散を行う。次にP型領
域28を形成したと同様に写真食刻法により領域
27にP型不純物を選択拡散し、その後再分布拡
散を行うことで、P型領域27,28に必要な接
合深さ及び不純物濃度を得ることができる。
FIG. 3 shows an embodiment of the present invention, and similarly to FIG. 2a described in the conventional example, it schematically shows a cross section of the charge transfer imaging device shown in FIG. 1 on the - line. be. In FIG. 3, areas having the same functions as those in FIG. 2 are indicated by the same symbols. This third
The difference between the embodiment shown in the figure and the conventional example shown in FIG. It is in the fact that An example of a method for forming P-type regions 27 and 28 having different junction depths on an N-type semiconductor 26 will be described with reference to FIG. 4. First, a region 2 is formed on the substrate semiconductor 26 using ordinary photolithography technology.
P-type impurities are diffused into the portion corresponding to No. 8 by ion implantation or thermal diffusion. Thereafter, as shown in FIG. 4a, impurities are redistributed and diffused in an inert gas or a thin oxygen atmosphere. Next, in the same way as forming the P-type regions 28, P-type impurities are selectively diffused into the region 27 by photolithography, and then redistribution diffusion is performed to achieve the required junction depth and Impurity concentration can be obtained.

領域27,28を形成する他の方法の一例を第
5図を用いて説明する。最初に第5図aでN型基
板半導体26上の領域27に該当する部分に写真
食刻法により基板不純物と同一型不純物の高濃度
領域29を形成する。その後第5図bに示すよう
に基板半導体26と反対の導電型をもつP型半導
体層30を例えば気相成長法によつて形成する。
このような状態で高温処理を行うと高濃度埋込み
層29から気相成長したP型層30へ不純物拡散
が行なわれ、第5図cに図示したように接合深さ
が異るP型層領域27,28を得ることができ
る。
An example of another method for forming the regions 27 and 28 will be explained using FIG. 5. First, as shown in FIG. 5A, a high concentration region 29 of the same type of impurity as the substrate impurity is formed in a portion corresponding to region 27 on the N type substrate semiconductor 26 by photolithography. Thereafter, as shown in FIG. 5b, a P-type semiconductor layer 30 having a conductivity type opposite to that of the substrate semiconductor 26 is formed by, for example, vapor phase growth.
When high-temperature treatment is performed in such a state, impurities are diffused from the heavily doped buried layer 29 to the vapor-grown P-type layer 30, resulting in P-type layer regions with different junction depths as shown in FIG. 5c. 27 and 28 can be obtained.

次に本発明の実施例の動作について説明する。
撮像装置としての基本的な動作は、第1図で示し
た従来例の撮像装置と同様であるため、第3図に
示した本発明の重要な要素であるP型領域27,
28の動作について説明する。
Next, the operation of the embodiment of the present invention will be explained.
Since the basic operation as an imaging device is the same as that of the conventional imaging device shown in FIG. 1, the P-type region 27, which is an important element of the present invention shown in FIG.
The operation of 28 will be explained.

第6図は第3図に示す光電変換部の−線
上、すなわち光電変換部の深さ方向の電位分布を
示している。第6図の横軸は深さ方向の距離、縦
軸は電位を表わしている。今第3図に示すチヤネ
ルストツプ領域20の電位を基準電位、(この場
合0ボルト)とする。N型光電変換部19はトラ
ンスフアゲート18の電位をVTG、トランスフア
ゲートの閾値電圧をVTとするとVTG−VTの電位
でセツトされる。またP型領域27と基板26に
印加する逆バイアス電圧を曲線31で示す低い電
圧から、より高い逆バイアス電圧にすると曲線3
2のようにP型領域27は完全に空乏化する。光
電変換領域19に光が照射され信号電荷が蓄積す
ると、光電変換領域19の電位は曲線32から曲
線33のように小さくなつてゆき最終的には曲線
34のように光電変換部19とP型領域27の接
合は順方向となり、これ以上光電変換部19で発
生した電荷はP型領域27を介して基板半導体2
6へ流れ込む。すなわち第3図で示すトランスフ
アゲート18直下、チヤネルストツプ領域20直
下、および図示していないが光電変換部19を囲
む全ての領域の表面電位より光電変換部19とP
型領域27の接合電位が高くなるように基板半導
体とP型領域27に逆バイアス電圧を印加するこ
とにより、光電変換部19で発生する過剰電荷は
完全に基板半導体へ掃き出すことができる。
FIG. 6 shows the potential distribution on the - line of the photoelectric conversion section shown in FIG. 3, that is, in the depth direction of the photoelectric conversion section. In FIG. 6, the horizontal axis represents distance in the depth direction, and the vertical axis represents potential. Let us now assume that the potential of the channel stop region 20 shown in FIG. 3 is a reference potential (in this case, 0 volts). The N-type photoelectric conversion section 19 is set at a potential of V TG -V T where the potential of the transfer gate 18 is V TG and the threshold voltage of the transfer gate is V T . Further, when the reverse bias voltage applied to the P-type region 27 and the substrate 26 is changed from a low voltage shown by curve 31 to a higher reverse bias voltage, curve 3
As shown in FIG. 2, the P type region 27 is completely depleted. When the photoelectric conversion region 19 is irradiated with light and signal charges are accumulated, the potential of the photoelectric conversion region 19 decreases as shown by a curve 32 to a curve 33, and finally, as shown in a curve 34, the potential of the photoelectric conversion region 19 and the P type The junction of the region 27 is in the forward direction, and any more charges generated in the photoelectric conversion section 19 are transferred to the substrate semiconductor 2 via the P-type region 27.
Flows into 6. In other words, the photoelectric conversion section 19 and P
By applying a reverse bias voltage to the substrate semiconductor and the P-type region 27 so that the junction potential of the type region 27 becomes high, excess charges generated in the photoelectric conversion section 19 can be completely swept out to the substrate semiconductor.

この構造及び動作によつて従来の欠点であつた
ブルーミング現象を完全に抑制することができ
る。一方、光電変換部でブルーミング抑制を行つ
ている状態における垂直電荷転送領域すなわち第
3図に示す−線上の電位分布を第7図に示し
た。この垂直シフトレジスタ10は埋込みチヤネ
ルで構成されている場合について記述してある。
With this structure and operation, it is possible to completely suppress the blooming phenomenon, which has been a drawback of the prior art. On the other hand, FIG. 7 shows the potential distribution in the vertical charge transfer region, that is, on the - line shown in FIG. 3, in a state where blooming is suppressed in the photoelectric conversion section. The vertical shift register 10 is described as being configured with embedded channels.

曲線35は垂直電荷転送電極17に印加されて
いるパルスがハイレベルで垂直レジスタには信号
電荷が存在しない状態での電位分布である。曲線
35で示すように光電変換部でブルーミング抑制
を行う動作条件では垂直シフトレジスタ10直下
のP型領域28は完全に空乏化しないような厚さ
に形成することが望ましく、空乏化しても、埋込
みチヤネル10とP型領域28、及びP型領域2
8と基板半導体26のそれぞれが順方向にならな
いようなP型領域28の厚さ及び不純物濃度をも
たなければならない。
A curve 35 is a potential distribution when the pulse applied to the vertical charge transfer electrode 17 is at a high level and there is no signal charge in the vertical register. As shown by curve 35, under the operating conditions in which blooming is suppressed in the photoelectric conversion section, it is desirable to form the P-type region 28 directly under the vertical shift register 10 to a thickness that does not completely deplete it. Channel 10, P-type region 28, and P-type region 2
The thickness and impurity concentration of the P-type region 28 must be such that the P-type region 8 and the substrate semiconductor 26 are not in the forward direction.

この理由について図面を用いて説明する。第1
1図は浅いP型領域27上に埋込チヤネルからな
る垂直シフトレジスタ10を形成したと仮定した
場合について、その深さの方向の電位分布を示し
た。また図中には比較のため光電変換領域19が
セツトされた電位曲線32を同時に示してある。
The reason for this will be explained using the drawings. 1st
FIG. 1 shows the potential distribution in the depth direction assuming that the vertical shift register 10 consisting of a buried channel is formed on the shallow P-type region 27. Also shown in the figure for comparison is a potential curve 32 on which the photoelectric conversion region 19 is set.

曲線57は転送電極17のパルスがハイレベル
で垂直シフトレジスタには信号が存在していない
状態での電位分布である。またP型領域27と基
板26には第6図の曲線32と同一の逆バイアス
が印加されている。埋込チヤネル垂直シフトレジ
スタ10の電位57は垂直転送電極17に印加さ
れるハイレベル(通常トランスフアゲート電極に
印加される電圧VTGより大きい電圧が印加され
る)より高くなる。またこの垂直シフトレジスタ
10の電位57は第6図に示した光電変換領域1
9がセツトされる電位(VTG−VT)より高い電
位になつている。
A curve 57 is a potential distribution when the pulse of the transfer electrode 17 is at a high level and no signal exists in the vertical shift register. Further, the same reverse bias as the curve 32 in FIG. 6 is applied to the P-type region 27 and the substrate 26. The potential 57 of the buried channel vertical shift register 10 is higher than the high level applied to the vertical transfer electrode 17 (usually a voltage greater than the voltage V TG applied to the transfer gate electrode). Further, the potential 57 of this vertical shift register 10 is set to the photoelectric conversion area 1 shown in FIG.
9 is set at a potential higher than the potential (V TG -V T ).

埋込チヤネル垂直シフトレジスタ10とP型領
域27の逆バイアス電圧、およびP型領域27と
N型基板26の逆バイアス電圧によつてP型領域
27の電位は高くなり、曲線57のように基板2
6とP型領域27が順方向になる場合もある。こ
の場合、基板半導体26から垂直シフトレジスタ
10へ矢印58のように電子が流れ込む。このよ
うな理由により、光電変換部19以外は基板から
の電子の注入が起らない不純物濃度と接合の深さ
をもつP型領域28に形成しなければならない。
The potential of the P-type region 27 becomes high due to the reverse bias voltage of the buried channel vertical shift register 10 and the P-type region 27, and the reverse bias voltage of the P-type region 27 and the N-type substrate 26, and the potential of the P-type region 27 increases as shown by a curve 57. 2
6 and the P-type region 27 may be in the forward direction. In this case, electrons flow from the substrate semiconductor 26 to the vertical shift register 10 as indicated by an arrow 58. For this reason, the parts other than the photoelectric conversion part 19 must be formed in the P-type region 28 having an impurity concentration and junction depth that prevent injection of electrons from the substrate.

第8図は、第3図における水平方向断面V−V
線上の電位分布を示したものである。光の開口部
(光電変換部)11直下では曲線36で示される
ように電位が高くなつているため、開口部の周辺
で発生した電荷は全て光電変換部へ流れ込む、ま
た図示していないが第3図のP型領域は完全に空
乏化しておりこのP型領域27から対応する垂直
レジスタあるいは隣接する垂直シフトレジスタへ
は深さ方向のどの位置においても曲線36で示す
ような障壁があるため、拡散による電荷の漏れ込
みはない。このため第2図bで説明したいわゆる
スミア現象はほとんど発生しない。
Figure 8 is a horizontal cross section V-V in Figure 3.
This shows the potential distribution on the line. Directly below the light aperture (photoelectric conversion section) 11, the potential is high as shown by the curve 36, so all the charges generated around the aperture flow into the photoelectric conversion section. The P-type region in FIG. 3 is completely depleted, and there is a barrier as shown by the curve 36 at any position in the depth direction from this P-type region 27 to the corresponding vertical register or adjacent vertical shift register. There is no charge leakage due to diffusion. Therefore, the so-called smear phenomenon described in FIG. 2b hardly occurs.

以上述べてきたように第3図に示した本実施例
はブルーミング、スミア現象を大幅に低減でき
る。
As described above, the present embodiment shown in FIG. 3 can significantly reduce blooming and smear phenomena.

第9,第10図は本発明の他の実施例を説明す
るためのもので、37は基板とP−n接合を形成
してなる光電変換素子、38は垂直読み出し用の
スイツチでMOSトランジスタで形成されてい
る。垂直スイツチMOSトランジスタ38のゲー
トは、一行毎垂直遅延パルスを発生する垂直シフ
トレジスタのタツプ41に共通接続されている。
また各垂直スイツチMOSトランジスタ38のド
レインは垂直方向に配列された素子が垂直信号読
み出し線39で共通接続されている。42は水平
切換MOSトランジスタで、各ゲートは水平シフ
トレジスタ43の各タツプ44に接続される。
9 and 10 are for explaining other embodiments of the present invention, 37 is a photoelectric conversion element formed by forming a P-n junction with the substrate, and 38 is a vertical readout switch which is a MOS transistor. It is formed. The gates of the vertical switch MOS transistors 38 are commonly connected to a tap 41 of a vertical shift register that generates vertical delay pulses for each row.
Further, the drains of each vertical switch MOS transistor 38 are commonly connected to the elements arranged in the vertical direction by a vertical signal readout line 39. 42 is a horizontal switching MOS transistor, each gate of which is connected to each tap 44 of the horizontal shift register 43.

第9図に示す撮像装置は通称MOS型センサと
呼ばれる撮像装置でその動作は、光電変換素子群
37で蓄えられた光情報信号は、垂直シフトレジ
スタの任意のタツプ41がハイレベルになるとこ
のタツプ41に接続される行の垂直スイツチ
MOSトランジスタ38が同時に導通状態となり
信号電荷はそれぞれ対応する垂直読み出し線39
に読み出される。この信号電荷は、水平シフトレ
ジスタ43からの各タツプ出力44により水平ス
イツチMOSトランジスタを介して順次出力ライ
ン45へ読み出される。このように垂直シフトレ
ジスタの任意のタツプ41に対応する光電変換素
子群37の信号がすべて読み出されたら、垂直シ
フトレジスタ40は1段進んで次のタツプがハイ
レベルになり、同時にそのタツプに対応する行の
光電変換素子群37の信号電荷が対応する垂直読
み出し線39に読み出される。以下同様な動作を
くり返すことにより、第9図に示す光電変換素子
37に蓄えられた信号電荷を一行毎順次読み出す
ことができる。しかし垂直読み出し線39は垂直
方向に配列された全ての光電変換素子に垂直スイ
ツチMOSトランジスタ38を介して接続されて
いるため、垂直ラインの一部に強い光が照射され
その素子がブルーミングを起すと過剰電荷は垂直
読み出し線39に漏れ込む、また同様に基板内部
で発生した電荷も拡散によつて垂直読み出し線3
9に漏れ込む。これらの現象は第1図で説明した
電荷転送型撮像装置と同様再生画像を劣化させ
る。第10図は第9図に示す撮像装置の一素子を
構成する領域46の断面模式図を示すものであ
る。第9図に対応する光電変換素子37はN型領
域47で示される。同様に48は垂直スイツチ
MOSトランジスタのゲート、50はドレインで
垂直読み出し線51の金属に接続されている。ゲ
ート48の端子49は図示してないが垂直シフト
レジスタ40のタツプ41に接続される。55は
チヤネルストツプ領域である。
The imaging device shown in FIG. 9 is commonly called a MOS type sensor, and its operation is such that when an arbitrary tap 41 of the vertical shift register becomes high level, the optical information signal stored in the photoelectric conversion element group 37 is transferred to this tap. Vertical switch in the row connected to 41
The MOS transistors 38 become conductive at the same time, and the signal charges are transferred to the corresponding vertical readout lines 39.
is read out. This signal charge is sequentially read out to an output line 45 by each tap output 44 from the horizontal shift register 43 via a horizontal switch MOS transistor. When all the signals of the photoelectric conversion element group 37 corresponding to an arbitrary tap 41 of the vertical shift register are read out in this way, the vertical shift register 40 advances by one stage and the next tap becomes high level, and at the same time The signal charges of the photoelectric conversion element group 37 in the corresponding row are read out to the corresponding vertical readout line 39. By repeating the same operation thereafter, the signal charges stored in the photoelectric conversion element 37 shown in FIG. 9 can be sequentially read out row by row. However, since the vertical readout line 39 is connected to all the photoelectric conversion elements arranged in the vertical direction via the vertical switch MOS transistor 38, if a part of the vertical line is irradiated with strong light and the element blooms, Excess charge leaks into the vertical readout line 39, and similarly, charge generated inside the substrate also diffuses into the vertical readout line 39.
It leaks into 9. These phenomena deteriorate the reproduced image as in the charge transfer type imaging device described in FIG. FIG. 10 shows a schematic cross-sectional view of a region 46 constituting one element of the imaging device shown in FIG. The photoelectric conversion element 37 corresponding to FIG. 9 is shown as an N-type region 47. Similarly, 48 is a vertical switch
The gate 50 of the MOS transistor is connected to the metal of the vertical readout line 51 at the drain. A terminal 49 of the gate 48 is connected to a tap 41 of the vertical shift register 40, although not shown. 55 is a channel stop area.

光電変換領域47直下は基板半導体52と反対
の導電型をもち接合の浅い領域53からなり、ま
た垂直読み出し線51に接続されるドレイン50
直下は深い接合をもつ領域54で構成されてい
る。この様な構造で基板半導体と領域53,54
に逆バイアス電圧を印加することにより、第3図
の実施例で説明したと同様な効果により光電変換
部47で蓄えられる過剰電荷はすべて基板半導体
52に掃き出すことが出来る。しかも領域54の
不純物濃度、及び接合深さを制御することにより
垂直読み出し線51に接続されるドレイン50
は、基板半導体52の影響を全く受けないように
することができる。
Immediately below the photoelectric conversion region 47 is a shallow junction region 53 having a conductivity type opposite to that of the substrate semiconductor 52, and a drain 50 connected to the vertical readout line 51.
Immediately below is a region 54 with deep junctions. With this structure, the substrate semiconductor and regions 53 and 54
By applying a reverse bias voltage to the photoelectric converter 47, all the excess charge stored in the photoelectric converter 47 can be swept out to the substrate semiconductor 52 by the same effect as explained in the embodiment of FIG. Furthermore, by controlling the impurity concentration of the region 54 and the junction depth, the drain 50 can be connected to the vertical readout line 51.
can be made completely unaffected by the substrate semiconductor 52.

以上本発明の実施例についてその構造と駆動法
について述べて来たが、感光素子と読み出し装置
が対になつて構成される固体撮像装置には全て適
用されるであろう。また第3図に示す実施例での
光電変換部19はMOS構造で形成される素子で
も良い。
Although the structure and driving method of the embodiments of the present invention have been described above, the present invention may be applied to any solid-state imaging device in which a photosensitive element and a readout device are configured as a pair. Further, the photoelectric conversion section 19 in the embodiment shown in FIG. 3 may be an element formed with a MOS structure.

また実施例ではNチヤネル型半導体装置につい
て説明したが各領域の導電型を反対にすることで
Pチヤネル半導体装置に適用できることは言うま
でもない。
Furthermore, although the embodiments have been described with reference to an N-channel semiconductor device, it goes without saying that the present invention can be applied to a P-channel semiconductor device by reversing the conductivity type of each region.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電荷転送装置を用いた撮像装置
の平面図、第2図は第1図に示す−線上の断
面模式図、およびその直下の電位分布図を示して
いる。第3図は本発明の一実施例を示す装置の断
面図で、第4図、第5図は本発明の実施例を構成
するための製作方法の一例を説明するための図で
ある。第6図、第7図、第8図は第3図に示す
−、−、−線上の電位分布を示してい
る。第9図、第10図は本発明の他の実施例を示
す撮像装置の構成図及び断面模式図を示してい
る。第11図は浅いP型領域27上に埋込チヤネ
ルからなる垂直シフトレジスタを形成したと仮定
した場合の深さ方向の電位分布を示す図である。 10は垂直シフトレジスタ、11,37は光電
変換素子、27,53は基板と反対の導電型をも
ち接合が浅い領域、28,54は基板と反対の導
電型をもち接合が深い領域を示す。
FIG. 1 is a plan view of an imaging device using a conventional charge transfer device, and FIG. 2 is a schematic cross-sectional view on the - line shown in FIG. 1, and a potential distribution diagram immediately below the cross-sectional view. FIG. 3 is a sectional view of an apparatus showing an embodiment of the present invention, and FIGS. 4 and 5 are diagrams for explaining an example of a manufacturing method for constructing the embodiment of the present invention. FIGS. 6, 7, and 8 show potential distributions on the -, -, and - lines shown in FIG. 3. FIG. 9 and FIG. 10 show a configuration diagram and a schematic cross-sectional view of an imaging device showing another embodiment of the present invention. FIG. 11 is a diagram showing the potential distribution in the depth direction assuming that a vertical shift register consisting of a buried channel is formed on the shallow P-type region 27. 10 is a vertical shift register; 11 and 37 are photoelectric conversion elements; 27 and 53 are regions with a conductivity type opposite to that of the substrate and a shallow junction; and 28 and 54 are regions with a conductivity type opposite to that of the substrate and a deep junction.

Claims (1)

【特許請求の範囲】 1 半導体基板の主面に、前記基板と反対の導電
型を形成してなる接合領域で、前記接合深さが浅
い第1の領域と、前記接合深さが深い第2の領域
を設け、前記第1の領域の主面に光電変換素子群
を形成し、前記第2の領域の主面に前記光電変換
素子群からの信号を読み出す装置を形成してなる
ことを特徴とする固体撮像装置。 2 半導体基板の主面に、前記基板と反対の導電
型を形成してなる接合領域で、前記接合深さが浅
い第1の領域と、前記接合深さが深い第2の領域
を設け、前記第1の領域の主面に光電変換素子群
を形成し、前記第2の領域の主面に前記光電変換
素子群からの信号を読み出す装置を形成してなる
固体撮像装置において、少くとも前記第1の領域
が完全に空乏化するに必要な、逆バイアス電圧を
前記第1の領域及び第2の領域と前記半導体基板
間に印加することを特徴とする固体撮像装置の駆
動方法。
[Scope of Claims] 1. A junction region formed on the main surface of a semiconductor substrate and having a conductivity type opposite to that of the substrate, including a first region with a shallow junction depth and a second region with a deep junction depth. A region is provided, a group of photoelectric conversion elements is formed on the main surface of the first region, and a device for reading signals from the group of photoelectric conversion elements is formed on the main surface of the second region. A solid-state imaging device. 2. A first region having a shallow junction depth and a second region having a deep junction depth are provided on a main surface of a semiconductor substrate, the junction region having a conductivity type opposite to that of the substrate, and the second region having a shallow junction depth. In a solid-state imaging device, a group of photoelectric conversion elements is formed on the main surface of the first region, and a device for reading out signals from the group of photoelectric conversion elements is formed on the main surface of the second region. 1. A method for driving a solid-state imaging device, comprising: applying a reverse bias voltage necessary to completely deplete one region between the first region and the second region and the semiconductor substrate.
JP55130517A 1980-09-19 1980-09-19 Solid-state image pickup device and its driving method Granted JPS5755672A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP55130517A JPS5755672A (en) 1980-09-19 1980-09-19 Solid-state image pickup device and its driving method
DE8181107482T DE3168333D1 (en) 1980-09-19 1981-09-21 Semiconductor photoelectric converter
EP81107482A EP0048480B1 (en) 1980-09-19 1981-09-21 Semiconductor photoelectric converter
US06/304,301 US4527182A (en) 1980-09-19 1981-09-21 Semiconductor photoelectric converter making excessive charges flow vertically

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55130517A JPS5755672A (en) 1980-09-19 1980-09-19 Solid-state image pickup device and its driving method

Publications (2)

Publication Number Publication Date
JPS5755672A JPS5755672A (en) 1982-04-02
JPS6216599B2 true JPS6216599B2 (en) 1987-04-13

Family

ID=15036179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55130517A Granted JPS5755672A (en) 1980-09-19 1980-09-19 Solid-state image pickup device and its driving method

Country Status (1)

Country Link
JP (1) JPS5755672A (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589361A (en) * 1981-07-08 1983-01-19 Hitachi Ltd Solid state image pickup element
JPS58187082A (en) * 1982-04-26 1983-11-01 Matsushita Electric Ind Co Ltd Driving method of solid-state imaging device
JPS5965470A (en) * 1982-10-05 1984-04-13 Nec Corp Charge coupled device output structure
JPS607766A (en) * 1983-06-27 1985-01-16 Sony Corp Manufacturing method of solid-state image sensor
JPS6020687A (en) * 1983-07-15 1985-02-01 Nippon Kogaku Kk <Nikon> electronic still camera
JPS60169165A (en) * 1984-02-10 1985-09-02 Hitachi Ltd solid-state image sensor
JPH0624239B2 (en) * 1984-02-15 1994-03-30 ソニー株式会社 Vertical overflow image sensor
JPH0680812B2 (en) * 1985-03-29 1994-10-12 松下電子工業株式会社 Solid-state imaging device
JPS61121580A (en) * 1984-11-16 1986-06-09 Matsushita Electronics Corp Solid-state image pick-up device
JPS61176150A (en) * 1985-01-31 1986-08-07 Toshiba Corp Solid-state image pickup device
JPS61198110U (en) * 1985-06-03 1986-12-11
JPS61281790A (en) * 1985-06-07 1986-12-12 Hitachi Ltd Solid-state image pickup device
JPS62156870A (en) * 1985-12-28 1987-07-11 Matsushita Electronics Corp Manufacture of solid-state image pickup device
JPH07120774B2 (en) * 1986-12-05 1995-12-20 松下電子工業株式会社 Solid-state imaging device
KR930000914B1 (en) * 1990-01-29 1993-02-11 금성일렉트론 주식회사 Method for suppressing OFD of photodiode in CCD image sensor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724576A (en) * 1980-07-22 1982-02-09 Toshiba Corp Solid state image pick up device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724576A (en) * 1980-07-22 1982-02-09 Toshiba Corp Solid state image pick up device

Also Published As

Publication number Publication date
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