JPH02119265A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a device whose reliability has been enhanced by reducing an unstable circuit operation caused by a side-gate effect by a method wherein a ring-shaped element isolation region isolated from an adjacent semiconductor element is formed in a region surrounding a semiconductor element region. CONSTITUTION:In a compound semiconductor device having a semiconductor element formed on a semi-insulating compound semiconductor substrate 1, a ring-shaped element isolation region 7 isolated from an adjacent semiconductor element is formed in a region surrounding a periphery of a semiconductor element region. For example, a MESFET is constituted in such a way that an active layer 2, a gate electrode 3, a high-concentration impurity diffusion region 4, a source electrode 5 and a drain electrode 6 are formed on a semi-insulating GaAs substrate 1; boron ions are implanted selectively into a region surrounding an outer periphery of the high-concentration impurity diffusion region 4 isolated from an adjacent semiconductor element, where an acceleration energy is 100keV and a dosage is 1X10<14>cm<-2>; a ring-shaped element isolation region 7 is formed. Instead of the ion of boron, protons may be implanted, an acceleration energy being 150keV and a dosage being 1X10<15>cm<-2>.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a compound semiconductor device.

[Conventional technology]

GaAs Schottky barrier junction gate field effect transistor (hereinafter referred to as G
aAsMESFET) has recently begun to be applied to integrated circuits. In this case, a plurality of semiconductor elements are formed on the same substrate, but each element needs to be electrically insulated.

FIG. 4 is a cross-sectional view of a semiconductor chip showing an example of a conventional compound semiconductor device.

As shown in the figure, Si is deposited on the surface of a semi-insulating GaAs substrate 1.
After selectively implanting ions, annealing is performed at 800° C. to form the active layer 2.

Next, a tungsten silicide layer is deposited on the surface including the active layer 2 and selectively etched to form a gate electrode 3 having a Schottky junction with the active layer 2. next,
Using the gate electrode 3 as a mask, Si ions are selectively implanted, and annealing is performed again at 800°C to form the gate electrode 3.
6th order to form the high concentration impurity diffusion region 4 in accordance with
Source electrode 5 having an ohmic contact made of Au-Ge-Ni alloy on high concentration impurity diffusion region 4
and a drain electrode 6 are selectively formed to constitute a MESFET.

[Problem to be solved by the invention]

In the conventional compound semiconductor device described above, the drain current of the MESFET is affected by the negative potential (hereinafter referred to as side gate voltage) applied to other adjacent MESFETs (hereinafter referred to as side gate effect), and the operation of the integrated circuit is affected. There is a problem with instability.

An object of the present invention is to provide a compound semiconductor device with improved reliability by reducing unstable circuit operation due to the above-mentioned side gate effect.

[Means to solve the problem]

The compound semiconductor device of the present invention is a compound semiconductor device having a semiconductor element formed on a semi-insulating compound semiconductor substrate, in which an annular element isolation device is provided in a region surrounding the semiconductor element region to be isolated from an adjacent semiconductor element. It is composed of areas.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line X-X' of a semiconductor chip for explaining a first embodiment of the present invention.

As shown in FIGS. 1(a) and 1(b), a MESFET is constructed using the same steps as in the conventional example, and boron ions are injected at 100 keV into a region surrounding the outer periphery of the high-concentration impurity diffusion region 4, isolated from adjacent semiconductor elements. acceleration energy and l X I
Boron ions are selectively implanted at a dose of Q14C11-2 to form an annular element isolation region 7.

Here, instead of boron ions, protons are accelerated with an energy of 1
50 keV and a dose of I x 10"cm-2, or oxygen ions were implanted with an acceleration energy of 70 keV,
I implanted it at a dose of 1 x 1013 CI11-2 and it worked fine.

FIG. 2 is a characteristic diagram showing drain current characteristics and leakage current characteristics with respect to side gate voltage of the present invention in comparison with a conventional example.

As shown in the figure, the train current characteristic A with respect to the side gate voltage (voltage applied to the source electrode of the adjacent FET) maintains a constant value up to a lower voltage than the characteristic B of the conventional example, and The result was that the leakage current characteristic C between the two elements was also suppressed to a lower level than that of the conventional example, indicating that the present invention reduces the influence from adjacent elements.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

As shown in the figure, the MESFET is manufactured using the same process as the conventional example.
After forming the gate electrode 3. An insulating film 8 such as 5i02 is deposited on the surface including the source electrode 5 and the drain electrode 6,
A photoresist film 9 is applied and patterned on the insulating film 8 to form an opening 10 surrounding the high concentration impurity diffusion region 4. Next, using the photoresist film 9 as a mask, boron ions are applied through the insulating film 8 in the opening 10. ions are implanted to form element isolation regions 7. At this time, since the highest concentration region of the impurity concentration distribution of the element isolation region 7 can be formed near the surface of the semi-insulating GaAs substrate 1, the element isolation effect can be enhanced.

〔Effect of the invention〕

As explained above, the present invention provides a compound semiconductor device with reduced side gate effects by ion-implanting impurities into the outer periphery of a semiconductor element region provided on a semi-insulating semiconductor substrate to form an element isolation region. This has the effect of suppressing instability of circuit operation.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view taken along line X-X' of a semiconductor chip for explaining the first embodiment of the present invention;
FIG. 2 is a characteristic diagram showing the drain current characteristics and leakage current characteristics with respect to the side gate voltage of the present invention in comparison with a conventional example, and FIG. 3 is a cross section of a semiconductor chip for explaining the second embodiment of the present invention. 4 are cross-sectional views of a semiconductor chip showing an example of a conventional compound semiconductor device. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate, 2... Active layer, 3...
...gate electrode, 4...high concentration impurity diffusion region, 5.
... Source electrode, 6... Drain electrode, 7... Element isolation region, 8... Insulating film, 9... Photoresist film,
10... Opening part.
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Claims (1)

[Claims] A compound semiconductor device having a semiconductor element formed on a semi-insulating compound semiconductor substrate, characterized in that an annular element isolation region is provided in a region surrounding the semiconductor element region to be isolated from an adjacent semiconductor element. Compound semiconductor device.