JPH02115942A - Information processor test system - Google Patents

Abstract

PURPOSE:To perform a test for a branching prediction function by setting the branching destination of a branching instruction, setting an instruction to initialize a condition to be completed and an instruction to change a comparison value, and escaping from a loop when the instruction is an unconditional branching instruction. CONSTITUTION:The branching destination of the branching instruction in instruction sequence generated by a random test program generating means 11 is set by a branching destination decision means 12. And the instruction to initialize the condition to be compared by a conditional branching instruction and the instruction to change the comparison value to escape from a cyclic loop are set in the above instruction sequence by a branching environment setting means 13 set in the instruction sequence. Furthermore, when the unconditional branching instruction is issued, the instruction to escape from the loop is set by an unconditional loop escape means 14. A generated random test program is transferred to a first random test program 40 on a second main storage 4 via an inter-device interface 7. In such a manner, it is possible to perform the test for the branching prediction function.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device testing method, and particularly to a testing method using randomly generated test data and test procedures.

[Conventional technology]

Conventionally, this test method has been used to test the results of running a random test program with test data and test procedures randomly generated using random numbers with advance control of the information processing device under test enabled. and advance 1i1J all
The method used was to compare the results with those executed with the function disabled and decide whether it was good or bad.

[Problem that the invention seeks to solve]

In the conventional information processing device testing method described above, the branch instruction included in the random test procedure is executed only once, and the branch destination of the branch instruction is predicted and the predicted instruction is executed first. The drawback is that the branch prediction function of decoding and execution has not been tested.

[Means for Solving the Three Problems] The information processing device testing method of the present invention includes a random test program generating means, and a random test program generating means that sets a branch destination of a branch instruction in an instruction string generated by the random test program generating means. branching environment setting means for setting in the instruction string an instruction for initializing a condition to be compared with a conditional branching instruction and an instruction for changing a comparison value in order to break out of a repeat loop; It has an unconditional loop escape means that sets a command to exit the loop when the command is issued.

(Function) By having a branch destination determination means, a branch environment setting means, and an unconditional loop escape means, the branch Y81+! Functional tests can be performed.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram configuring an embodiment of the information processing device testing method of the present invention, FIG. 2 is a diagram showing the contents of a random test program, and FIG. 3 is a diagram showing the configuration of a test counter command table. , FIG. 4 is a diagram showing the branch instruction setting procedure in random test procedure 7-bull generation, FIG. 5 is a diagram showing the processing of random test task 10, FIG. 6 is a diagram showing the random test procedure generation process, Figure 7 shows the temporary instruction sequence table generation process, Figure 8 shows the random test procedure table creation process, Figure 9 shows the comparison value cut-off Iff setting process, and Figure 10 shows the unconditional FIG. 7 is a diagram showing a loop escape command setting process and a comparison value change setting process.

The system to which the information processing and equipment testing method is applied is
As shown in FIG. 1, it consists of a test processing device 1 and an information processing device under test 2, which are connected through an inter-device interface 7.

The test processing device 1 includes a first main memory 3 and a first instruction processing unit 5, and the information processing device under test 2 includes a second main memory 4 and a second instruction processing unit 6. It is. On the first main memory 3 of the test processing device 1, a random test program generation means 11 and a random test program starting means 15 are stored.
a random test task 10 that performs the execution result determination means 16 and the simulator 17; and the operating system 3.
0 is stored. The random test program generation means 11 includes a random test program [1 program], a branch destination determination means 12 for setting the branch destination of a branch instruction in the instruction sequence generated by the 1-gram generation means, and an instruction for initializing the conditions to be compared with the conditional branch instruction. branch I) setting means 13 for setting in the instruction sequence an instruction for changing a comparison value in order to escape from repeat loop 1; and unconditional loop escape means for setting an instruction for breaking out of the loop in the case of an unconditional branch instruction. 14.

The Shimi-Leuw 17 includes a third main memory 18 and a third instruction processing section 20.

As shown in FIG. 2, the random test program generated by the random test task 10 is a random test program consisting of 100 instructions created using random numbers and a test procedure end notification command that notifies the end of the random test program. It includes a test procedure and random test data consisting of register data and memory data generated using random numbers.

Next, the operation of this embodiment will be explained. .

First, the operating system 30 issues the first 1-3) command to the sindam test task 10, starts the random test task 10, and performs the processing shown in FIG.

First, the random test procedure shown in FIG. 2 is generated, and the random test data used by the random test procedure is generated using random numbers. 7 to the first random test program 40 on the second main memory 4, and the second random test program 1 to the third main memory 18 of the simulator 170.
9 (step 101). The first random test procedure ram 4 is then connected via the inter-device interface 7.
Step 102) to start up the similator 17, step 103) to run the second random test program, and after the similator 171' has finished running, the information processing device under test 2 until it receives a notification of completion of the first random test block [1 gram 40] (step 104). The random test task 10 that has received the notification of completion of the first random test program 40 of the information processing device under test 2 executes the execution results of the first random test program 40 stored in the second main memory 4 and the second random test task 10 . Compare the execution results of the test program 19 (Step 105). If they match, it is determined that there is no error and check for a termination request from the operating system 30 (Step 107); if there is no termination request, proceed to Step 105). The process returns to step 100 and continues the random test, and if there is a request for termination, the test is terminated. On the other hand, when the execution results are compared in step 105 and there is a discrepancy, the error part is output as an error message (step 106), a termination request from the operating system 30 is checked (step 107), and if there is no termination request, step The process returns to step 100 and continues the random test, and if there is a request for termination, the test is terminated.

Next, the random test procedure generation process performed in step 100 of FIG. 5 will be explained in detail using FIG. 6.

First, instructions are randomly extracted from the test target instruction table shown in FIG. 3 using random numbers and stored in the temporary instruction string daple shown in FIG. 3 (step 200). Next, check the number of instructions stored in the temporary instruction sequence table (Step 201), and if it is less than 100 instructions, check Step 201).
Return to and continue storing instructions. On the other hand, step 201
If 100 instructions have already been stored in step 202, a test procedure end notification instruction is stored in the temporary instruction string table (step 202).
). Next, instructions are taken out one by one from the beginning of the temporary instruction sequence table, the operand fields of each instruction are set, and the results are stored in the random test procedure table shown in FIG. 4 (step 203). Furthermore, random test data to be used in the random test procedure is generated using random numbers (step 204), and the process ends.

Next, the provisional instruction table generation step 200 of FIG. 6 will be explained in detail using FIG.

First, a random number n is generated modulo the number N of instructions in the test target instruction table (step 300), and the nth test target instruction 4 is extracted from the test target instruction table (step 30).
1) It is difficult to judge whether the fetched instruction is a branch instruction or not. Step 302) When it is not a branch instruction, as shown in FIG. 4(a)
The instruction to be tested is stored in the temporary instruction string -1-pull shown in step 305), O++ is stored in the flag table to indicate that it is suitable as the branch destination of the branch instruction (step 306), and the process ends. On the other hand, when the instruction extracted from the test target instruction table is a branch instruction, the branch instruction that is the test target instruction is stored in the temporary instruction sequence table (step 303), and the flag table indicates that it is inappropriate as a branch destination for the branch instruction. Step 304: Store “1”
), the process ends.

Next, details of the generation of the random test procedure table in step 203, which is performed in FIG. 6, will be explained using FIG. 8.

First, start from the beginning of the temporary instruction sequence table! , Step 400) to extract one instruction at a time; determine whether the extracted instruction to be tested is a branch instruction; step 401); step 408) to set the operand field of the instruction to be tested if it is not a branch instruction; ) is stored in the random test procedure table shown in step 409), and the process ends. - On the other hand, when the instruction to be tested is a branch instruction, a comparison value initialization instruction for initializing the conditions to be compared with a conditional branch instruction is incorporated into the random test procedure table (step 402), and when the branch instruction is an unconditional branch instruction, An instruction for escaping from the unconditional loop is incorporated into the random test procedure table (step 403).

Furthermore, an instruction that changes the comparison value in order to break out of the repeat loop is incorporated into the random test table (step 404), and the operand field of the branch instruction, which is the instruction to be tested, is set (step 405) and stored in the random test procedure table (step 405). Step 406). Next, as shown in FIG. 4(b), 1'' is stored in the flag table position corresponding to the period from the comparison value first III setting instruction to the branch instruction to indicate that the branch destination is inappropriate (step 407). Finish the process.

Next, the comparison value initialization process in step 402 in FIG. 8 will be explained in detail using FIG. 9.

First, a random number m is generated modulo the number of test target instructions in the tentative instruction string daple, 100, and the ml-th instruction in the sindam test procedure table is set as the branch destination of the branch instruction in step 501.
), it is determined whether the m-th instruction exists in the random test procedure table (step 502), and if it does not exist, the process returns to step 500; Step 503), II.
If it is not OII, the process returns to step 500. On the other hand, set the operand field of the comparison value initialization command in the 10th flag table (if the value is 0", then shift one place below the mth random test procedure table (step 504), the comparison value initialization command (step 505), and the comparison ( The initial setting command is stored in the m-th position of the random test procedure table (step 506), and the process ends.

Next, step 403 for setting an unconditional loop escape command and step 404 for setting a comparison value change command are performed in FIG.
This will be explained in detail using FIG.

First, the operan 1 field of the unconditional loop escape instruction is set (step 600) and stored in the random test procedure table (step 601).

Subsequently, the operand field of the comparison value change command is set (step 602), stored in the random test procedure table (step 603), and the process ends.

Here, examples of the processing in FIGS. 8, 9, and 10 will be explained in an easy-to-understand manner using FIG. 4.

First, as shown in Figure 4(a), a temporary instruction sequence table and a flag table are generated, one instruction at a time is extracted from the beginning of the temporary instruction sequence table, an operand field suitable for that instruction is set, and a random test is performed. The procedure table is stored sequentially from the beginning to the O instruction. When the n-th instruction, that is, 1<instruction, is reached in the temporary instruction sequence table, R
When determining that the instruction is a branch instruction and generating a random number m modulo 100, the number of instructions to be tested in the temporary instruction sequence table, m points to the n-5th instruction in the temporary instruction sequence table, that is, the H instruction. did. Therefore, flag daple n-・5
When I checked the number, it was 0'', which is appropriate as the branch destination.N-,5 of the C random test procedure table
Shift the instruction below by 1 and set the operand field in the n-5th position. Comparison value cut l! Stores the Il setting command. Next, 0 in the random test procedure table
After the instruction, when an unconditional branch instruction is used, store an unconditional loop escape instruction with the operand field set to branch to the instruction after the R instruction, and also change the comparison condition of the conditional branch instruction. Store the comparison value change instruction with the operand field set, then set the operand field of the R instruction, which is a branch instruction, to branch to 11 instructions, store it in the random test procedure table, and set the comparison value change 1
1" is stored in the position of the flag table corresponding to λ1 between the 1JI setting command and the 1st command.For the R command and below, [process in the same manner as described above to complete the random test procedure table.1" By the way, On the Kinomi side, the comparison value cut 1 setting command, unconditional loop escape command, and comparison value change command are stored when generating the random test procedure table, but it is clear that they may be incorporated into the temporary command sequence table. Although the unconditional loop escape instruction is included in the random test procedure table regardless of whether it is an unconditional branch instruction or a conditional branch instruction, it is clear that it may be included only in the case of an unconditional branch instruction.

Further, although the temporary instruction sequence table is used when generating the random test procedure table, it is clear that the temporary instruction sequence j-pull may be omitted. Furthermore, in this embodiment, the unconditional loop escape instruction and the comparison value change instruction are placed immediately before the branch instruction, but it is clear that other instructions may be inserted between them, and in the above embodiment, only a single loop is used. Although explained, it is clear that the same method as above can be used for multi-Φ loops as well. Furthermore, although the series of processes described above are performed on the test processing equipment 1 and the information processing device under test 2, it is clear that all the processes may be performed on the information processing device under test 2.

(Effects of the Invention) As described above, the present invention provides a branch destination determining means for randomly setting the branch destination of a branch instruction, and an instruction for initializing the conditions to be compared with a conditional branch instruction in generating a random test block E1gram. A branch environment means that sets an instruction to change the comparison value in order to break out of a repeat loop, and an unconditional loop escape means that sets an instruction to break out of the loop when an unconditional branch instruction is used. This has the advantage that branch prediction functions, which could not be tested in information processing equipment tests, can be tested.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram configuring an embodiment of the information processing device testing method of the present invention, FIG. 2 is a diagram showing the contents of a random test program, and FIG. 3 is a diagram showing the configuration of a test target instruction table. FIG. 4 is a diagram showing the branch instruction setting procedure in random test procedure table generation, FIG. 5 is a diagram showing the processing of random test task 10, FIG. 6 is a diagram showing the random test procedure generation process, and FIG. FIG. 8 is a diagram showing a temporary instruction sequence table generation process; FIG. 8 is a diagram showing a random test procedure Arble generation process; FIG. 9 is a diagram showing a comparison value initialization process;
FIG. 10 is a diagram showing the unconditional loop escape command setting process and the comparison value change setting process. DESCRIPTION OF SYMBOLS 1... Test processing device, 2... Information processing device under test, 3... First main memory, 4... Second main memory, 5
. . . first instruction processing unit, 6 . . . second instruction processing unit,
7... Inter-device interface, 10... Random test task, 11... Random test block [l-gram generation means, 12...
... Branch destination determining means, 13... Branch environment setting means, 14... Unconditional loop escape means, 15... Random test block [1 gram starting means, 16.
. . . Execution result determination means, 17 .
19...Second random test program [1 gram, 20...
-Third instruction processing unit, 30...operating system, 40...first
A random test of Bu[]g. Patent Applicant: Japan Electric Agency, Shushiki Company, Hokuriku NEC Software Co., Ltd. Agent: Patent Attorney: Han Uchihara Figure 2 Figure 1 Figure 3 LnN↑

Claims (1)

[Claims] 1. A random test program generation means, a branch destination determination means for setting a branch destination of a branch instruction in the instruction string generated by the random test program generation means, an instruction for initializing a condition to be compared with a conditional branch instruction, and repetition. An information processing device comprising branch environment setting means for setting an instruction for changing a comparison value in order to break out of a loop in the instruction string, and unconditional loop escape means for setting an instruction to break out of the loop in the case of an unconditional branch instruction. Test method.