JPS63265342A - central processing unit - Google Patents

Abstract

PURPOSE:To effectively debug a microprogram and to effectively check the hard ware by providing a reading route to an internal bus of an arithmetic part and reading out the data on the internal bus obtained at that time point to the outside. CONSTITUTION:When a control means 43 performs the start control, an arithmetic part 25 starts its operating to perform the processing based on a microprogram stored in a control memory 1 and the data stored in registers 4-6 and to deliver the processing result to an internal bus 50. When the means 43 performs the stop control, the part 25 stops its processing. Then a prescribed address is indicated from outside to an address indicating means 41. Thus the means 41 accepts the address and indicates this to the memory 1. Then a microinstruction stored previously into said address is read out and decoded. Thus the data stored in a desired one of registers 4-6 is delivered to the bus 50 via the part 25. A reading means 42 reads the delivered data to outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In order to meet the demands for higher functionality and higher speed of central processing units, the hardware and software thereof tend to become increasingly complex. The same applies to central processing units that execute instructions based on microprograms. Therefore, a microprogram composed of microinstructions (
The number of man-hours for developing and debugging (so-called firmware) is increasing. In order to efficiently develop and debug microprograms, the microprogram is executed step by step, checking the data held in various internal registers, etc., and then executing the next step. The means to do so are being used.

However, conventional microprogram debugging methods did not take into account the ability to directly grasp the data held by various internal registers, etc., so the data was temporarily transferred from each internal register to the register file. By advancing the steps of the microprogram until the data is saved and reading the data from this register file, the data in the desired register is indirectly grasped. Therefore, there was a problem in that it took time to debug the microprogram.

Therefore, in order to solve these conventional problems, the present invention provides a read path on the internal bus of the central processing unit, and also writes a microinstruction for outputting desired register data to the internal bus in advance to a predetermined location in the control memory. After the central processing unit is stopped, the data held in the desired register is output to the internal bus by specifying the address where the above microinstruction is stored, and read to each register. Similar to providing a path, the data held in the direct register can be read out.

(Industrial Application Field) The present invention relates to a central processing unit that executes instructions based on a microprogram control method, and particularly relates to a central processing unit that executes instructions based on a microprogram control method. By making it possible to read data from an internal bus, the present invention has the same effect as providing a read path for each register.

(Prior Art) An example of a central processing unit using a conventional microprogram control method is shown in FIG.

A control circuit 32 outputs various control signals 37 to each part of the central processing unit at predetermined timings. This control signal 37 also includes a clock signal 39 for synchronization. 1 is a control memory (CS) realized by a read-only memory (ROM). This control memory 1 stores in advance a microprogram (so-called firmware) composed of microinstructions.

2 is a microinstruction register (MIR) that holds microinstructions read from control memory 1; Address designation for control memory 1 is performed through a path from microinstruction address register (MIAR) 3 to multiplexer 30 to address decoder 29 when the central processing unit is activated. When the central processing unit is activated, the multiplexer 30 selects the output signal 49 based on the information in the address field 23 of the microinstruction set in the microinstruction register 2.

Therefore, after starting up the central processing unit, the control memory 1
The address instructions for the microinstructions are specified in the microinstruction address field 23 which is sequentially set in the microinstruction register 2.
It will be held at This address field 23 indicates the address of the next microinstruction to be read from the control store 1. Further, after the central processing unit is activated, the multiplexer 31 selects the output signal 49 from the address field 23 of the microinstruction set in the microinstruction register 2.

Therefore, the microinstruction address register 3 sequentially takes in the address indicated by the address field 23 of the microinstruction set in the microinstruction register 2, and holds this address.

The other input of the multiplexer 31 is externally connected to the control memory 1.
Address signal line 51 for instructing the address to
is connected. When a microinstruction is set in the microinstruction register 2, the information in each field 20, 21, and 22 of the set microinstruction is decoded by a decoding circuit (not shown) and set in the microinstruction register 2. A multiplexer 11.1, which will be described later, generates control signals 46 to 48 according to the specifications 9 functions of microinstructions.
0 is output to the calculation section 25.

The multiplexer 30 is controlled to select the microinstruction address register 3 when the central processing unit is stopped, and to select the output signal 49 based on the address information from the address field 23 when the central processing unit is in operation.

4.5 and 6.7 are data registers that store various data. The data multiplexer 11 can select either the data output from the data register 4 or the data register 5, and the data multiplexer 11 can select either the data output from the data register 4 or the data register 5.
is controlled by a control signal 46 based on information from field 21 of. The multiplexer 10 is capable of selecting either the data output by the data register 6 or the register file 8 and is controlled by a control signal 47 based on information from the field 22 of the microinstruction register 2. 20 is an operation instruction field, which includes an arithmetic logic unit (ALU) 13 and a shifter (SFT) 14.
It has control information for a control signal 48 for the arithmetic unit 25. This control signal 48 instructs the multiplexer 12 to function for the arithmetic logic unit 13 and shifter 14, and to select either the arithmetic logic unit 13 or the shifter 14. Multiplexer 12
The information from is set in the data register 7 via the internal bus 50. 8 is a register file (RF);
This is for centrally storing the various data stored in the data registers 4, 5, 6.7 during exception handling and the like.

At the start of exception handling, the data saved in the register file 8 is transferred to the signal line 18 and the multiplexer 15 for reading data. The data is read out to the outside of the central processing unit through the path of the signal line 19. A status register (SR) 9 stores a flag indicating the operating state of the central processing unit, and information stored in the status register 9 is transmitted from outside the central processing unit to a signal line 24. Multiplexer 15 for reading data. It is possible to read through the path of the signal line 19. The multiplexer 15 is selectively controlled by a select signal 16 from outside the central processing unit.

Furthermore, this multiplexer 15 can also read addresses from the microinstruction address register 3 via the signal line 26. This is a consideration for returning to the original microprogram address after the central processing unit executes other processing during exception processing or the like. That is, when the central processing unit is stopped, the microinstruction address register 3 holds the address of the next microinstruction to be executed. Then, the address of the microinstruction address register 3 is transferred to the signal line 26 and the multiplexer 1
5. Read and save via the signal line 19 path. When the exception handling etc. are finished and the original microprogram is restored, the address of the already saved microinstruction is set in the microinstruction address register 3 via the address signal line 51. Then, by restarting the central processing unit, the microprogram can be restarted from the original address.

[Problem that the invention seeks to solve]

However, in such conventional technology, it was not considered that the data held by each internal register could be directly grasped, so until the data was temporarily saved from each register to the register file. By advancing the steps of the program and reading data from this register file, the data in the desired register is indirectly grasped. Therefore, microprograms,
There was a problem that debugging was time consuming.

The present invention has been made in view of these conventional problems, and allows the data held in each register to be directly read externally, thereby making it possible to efficiently debug microprograms and verify hardware. The purpose is to provide a central processing unit capable of performing the following steps.

(Means for solving the problem) In order to achieve this object, the present invention includes a control memory in which a microprogram is stored in advance;
Performs processing based on the microprogram stored in the control memory and data held in the registers,
A calculation section that outputs the processing results to an internal bus, a control means that controls the start/stop of the processing and outputs control signals to each section, and a control section that outputs control signals from the outside when the processing section is stopped. A central processing unit comprising address instruction means for accepting an address for a control memory and instructing the address to the control memory, further comprising a reading means for reading out data outputted to the internal bus to the outside; It was decided to store a microinstruction that causes the data held in a desired register to be output to the internal bus via the arithmetic unit.

(Operation) The operation of the present invention will be explained based on the principle block diagram of the present invention shown in FIG.

Control memory l is microprogram and register 4.5.6
It stores microinstructions for outputting data held by the CPU to the internal bus 50 via the arithmetic unit.

First, when the control means 43 performs startup control, the calculation section 25
starts operation, performs processing based on the microprogram stored in the control memory 1 and data held in the registers 4 and 5, and transfers the processing results to the internal bus 5.
Output to 0. At this time, the control means 43 outputs a control signal 37 to each part.

Therefore, when the control means 43 performs stop control, the calculation section 2
5 stops the process. Then, when a predetermined address is instructed to the address instruction means 41 from the outside, the address instruction means 41 accepts this address and instructs the control memory 1 to receive the address. Then, the microinstruction previously stored at this address is read out and decoded, and the data held in a desired register among registers 4 to 6 is outputted to the internal bus via the arithmetic unit 25. Then, the reading means 42 reads this data outputted to the internal bus 50 to the outside.

(Example) An embodiment of the present invention will be described based on FIG.

This central processing unit differs from the conventional central processing unit shown in FIG. 3 in the following points.

First, the internal bus 50 located between the data register 7 and the multiplexer 12 and the multiplexer 15 for reading data are connected by a bus signal line 17. This bus signal line 17 corresponds to the reading means 42 described in the claims.

Second, the following microinstructions are stored in advance at predetermined addresses (spare addresses, etc.) in the control memory 1. For example, a microinstruction for reading data from data register 6, specifically, ``Multiplexer 10 selects data register 6, arithmetic logic unit 13 passes the output data of multiplexer 10 through, and outputs the data to multiplexer 12.'' output, the multiplexer 12 selects the arithmetic logic unit 13, and the multiplexer 12 selects the arithmetic logic unit 13.
The output data is outputted to the internal bus 50. " is stored in the control memory 1. For example, an instruction for verifying the function of the arithmetic logic unit 13, specifically, "Multiplexer 10 selects data register 6, multiplexer 11 selects data register 4, arithmetic logic unit 13 adds, The multiplexer 15 selects the arithmetic logic unit 13 and outputs the output data from the arithmetic logic unit 13 to the internal bus 50." is stored in the control memory 1. Furthermore, micro-instructions for outputting data held by other data registers 4.5, etc. to the internal bus 50, and micro-instructions for confirming the functions of the chic 14, etc., are also stored at predetermined addresses in the control memory 1. There is.

The address signal line 51, the multiplexer 31, and the microinstruction address register 3 realize the address instruction means 41 described in the claims.

Control circuit 32, control means 43 described in the claims
has been realized. This control circuit 32 sends the clock signal 39 to the microinstruction register 2 even when the central processing unit is stopped.
It is output to. Therefore, by stopping the central processing unit,
When a desired address is set on the address signal line 51 from the outside, this address is set in the microinstruction address register 3 from the multiplexer 31. Therefore, when a microinstruction is read from the control memory 1, this microinstruction is always set in the microinstruction register 2.

In the central processing unit having the above configuration, a case will be described in which data is read from a desired data register when debugging a microprogram. Note that the operations after the central processing unit is activated are the same as those of the prior art.

First, the central processing unit is brought into a stopped state. Then, multiplexer 31 selects address signal line 51 and multiplexer 30 selects microinstruction address register 3. At this time, the clock signal 39 from the control circuit 32 is still being output to the microinstruction register 2.

Registers 4-6 hold respective data as a result of a microinstruction operation executed immediately before the central processing unit stopped.

In such a state, a predetermined select signal 16 is output from the outside. Then, the multiplexer 15 can read the contents of the address held by the microinstruction address register 3 to the outside via the signal line 26, multiplexer 15, and signal line 38. Then save this address. Next, the microinstruction address register 3
Set the specified address to . Then, this set address reaches the address decoder 29 of the control memory 1 from the microinstruction address register 3 via the multiplexer 30. Therefore, the control memory 1 reads out a microinstruction stored in advance at a predetermined address and sets the instruction in the microinstruction register 2. The instructions set in the microinstruction register 2 are decoded and various control signals 46 to 48 are output. For example, if the set command is to read data from data register 6,
The state of the hardware for reading the data of data register 6, i.e. "Multiplexer 10 selects data register 6, arithmetic logic unit 13 selects multiplexer 1
0 output data is passed through to multiplexer 1.
2 and multiplexer 12 outputs to arithmetic logic unit 1
3 is selected, and the output data from this arithmetic logic unit 13 is output to the internal bus 50. ” That happens. In this state, the data in the data register 6 will be output to the internal bus 50 of the multiplexer 12. This data is then output from the internal bus 50 to the multiplexer 15 via the data signal line 17.

Therefore, when data from the internal bus 50 is selected by the select signal 16, the data from the data register 6 is read out from the multiplexer 15 via the signal line 19. By changing the address specified via address signal line 51, data in data register 4.5 can also be read.

Furthermore, the functions of the arithmetic logic unit 13 and the like can be confirmed by similarly indicating the address in which the above-mentioned microinstruction is stored via the address signal line 51.

In the central processing unit after such operation, among the data originally held in each register, only the address of the microinstruction address register 3 and the microinstruction of the microinstruction register 2 have changed. However, by restoring the saved addresses to the microinstruction address register 3 and microinstruction register 2 as will be described later, the original state can be restored.

In order to restart the central processing unit from the original state, the saved address is set in the microinstruction address register 3 from the address signal line 51 via the multiplexer 31.

Then, this address is set in the microinstruction address register 3 from the multiplexer 31. Therefore, when the central processing unit is restarted, the central processing unit restarts from the original address and the state in which the registers 4 to 7 are held.

According to this embodiment, when verifying hardware using a test program or the like, it is possible to verify the functions of the central processing unit without actually starting it, which is useful for reducing the time required for hardware verification. Furthermore, if a debugging console or the like is installed outside the central processing unit, a very powerful debugging tool can be provided.

(Effects of the Invention) According to the present invention, data held in a desired register is outputted to the internal bus of the arithmetic unit, and the outputted data is read out, without providing a readout path for each register. Therefore, data in each register can be read out relatively easily by operations according to the function of the microinstruction currently being executed. As a result, it is possible to provide a central processing unit that can efficiently debug microprograms and verify hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a central processing unit in an embodiment of the present invention, and FIG. 3 is a block diagram of a central processing unit in a conventional example. 1... Control memory (C3) 2... Micro instruction register (MIR) 3... Micro instruction address register (MIAR) 4-7... Data register (DR) 8... Register file (RF) 13... Arithmetic logic unit 14... Thick (SFT) 15... Multiplexer 16... Select signal 17... Bus signal line 41... Address instruction means 42... Reading means 43... Control means 50...internal bus 51...address signal line

Claims (1)

[Claims] Control memory (1) in which a microprogram is stored in advance
and performs processing based on the microprogram stored in the control memory (1) and the data held in the registers (4, 5, 6), and outputs the processing results to the internal bus (50). A calculation section (25), and a control means (43) that controls start/stop of processing of the calculation section (25) and outputs a control signal (37) to each section.
and address instruction means (41) for accepting an address for the control memory (1) from the outside and for instructing the address to the control memory (1) when the arithmetic unit (25) is stopping processing. The central processing unit is equipped with a reading means (42) for reading out the data outputted to the internal bus (50) to the outside, and the control memory (1) holds desired registers (4, 5, 6). The calculation unit (25)
A central processing unit characterized by storing microinstructions to be output to an internal bus (50) via the central processing unit.