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JPH02113528A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02113528A
JPH02113528A JP26641188A JP26641188A JPH02113528A JP H02113528 A JPH02113528 A JP H02113528A JP 26641188 A JP26641188 A JP 26641188A JP 26641188 A JP26641188 A JP 26641188A JP H02113528 A JPH02113528 A JP H02113528A
Authority
JP
Japan
Prior art keywords
semiconductor chip
insulating protective
protective film
stress
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26641188A
Other languages
Japanese (ja)
Inventor
Ikuo Niikura
郁生 新倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP26641188A priority Critical patent/JPH02113528A/en
Publication of JPH02113528A publication Critical patent/JPH02113528A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To cancel mechanical stress created when a semiconductor chip is sealed in a package by adjusting a thickness of an insulating protective film formed on the surface of the semiconductor chip or laminating such insulating protective films to provide a multiple layer. CONSTITUTION:Stress created by bonding a semiconductor chip 1 to a metallic substrate 3 acts such that the top face of the semiconductor chip 1 is extended and the bonded face is contracted. On the other hand, stress created by an insulating protective film 2 on the surface of the semiconductor chip 1 acts such that the top face of the chip 1 is contracted and the rear face is extended, Since these stresses act opposite to each other, the stress of the insulating protective film 2 can be controlled by selecting a type and thickness of the film 2 appropriately or by combining several such films to provide a multiple layer. In this manner, the stress created by bonding the semiconductor chip 1 to the metallic substrate 3 can be cancelled.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、シリコン(Si)やヒ化ガリウム(GaAs
)などの半導体基板に、回路素子を集積した半導体チッ
プを、プラスチックやセラミック容器に封入する際に生
じるそりを相殺する半導体装置の製造方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to silicon (Si) and gallium arsenide (GaAs).
The present invention relates to a method for manufacturing a semiconductor device that cancels warpage that occurs when a semiconductor chip, which is a semiconductor substrate such as a semiconductor substrate with circuit elements integrated therein, is sealed in a plastic or ceramic container.

従来の技術 SiやGaAsなどの半導体基板に多(の回路素子を集
積した半導体チップの表面に、外部との電気的接触や機
械的破損、あるいは水分などから保護するために、酸化
膜や窒化膜などの絶縁保護膜を形成する。
Conventional technology An oxide film or nitride film is applied to the surface of a semiconductor chip, which has a large number of circuit elements integrated on a semiconductor substrate such as Si or GaAs, to protect it from electrical contact with the outside, mechanical damage, moisture, etc. Form an insulating protective film such as

この絶縁保護膜を形成した半導体チップを金属でできた
リードフレームのグイパッド部分に接着し、この後、樹
脂封止をして半導体装置を形成していた。
The semiconductor chip on which the insulating protective film has been formed is adhered to the pad portion of a lead frame made of metal, and then sealed with resin to form a semiconductor device.

発明が解決しようとする課題 第2図に示すように、半導体基板1の表面に絶縁保護膜
2を形成すると応力により半導体基板1は絶縁保護膜2
側にそりが生じる。一方、第3図に示すように、半導体
基板1をリードフレームや金属容器等の金属基板3の上
に接着した場合、熱応力により半導体基板1の裏面側に
そりが生じる。
Problems to be Solved by the Invention As shown in FIG. 2, when the insulating protective film 2 is formed on the surface of the semiconductor substrate 1, the semiconductor substrate 1 is damaged by the insulating protective film 2 due to stress.
Warpage occurs on the sides. On the other hand, as shown in FIG. 3, when the semiconductor substrate 1 is bonded onto a metal substrate 3 such as a lead frame or a metal container, warpage occurs on the back side of the semiconductor substrate 1 due to thermal stress.

このように、応力による半導体基板のそりによって集積
回路素子や電気回路の特性が変化する問題があった。
As described above, there is a problem in that the characteristics of integrated circuit elements and electric circuits change due to warping of the semiconductor substrate due to stress.

本発明は、これらの応力の影響を少な(した半導体装置
を提供することを目的とするものである。
An object of the present invention is to provide a semiconductor device that is less affected by these stresses.

課題を解決するための手段 本発明の半導体装置の製造方法は、半導体チップ表面に
形成する絶縁保護膜の膜厚を調整したり、絶縁保護膜を
多層にすることにより半導体チップをパッケージに封入
する際に生じる機械的応力を相殺するものである。
Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention includes encapsulating a semiconductor chip in a package by adjusting the thickness of an insulating protective film formed on the surface of a semiconductor chip or by forming multiple layers of insulating protective films. This offsets the mechanical stress that occurs when

作用 本発明の半導体装置の製造方法によれば、半導体チップ
の応力によるそりを押えることができる。
Effect: According to the method of manufacturing a semiconductor device of the present invention, it is possible to suppress warping of the semiconductor chip due to stress.

実施例 半導体チップにかかる応力の大きなものは、第3図に示
すように半導体チップを金属基板に接着することによる
ものと、第2図に示すように半導体チップ表面の絶縁保
護膜を堆積することにより生じるものとがある。金属基
板に接着することによる応力は半導体チップ表面が伸び
、接着面側が縮む方向である。一方、半導体チップ表面
の絶縁保護膜による応力は半導体チップ表面が縮み、裏
面が伸びる方向である。この両者の応力の方向は相反し
ているので、絶縁保護膜の種類、膜厚、及びこれらを多
層に組合せることにより絶縁保護膜の応力を制御して、
半導体チップを金属基板に接着することにより生じる応
力を相殺することができる。また、容器基板への接着に
よる応力を、接着剤、接着の温度、基板材料などにより
制御することも可能である。
Examples of large stress applied to the semiconductor chip are due to bonding the semiconductor chip to a metal substrate as shown in Figure 3, and due to depositing an insulating protective film on the surface of the semiconductor chip as shown in Figure 2. There are some things that occur due to The stress caused by bonding to a metal substrate is such that the surface of the semiconductor chip stretches and the bonding surface side contracts. On the other hand, the stress caused by the insulating protective film on the surface of the semiconductor chip is such that the front surface of the semiconductor chip contracts and the back surface stretches. Since the directions of these two stresses are opposite to each other, the stress of the insulating protective film can be controlled by changing the type and thickness of the insulating protective film, and by combining these into multiple layers.
Stress caused by bonding a semiconductor chip to a metal substrate can be offset. It is also possible to control the stress caused by adhesion to the container substrate by adjusting the adhesive, adhesion temperature, substrate material, etc.

一定の半導体チップ接着工程に対して、絶縁保護膜とし
て、窒化シリコン膜をシリコン半導体表面に堆積し、こ
の膜厚に対して、回路素子である抵抗の抵抗値を測定し
た結果を第1図に示す。
For a certain semiconductor chip bonding process, a silicon nitride film is deposited on the surface of a silicon semiconductor as an insulating protective film, and the resistance value of a resistor, which is a circuit element, is measured against this film thickness. Figure 1 shows the results. show.

第1図に示すように、膜厚を変化させることにより応力
が変化して抵抗値が変化する。上記の両者の応力が相殺
するとき抵抗変化が最小となる。
As shown in FIG. 1, by changing the film thickness, the stress changes and the resistance value changes. When the above two stresses cancel each other out, the resistance change is minimized.

このため窒化シリコン膜の厚さを最適化して抵抗変化を
最小にする。
Therefore, the thickness of the silicon nitride film is optimized to minimize the resistance change.

発明の効果 本発明の半導体装置の製造方法によれば、半導体チップ
を容器に封入する際の基板に接着する工程に対応して、
絶縁保護膜の種類、膜厚、それらの組み合わせによる多
層を制御することにより、応力を相殺することができる
。この結果、半導体素子や回路の特性の変化をさけるこ
とができる。
Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, in response to the step of adhering a semiconductor chip to a substrate when encapsulating it in a container,
Stress can be offset by controlling the type of insulating protective film, the film thickness, and the multilayer structure based on a combination thereof. As a result, changes in the characteristics of semiconductor elements and circuits can be avoided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による半導体チップの接着工程を一定に
して、絶縁保護膜の膜厚を変化させたときの集積回路内
の抵抗値の変化を示す図、第2図は半導体チップ表面に
絶縁保護膜を堆積したことによる半導体チップの変形図
、第3図は半導体チップを金属基板に接着したときの半
導体チップの変形図を示す。 1・・・・・・半導体チップ、2・・・・・・絶縁保護
膜、3・・・・・・金属基板。 代理人の氏名 弁理士 粟野重孝 ほか1名第1図 第2図 第3図
Figure 1 is a diagram showing the change in resistance value within an integrated circuit when the thickness of the insulating protective film is changed while the bonding process of the semiconductor chip is kept constant according to the present invention. FIG. 3 shows a deformation of the semiconductor chip due to the deposition of a protective film. FIG. 3 shows a deformation of the semiconductor chip when the semiconductor chip is bonded to a metal substrate. 1... Semiconductor chip, 2... Insulating protective film, 3... Metal substrate. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1 Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)半導体チップ表面に形成する絶縁保護膜の膜厚を
調整することにより、半導体チップを金属基板に接着す
る際に生じる機械的応力を相殺することを特徴とする半
導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, which comprises adjusting the thickness of an insulating protective film formed on the surface of the semiconductor chip to offset mechanical stress generated when bonding the semiconductor chip to a metal substrate.
(2)半導体チップ表面に形成する絶縁保護膜を多層に
することにより、半導体チップを金属基板に接着する際
に生じる機械的応力を相殺することを特徴とする半導体
装置の製造方法。
(2) A method for manufacturing a semiconductor device, characterized in that mechanical stress generated when bonding a semiconductor chip to a metal substrate is offset by forming a multilayer insulating protective film on the surface of the semiconductor chip.
JP26641188A 1988-10-21 1988-10-21 Manufacture of semiconductor device Pending JPH02113528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26641188A JPH02113528A (en) 1988-10-21 1988-10-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26641188A JPH02113528A (en) 1988-10-21 1988-10-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02113528A true JPH02113528A (en) 1990-04-25

Family

ID=17430562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26641188A Pending JPH02113528A (en) 1988-10-21 1988-10-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02113528A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5947182A (en) * 1995-05-08 1999-09-07 Nippon Steel Corporation System for producing continuously metallic coil

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5947182A (en) * 1995-05-08 1999-09-07 Nippon Steel Corporation System for producing continuously metallic coil

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