JPS62173744A - Ceramic substrate for semiconductor devices - Google Patents
Ceramic substrate for semiconductor devicesInfo
- Publication number
- JPS62173744A JPS62173744A JP61016200A JP1620086A JPS62173744A JP S62173744 A JPS62173744 A JP S62173744A JP 61016200 A JP61016200 A JP 61016200A JP 1620086 A JP1620086 A JP 1620086A JP S62173744 A JPS62173744 A JP S62173744A
- Authority
- JP
- Japan
- Prior art keywords
- oxide
- ceramic substrate
- glass
- ceramic
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用分野〕
本発明は半導体装置、特にガラス封止型半導体装置に用
いるセラミック基板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a ceramic substrate used in a semiconductor device, particularly a glass-sealed semiconductor device.
現在使用されている集積回路（以下ＩＣと略称する）の
パンケージ法は樹脂封止型、ガラス−セラミック封止型
及び積層セラミック型の３種類に分類される。これらの
パッケージ法は信頼性及び価格の点で長短があり、信頼
性に関しては積層セラミック型、ガラス−セラミック型
、樹脂封止型の順に硬れ、一方価格の点ではこの逆の順
序となる。最近では、各パッケージ法の短所を克服すべ
く研究が進められているが、信頼性と価格において中間
的なガラス−セラミック封止型の改良が強く望まれてい
る。The pancage methods for integrated circuits (hereinafter abbreviated as IC) currently in use are classified into three types: resin sealing type, glass-ceramic sealing type, and laminated ceramic type. These packaging methods have advantages and disadvantages in terms of reliability and cost, with the multilayer ceramic type, glass-ceramic type, and resin-sealed type being harder in this order in terms of reliability, while in terms of price they are in the opposite order. Recently, research has been carried out to overcome the shortcomings of each packaging method, but there is a strong desire to improve the glass-ceramic sealing type, which is intermediate in terms of reliability and cost.
第２図に従来のガラス−セラミック封止型半導体装置の
一例を示す。ＡＩＯ等の酸化物系のセラミック基板１の
凹部に工Ｃ等の半導体素子２がＡｕ等の接着層３により
チップボンディングされている。又、セラミック基板１
にはリードフレーム５が低融点ガラス４により固定され
、半導体素子２の各”ＲＦＭとリードフレーム５の各イ
ンナーリード先端部とがＡｕまたはＡ４のポンディング
ワイヤ６で各々結線されている。そして、半導体素子２
を気密封止すべく、セラミック基板ｌの周縁のガラス封
止部において低融点ガラス７によりＡＩＯ等のセラミッ
クまたはフバール等の金属からなるキャップ８をセラミ
ック基板１に固定しである。FIG. 2 shows an example of a conventional glass-ceramic sealed semiconductor device. A semiconductor element 2 such as a material C is chip-bonded to a recessed portion of an oxide-based ceramic substrate 1 such as AIO using an adhesive layer 3 such as Au. Also, ceramic substrate 1
A lead frame 5 is fixed with a low melting point glass 4, and each ''RFM of the semiconductor element 2 and each inner lead tip of the lead frame 5 are connected with a bonding wire 6 of Au or A4. Semiconductor element 2
In order to hermetically seal the ceramic substrate 1, a cap 8 made of ceramic such as AIO or metal such as Fvar is fixed to the ceramic substrate 1 using a low melting point glass 7 at the glass sealing portion at the periphery of the ceramic substrate 1.
一方、工Ｃを中心とする半導体装置の小型化、高集積化
及び軽量化の傾向に伴ない、パッケージは小型になる反
面、半導体素子の発熱量は益々増大している。しかし、
従来使用されているＡＩＯに代表される酸化物系セラミ
ック基板は熱伝導率が小さいために、半導体素子で発生
した熱を効率良く放散することができず、熱の蓄積によ
って半導体装置の誤動作を招いたり、場合によっては熱
膨張係数の差から半導体素子に亀裂が発生することがあ
った。On the other hand, with the trend toward smaller size, higher integration, and lighter weight of semiconductor devices, mainly those of electronic devices, packages are becoming smaller, but the amount of heat generated by semiconductor elements is increasing. but,
Conventionally used oxide-based ceramic substrates such as AIO have low thermal conductivity, so they cannot efficiently dissipate the heat generated by semiconductor elements, and the accumulation of heat can lead to malfunction of semiconductor devices. In some cases, cracks may occur in semiconductor elements due to differences in thermal expansion coefficients.
従来の酸化物系セラミック基板に代って、熱放散性に優
れ、熱膨張係数が半導体素子のそれに近いセラミック基
板として、非酸化物系セラミック基板の開発が進めらね
ている。しかし、非酸化物系セラミックは酸化物系セラ
ミックに比べて封止用低融点ガラスとの封着性が劣ると
いう問題点がある。半導体装置が小型化、高集積化及び
経呈叱するに伴なってガラス封正面債は益々減少する傾
向にあり、非酸化物系セラミック基板はガラス封着性分
改善しなければ実用に供し得ない実状で、ある０
本発明はかくる問題点を解決し、ガラス封着性が優れた
非酸化物系セラミック基板を提供することを目的とする
。In place of conventional oxide ceramic substrates, non-oxide ceramic substrates are being developed as ceramic substrates that have excellent heat dissipation properties and have a coefficient of thermal expansion close to that of semiconductor devices. However, non-oxide ceramics have a problem in that they have poorer sealing properties with low-melting glass for sealing than oxide ceramics. As semiconductor devices become smaller and more highly integrated, the number of glass-sealed substrates tends to decrease, and non-oxide ceramic substrates cannot be put to practical use unless their glass-sealing properties are improved. The object of the present invention is to solve these problems and provide a non-oxide ceramic substrate with excellent glass sealing properties.
本発明の半導体用セラミック基板は、非酸化物系のセラ
ミックからなり、少なくともガラス封止されるべき部分
の表面に酸化物層を有することを特徴とする。The semiconductor ceramic substrate of the present invention is made of non-oxide ceramic and is characterized by having an oxide layer on the surface of at least a portion to be sealed with glass.
非酸化物系セラミックとしては、熱放散性を、二愛れ熱
膨張係数が半導体素子のそれに近い、窒化アルミニウム
（Ａ４Ｎ） 、炭化ケイ素（ｉ’Ｅｉｃ）または窒化ケ
イ素（Ｓｉ Ｎ ）が好ましい。As the non-oxide ceramic, aluminum nitride (A4N), silicon carbide (i'Eic), or silicon nitride (SiN), which has heat dissipation properties and a coefficient of thermal expansion close to that of a semiconductor element, is preferable.
酸化物層としては、上記の非酸化物系セラミック基板及
び封止用ガラスとの密着性が浸れており、形成が容易な
酸化アルミニウム（Ａｔｏ）また）ま酸化ケイ素（Ｓｉ
Ｏ）が好ましい。The oxide layer may be aluminum oxide (ATO) or silicon oxide (Si), which has good adhesion to the non-oxide ceramic substrate and sealing glass and is easy to form.
O) is preferred.
酸化物層３非酸化物系セラミック基板の表面に形成する
方法としては、（１）基板の高温での酸化処理法及び（
２）蒸着等の表面被覆法がある。Methods for forming the oxide layer 3 on the surface of the non-oxide ceramic substrate include (1) oxidation treatment of the substrate at high temperature;
2) There are surface coating methods such as vapor deposition.
（１）非酸化物系セラミックを構成するＡ７及びＳｌ等
の金属元素はいずれも極めて強い酸化傾向を有しく例え
ば、Ａｔ Ｏ生成の自由エネルギーは一９００ＫＪ／ｍ
ａｔ 、 １２００ Ｃ） 、酸化物は窒化物及び炭化
物よりも安定である。従って、非酸化物セラミックを大
気または酸素等の酸化性雰囲気中で高温に曝すことによ
り、その表面にＡＩＯ及びＳｉＯ等の酸化物層を形成す
ることができる。(1) Metallic elements such as A7 and Sl that make up non-oxide ceramics all have an extremely strong tendency to oxidize. For example, the free energy of At O formation is 1900 KJ/m
at 1200 C), oxides are more stable than nitrides and carbides. Therefore, by exposing a non-oxide ceramic to high temperature in the air or an oxidizing atmosphere such as oxygen, an oxide layer such as AIO and SiO can be formed on its surface.
（２１蒸着等の表面被覆法のなかでは、気化した原材料
をイオン化することによりセラミック基板との良好な密
着性分湯ることができるイオンブレーティング法、スノ
ぐンタリング法及びプラズマａ ＶＤ法が好ましい。し
かし、プラズマＴ、 Ｖ Ｄ法は成型速度が遅く、高温
が必要であり、反応生成物（Ｈ（Ｊ又はＨＯ）による汚
染により半導体装置の信顕性を損なう可能性がある等の
点で本発明においては実用的ではない。(Among the surface coating methods such as 21 vapor deposition, the ion blating method, snow guntering method, and plasma a VD method are preferred because they can achieve good adhesion to the ceramic substrate by ionizing the vaporized raw material.) However, the plasma T and VD methods have slow molding speeds, require high temperatures, and are unfavorable in that they may impair the reliability of semiconductor devices due to contamination by reaction products (H (J or HO)). Not practical in invention.
次に、ガラス−セラミック封土型半導体装肯（′）−例
としてフラット−パッケージを示した第トコな用いて、
本発明の半導体装置用セラミック基ヅを更に説明する。Next, a glass-ceramic sealed semiconductor device (')--a flat package is shown as an example--is shown in detail below.
The ceramic substrate for semiconductor devices of the present invention will be further explained.
本発明の非酸化物系セラミツニ′・基板っけ少なくとも
ガラス封止されるべき部分の表面に酸化物層１０が形成
されている。この基板９を用いた実装工程では従来と同
様に、基板９の凹部にＩＣ等の半導体素子２がＡｕ等の
接着フ３によりチップボンディングされる。又、セラミ
ック基板９の酸化物−１０上にけり−ドフレーム５が低
融点ガラス４により固定され、半導ｆト素子この各電極
と１）−ドフレーム５の各インナーリード先端部とがボ
ンディングワイヤ６で各々結線される。最後に、半導体
素子２ひ気密封止すべく、セラミック基板９の周縁のガ
ラス封上部において低融点ガラス７によりセラミックま
たは金属からなるキ′ヤ゛ノブ８をセラミック基板９に
固定してフラット−パッケージが構成される。An oxide layer 10 is formed on the surface of at least the portion of the non-oxide ceramic substrate of the present invention to be sealed with glass. In the mounting process using this substrate 9, a semiconductor element 2 such as an IC is chip-bonded to a recessed portion of the substrate 9 using an adhesive film 3 made of Au or the like, as in the conventional case. Further, a die frame 5 is fixed on the oxide 10 of the ceramic substrate 9 with a low melting point glass 4, and each of the electrodes of the semiconductor element and the tip of each inner lead of the die frame 5 are bonded. Each is connected with a wire 6. Finally, in order to hermetically seal the semiconductor element 2, a ceramic or metal canister 8 is fixed to the ceramic substrate 9 with a low melting point glass 7 at the top of the glass seal at the periphery of the ceramic substrate 9 to form a flat package. is configured.
第１図ではフラントーパッケージの例企示したが、本発
明の非酸化物系セラミック基板はガラス−セラミック封
止型パッケージ全般に適用することができる。従って、
リードフレーム？用いずにセラミック基板上に多数の金
属配線層を形成する場合にも適用でき、その場合には非
酸化物系セラミック基板上に酸化物層を形成し、その上
に金属配線層３形成してもよいし、あるいは非酸化物系
セラミック基板上に金属配線層を形成した後その上に酸
化物層を形成してもよい。前者はもちろん後者の構成も
非酸化物系セラミック基鈑のガラス封止されるべき部分
表面に酸化物層が存在することに変わりなく、本発明の
範囲に含まれるものである。Although FIG. 1 shows an example of a Franteau package, the non-oxide ceramic substrate of the present invention can be applied to glass-ceramic sealed packages in general. Therefore,
Lead frame? It can also be applied to the case where a large number of metal wiring layers are formed on a ceramic substrate without using a metal wiring layer. In that case, an oxide layer is formed on a non-oxide ceramic substrate, and a metal wiring layer 3 is formed on it. Alternatively, a metal wiring layer may be formed on a non-oxide ceramic substrate and then an oxide layer may be formed thereon. Both the former and the latter configurations are included within the scope of the present invention since an oxide layer is present on the surface of the portion of the non-oxide ceramic substrate to be sealed with glass.
〔１乍用 〕
非酸化物系セラミック基板上の酸化物層がガラス封着性
を改善する理由は、封止用低融点ガラスは主成分及び副
成分がＰｂ０ＸＢ Ｏ及びＳｉＯ等の酸化物であるため
、酸化物層となじみが良く、強固な封着が得られるもの
と考えられる。[For 1 item] The reason why the oxide layer on the non-oxide ceramic substrate improves the glass sealing property is that the main component and subcomponents of the low melting point glass for sealing are oxides such as Pb0XBO and SiO. Therefore, it is thought that it is compatible with the oxide layer and a strong seal can be obtained.
特に記載した以外は従来の方法に従って下記３種類のＱ
ｕａｄ型フラット−パッケージを試作したつ■第１図の
構造な有し、基板はｋｌＮからなりガラス封止部にＡＩ
Ｏ層を備えたもの。Ａｔ０７ｔはＡｔ）ｊ基板を大気中
１２００ ｔ：’で１時間熱処理することにより膜厚２
μｍに形成した。Unless otherwise noted, the following three types of Q
We prototyped a UAD type flat package.It has the structure shown in Figure 1.The substrate is made of KIN, and the glass sealing part is made of AI.
Equipped with an O layer. At07t has a film thickness of 2 by heat-treating the At)j substrate in the air at 1200 t:' for 1 hour.
It was formed in μm.
■第１図の構造を有し、基板はｋｌＨからなりガラス封
止部にｋｌ Ｏ層を備えたもの。Ａ４０ 層は初・期
真空度２ Ｘ １０− ’ ｔｏｒｒ、導入０ガス王４
Ｘ １０− ’ｔｃｒｒ、基板温度３００Ｃ，及び成
膜速度３５χ／ｓｅｃのイオンブレーティング法で膜厚
５μｍに形成した。■It has the structure shown in Fig. 1, the substrate is made of klH, and the glass sealing part is provided with a klO layer. The A40 layer has an initial vacuum of 2 x 10-' torr, 0 gas introduced, and 4
The film was formed to a thickness of 5 μm using an ion blasting method at a substrate temperature of 300 C and a film formation rate of 35 χ/sec.
■第２図の構造を有し、基板はＡ Ｉ Ｎからなるが酸
化物層を備えていないもの。(2) A device having the structure shown in FIG. 2, with a substrate made of AlN but without an oxide layer.
これら３種類の試作品に気相での熱衝撃（１サイクル；
−６３ＣＸ１０分→２５ＣＸ５分→１５０ ＣＸ
１０分）を１００サイクル与えた後、Ｈｅリークテスト
３実施した。試作品■及び■（本発明）にはリークが全
く認められなかったが、試作品■（従来）にはリークが
認められた。These three types of prototypes were subjected to thermal shock in the gas phase (1 cycle;
-63CX 10 minutes → 25CX 5 minutes → 150 CX
After applying 100 cycles of 10 minutes), He leak test 3 was conducted. No leakage was observed in the prototypes ■ and ■ (invention), but leakage was observed in the prototype ■ (conventional).
本発明によれば、熱放散性に優れ、熱膨張係数が半導体
素子のそれに近い非酸化物系セラミックの性質３損なう
ことなく、ガラス封着性が優れた半導体装置用の非酸化
物系セラミック基板な提供することができる。According to the present invention, a non-oxide ceramic substrate for semiconductor devices that has excellent heat dissipation properties and excellent glass sealing properties without impairing the properties of non-oxide ceramics whose coefficient of thermal expansion is close to that of semiconductor elements. can be provided.
第１図は本発明の非酸化物系セラミック基板を用いたガ
ラス封止型半導体装置の一例を示す断面図であり、第２
図は酸化物系セラミック基板を用いた従来のガラス封止
型半導体装置の一例を示す断面図である。
１・・酸化物系セラミック基板 ２・・半導体素子４・
・低融点ガラス ５・・リードフレーム６・・ボンディ
ングワイヤ ７・・低融点ガラス８・・キャップ ９・
・非酸化物系セラミック基板１０・・酸化物層
第１図
第２図FIG. 1 is a sectional view showing an example of a glass-sealed semiconductor device using the non-oxide ceramic substrate of the present invention;
The figure is a cross-sectional view showing an example of a conventional glass-sealed semiconductor device using an oxide-based ceramic substrate. 1. Oxide ceramic substrate 2. Semiconductor element 4.
・Low melting point glass 5・・Lead frame 6・・Bonding wire 7・・Low melting point glass 8・・Cap 9・
・Non-oxide ceramic substrate 10...Oxide layer Fig. 1 Fig. 2
Claims (3)
ラス封止されるべき部分の表面に酸化物層を有すること
を特徴とする半導体装置用セラミック基板。(1) A ceramic substrate for a semiconductor device, which is made of a non-oxide ceramic and has an oxide layer on the surface of at least a portion to be sealed with glass.
炭化ケイ素または窒化ケイ素からなる、特許請求の範囲
（１）項に記載の半導体装置用セラミック基板。(2) The non-oxide ceramic is aluminum nitride,
The ceramic substrate for a semiconductor device according to claim (1), which is made of silicon carbide or silicon nitride.
素である、特許請求の範囲（１）項に記載の半導体装置
用セラミック基板。(3) The ceramic substrate for a semiconductor device according to claim (1), wherein the oxide layer is aluminum oxide or silicon oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61016200A JPS62173744A (en) | 1986-01-28 | 1986-01-28 | Ceramic substrate for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61016200A JPS62173744A (en) | 1986-01-28 | 1986-01-28 | Ceramic substrate for semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62173744A true JPS62173744A (en) | 1987-07-30 |
Family
ID=11909865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61016200A Pending JPS62173744A (en) | 1986-01-28 | 1986-01-28 | Ceramic substrate for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62173744A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8017967B2 (en) | 2004-09-09 | 2011-09-13 | Toyoda Gosei Co., Ltd. | Light-emitting element including a fusion-bonding portion on contact electrodes |
-
1986
- 1986-01-28 JP JP61016200A patent/JPS62173744A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8017967B2 (en) | 2004-09-09 | 2011-09-13 | Toyoda Gosei Co., Ltd. | Light-emitting element including a fusion-bonding portion on contact electrodes |
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