JPH02113489A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To simplify the control and to reduce the burden on a graphic processing unit by generating respective reset signals and counting-up clocks of a column system and a row system based on a clock and horizontal and vertical synchronizing signals according with the display dot rate. CONSTITUTION:A timing signal SYC of a timing generating circuit STG and a timing signal phiy of a timing generating circuit RTG go to the high level in accordance with a horizontal signal HSYC from a display device DPLY. This signal phiy is the reset signal to reset a column address decoder CAD. Word lines of a semiconductor storage device MARY are successively selected by the decoder CAD with the counting-up clock passing a column address buffer CAB to which a clock A0 to Ai according with the display dot rate from a graphic processing unit GPU is supplied, and data lines are selected in the same manner, and memory cells at intersections between both lines are extracted to control the display on the display device. Thus, the control of the array MARY is simplified and the burden on the graphic processing unit is reduced to increase the processing speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective when used in multi-port RAM (random access memory) used as image memory.

[Conventional technology]

In an image system, there is an image memory (frame buffer memory) for displaying characters or figures on a display device, and a random access port that randomly inputs and outputs stored data in units of one bit or multiple bits, and a storage data There is a multi-port RAM (dual port RAM) which is used as the above-mentioned image memory and is equipped with a serial access port that serially inputs and outputs images in units of word lines.

The multi-board RAM is described, for example, in "Nikkei Electronics" published by Nikkei McGraw-Hill, March 24, 1986, pages 243 to 264.

[Problem to be solved by the invention]

FIG. 4 shows the conventional multi-boat RA described above.
A connection diagram of an imaging system using M is shown. In the figure, the multi-board RAM (MPRAM) is controlled by the image processing device GPU, and is activated when the row address strobe signal RAS is set to low level, for example, and at this time, the data transfer control signal DT10R is set to low level. identifies the read transfer mode of stored data that is serially output. Then, when the data transfer control signal DT10E is returned to high level, the stored data read out in units of word lines is transferred to the data register of the serial access port SAP.

The image processing device GPU is supplied with the horizontal synchronization signal H3YC and the vertical synchronization signal vsyc from the display device DPLY. address signal AO- which also specifies the word line.
At is the horizontal synchronization signal H3YC and vertical synchronization signal vs.
Must be formed according to yc. This increases the processing load on the image processing device GPU as the ton trading speed of the display device DPLY increases, and this becomes a factor that ultimately limits the speeding up of the dot rate.

The purpose of this invention is to simplify control of multi-baud
An object of the present invention is to provide a semiconductor memory device such as a RAM. Another object of the invention is to reduce the processing load on an image processing device;
The aim is to promote faster ton trading.

The above and other objects and novel features of this invention include:
It will become clear from the description of this document and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical embodiments disclosed in this application is as follows. That is,
A multiport RAM or the like is provided with an address counter that sequentially specifies word lines, and the multiport RAM or the like is directly connected to a display device without going through an image processing device. Then, it transfers the read data to the serial access port, initializes the column system selection circuit, and increments the address counter in accordance with the horizontal synchronization signal supplied from the display device, and initializes the address counter in accordance with the vertical synchronization signal. , each is performed autonomously.

[For production]

According to the above means, it is possible to simplify the address control related to the serial output of the multi-port RAM, etc. and the transfer control of read data, and to directly connect the multi-port RAM, etc. to the display device, thereby reducing the processing load on the image processing device, and The system's ton trading can be made even faster.

〔Example〕

Figure 1 shows a multi-port RAM to which this invention is applied.
(A block diagram of an embodiment of MPRAM> is shown. Also, FIG. 3 shows a connection diagram of an embodiment of an image system using the multi-port RAM of FIG. 1. First, according to the diagram in this example, the multi-port
An overview of the configuration and operation of the RAM will be explained. Note that the circuit elements constituting each circuit block in FIG. 1 are formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques, although this is not particularly limited.

In FIG. 3, the image system includes, but is not particularly limited to, an image processing device GPU, a multiport RAM, and a display device DPLY.As will be described later, the multiport RAM randomly inputs and outputs stored data in 4-bit units. The random access port RAP includes a random access port RAP that outputs stored data serially in word line units, and a serial access port SAP that serially outputs stored data in word line units. A signal Tτ, a column address strobe signal cAs, and a write enable signal WE are supplied, and i+l bit X address signals AXO to AXi are supplied via an address signal line AO-At.
and Y address signals AYO to AYi are supplied in a time-division manner. Although not particularly limited, the random access port RAP selectively supplies a RAP enable signal REN to the image processing device GPU. Further, random input/output signal lines R100 to RIO3 are provided between the image processing device GPU and the random access port RAP for randomly inputting and outputting storage data.

On the other hand, the serial access port S of multiport RAM
The serial clock signal SC is supplied to the AP from the image processing device GPU, and the display device DPLY is also supplied to the AP.
A horizontal synchronizing signal H3YC and a vertical synchronizing signal vsyc are supplied from the horizontal synchronizing signal H3YC and the vertical synchronizing signal vsyc. The storage data serially output from the serial access port SAP is transmitted through the serial output signal line 80.
0 to S03, it is transmitted to the display device DPLY. Here, the serial clock signal SC is adapted to the ton trade of the display device DPLY, and the storage data input and output via the random input/output signal lines R100 to RIO3 and the serial output signal lines SoO to S03 is, for example, a color signal. Associated with each bit of the code.

As shown in FIG. 1, the random access port RAP of the multi-port RAM has a basic configuration of a memory array MARY. The memory array MARY includes, but is not particularly limited to, m+1 word lines WO to Wm arranged in parallel in the vertical direction in the figure, n+1 sets of complementary data lines arranged in parallel in the horizontal direction, and these. Arranged in a grid at the intersections of word lines and complementary data lines (m+l)
X (n+1) dynamic memory cells. In this embodiment, the number m+1 of word lines constituting the memory array MARY is the same as the number of horizontal scanning lines of the display device DPLY, and the number fi+l of complementary data lines is the same as the number of pixels provided on each horizontal scanning line. be done.

Word lines WO to Wm constituting the memory array MARY are coupled to a row address decoder RAD and are alternatively brought into a selected state.

Although not particularly limited, the row address decoder RAD is supplied with i+1 bit internal address signals xO-xi from the address multiplexer AMX, and is supplied with the timing signal φX from the RAP timing generation circuit RTG.

The row address decoder RAD receives the timing signal φ.
By setting X to a high level, it is selectively activated. In this operating state, the row address decoder R
AD decodes the internal address signals xO to xi, and selects a corresponding word line of the memory array MARY at a high level.

The first input terminal of the address multiplexer AMX has
Although not particularly limited, refresh address counter R
Internal address signals % r x O to rxi are supplied from the FC. Further, internal address signals axQ to axi are supplied from the row address buffer RAB to its second input terminal, and internal address signals sxQ to sxi are supplied from the SAP address counter SAC to its third input terminal. Ru. The address multiplexer AMX is further supplied with timing signals φrf, φrp, and φsp as selection control signals from the RAP timing generation circuit RTG. Here, the timing signal φrr is selectively set to a high level when the multi-board RAM is placed in refresh mode.

Further, the timing signals φrp and φ3p are selectively set to high level when the multi-port RAM is placed in the random access mode or the read transfer mode.

Address multiplexer AMX outputs internal address signal r when timing signal φrf is set to high level.
Select xO~rxi and apply the above internal address signals xO~x
It is supplied to the row address decoder RAD as i. Further, when the timing signal φrp or φsp is set to high level, the internal address signals axQ-axi or 3xO to sxi are respectively selected and used as the internal address signals xO to xi.

When the multi-port RAM is placed in the refresh mode, the refresh address counter RFC performs an increment operation according to the timing signal φrc supplied from the RAP timing generation circuit RTG, and calculates the internal address signal r x O-%-r x i form.

Row address buffer RAB is connected to external terminal AO- when multiport RAM is in random access mode.
X address signal AX time-divisionally supplied via At
O to AXi are captured and held in accordance with the timing signal φar supplied from the RAP timing generation circuit RTG. Then, based on these X address signals, the internal address signal axQ-maxi is formed.

The SAP address counter SAC is supplied with a timing signal φsc (second clock signal) and φsr (second reset signal) from the SAP timing generation circuit STG. Here, the timing signal φsc is formed in accordance with the horizontal synchronizing signal H3YC supplied from the display device DPLY, as will be described later, and the timing signal φsc is
sr is formed according to the vertical synchronization signal vsyc. S
The AP address counter SAC performs a stepping operation in accordance with the timing signal φsc to form the internal address signals sxO to sxi. Further, the SAP address counter SAC is brought to an initial state in accordance with the timing signal φsr, and its count value is set to all bits of logic "0".

The above row address decoder RAD, address multiplexer AMX and refresh address counter RF
C, the row address buffer RAB and the SAP address counter SAC constitute a row system selection circuit of the multi-baud RAM.

On the other hand, the complementary data lines constituting the memory array MARY are coupled at one end to the corresponding switch MO3FET pair of the column switch C8W, and are further selectively connected to the RAP common data line RCDONRCD3 in groups of four. On the other hand, it is coupled to a corresponding unit amplifier circuit of sense amplifier SA, and further coupled to a corresponding launch of data register DR of serial access port SAP.

The column switch C8W is an n+1 set of switches M provided corresponding to each complementary data line of the memory array MARY.
It is composed of a pair of O5FETs.

One of these switch MO3FET pairs is coupled to the corresponding complementary data line of the memory array MARY, and the other is commonly coupled alternately in four pairs to the RAP common data lines RCDO to RCD3.

4 sets of adjacent switches MO3 of column switch C8W
The gates of the FET pairs are commonly coupled, and a corresponding data line selection signal is supplied from the column address decoder CAD. As a result, the column switch C3W selects the corresponding four sets of complementary data lines of the memory array MARY as the RAP common data lines RCDO-RCD3 by selectively setting the data line selection signal to a high level. It has the ability to connect directly.

The column address decoder CAD is supplied with an internal address signal ayQ-ayl of t+l hint from the column address buffer cAB, although it is not particularly limited.
A timing signal φy is supplied from a timing generation circuit RTG.

The column address decoder CAD is selectively brought into operation when the timing signal φy is set to a high level. In this operating state, the column address decoder CAD decodes the internal address signals ayQ to ayi and selectively sets the corresponding data line selection signal to a high level selection state.

Column address buffer CAB connects external terminals AO to Ai
Y address signal AYO~ supplied in a time-division manner via
AYi is fetched and held in accordance with the timing signal φaC supplied from the RAP timing generation circuit RTG. The internal address signals ayQ to ayi are then formed based on these Y address signals.

The sense amplifier SA includes fi+1 unit amplifier circuits provided corresponding to each complementary data line of the memory array MARY. These unit amplifier circuits operate according to the timing signal φpa supplied from the RAP timing generation circuit RTG. Selectively activated. In this operating state, each unit circuit of the sense amplifier SA amplifies the minute read signal output to the corresponding complementary data line from the n+1 memory cells coupled to the selected word line of the memory array MARY, and level or low level 2
Use as value read signal. These binary readout signals are
By temporarily setting the timing signal φdt to a high level, it is taken into the corresponding launch of the data register DR.

The RAP common data lines RCDO to RCD3 are respectively coupled to the output terminals of the corresponding data input buffers of the RAP data input/output circuit RIO, and further coupled to the input terminals of the corresponding data output buffers.

The RAP data input/output circuit RIO includes four data input buffers and data output buffers provided corresponding to the RAP common data lines RCDO to RCD3. Among these, the data input buffers include, but are not particularly limited to, the following:
A timing signal φW is commonly supplied from the RAP timing generation circuit RTG, and a timing signal φro is commonly supplied to the data output buffer.

Each data input buffer of the RAP data input/output circuit RIO is selectively put into an operating state when the multi-board RAM is put into a selected state in the random write mode and the timing signal φW is set at a high level. In this operating state, each data input buffer forms a complementary write signal according to the write data supplied via the RAP data input/output terminals R100 to RI03, and transmits it to the corresponding RAP common data line RCDO to RCD3. do. On the other hand, in each data output buffer of the RAP data input/output circuit R1O, the multi-board RAM is in a selected state in the random read mode, and the timing signal φro
is set to a high level, thereby being selectively put into an operating state. In this operating state, each data output buffer is
The binary read signal transmitted from the selected memory cell of the memory array MARY via the corresponding RAP common data lines RCDO to RCD3 is further amplified and transmitted via the corresponding RAP data input/output terminals R100 to R103. Send.

The RAP timing generation circuit RTG is supplied with a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE from the image processing device GPU, and the SAP timing generation circuit ST
An internal control signal syc is supplied from G. The RAP timing generation circuit RTG forms the various timing signals mentioned above based on these control signals and internal control signals, and supplies them to each circuit of the random access port RAP. Also, based on the internal control signal syc, a RAP enable signal REN is formed and supplied to the image processing device GPU. This RAP enable signal REN is a horizontal synchronization signal H3YC or a vertical synchronization signal vsy, as described later.
When c is set to a high level, the serial output operation by the serial access port SAP is interrupted, and the read transfer mode and refresh mode are completed. By setting the signal REN to low level, the random access port R of the multiport RAM
Identify that the AP is accessible.

On the other hand, the serial access port S of multiport RAM
The AP has a data register DR as shown in FIG.
, a data selector DSL, and a pointer PNT.

Data register DR includes n+1 latches provided corresponding to each complementary data line of memory array MARY. The input/output nodes of these latches are coupled on one side to the corresponding unit amplifier circuit of the sense amplifier SA via the corresponding transfer switch MOSFET, and further coupled to the corresponding complementary data line of the memory array MARY.

On the other hand, it is selectively connected to the SAP common data lines 5CDO to 5CD3 via the corresponding output switch MO3FET of the data selector DSL.

The transfer switch MO3FET of the data register DR is supplied with a timing signal φdi from the RAP timing generation circuit RTG. This timing signal φdt
As will be described later, when the multi-port RAM is placed in the read transfer mode, the selection operation of the word line is completed and the binary read signal of the memory cell coupled to this word line is established on the corresponding complementary data line. At the point in time, it is set to a temporarily high level. As a result, these binary read signals are taken into the corresponding latches of the data register DR and held.

The data selector DSL has the same configuration as the column switch C8W described above, and includes fi+1 sets of output switches MOS FET provided corresponding to each complementary data line of the memory array MARY.
One of T is coupled to the human output node of the corresponding latch of the data register DR, and the other is commonly coupled alternately to the SAP common data lines 5CDo-3CD3 every fourth set. The gates of four adjacent sets of switches MO3FET of the data selector DSL are each commonly coupled, and a corresponding register selection signal is supplied from the pointer PNT. As a result, the data selector DSL selectively connects the four corresponding launches of the data register DR to the SAP common data lines 5CDO to 5CD3 by selectively setting the register selection signal to a high level. have a function.

Pointer PNT has each bit in memory array M
The basic configuration is a shift register provided corresponding to each complementary data line of ARY. The pointer PNT has SAP
The timing signal φp is generated from the timing generation circuit STG for
c (first clock signal) and φpr (first reset signal) are supplied. Here, the timing signal φpc is formed according to the serial clock signal SC, as will be described later, and the timing signal φpr is formed according to the horizontal synchronization signal H3.
Formed according to YC.

The pointer PNT is brought into an initial state by temporarily setting the timing signal φpr to a high level. At this time, although not particularly restricted, a shift signal of logic "1" is set in the first bit of pointer PNT, and all other bits are reset to logic "0". The shift signal of logic "1" set in the first bit of pointer PNT is shifted to pointer P according to timing signal φpc.
Shifted within NT. As a result, the register selection signals are sequentially formed, and according to these register selection signals, the read data held in the data register DR is
S via SAP common data lines 5CDO to 5CD3
The data is sequentially transmitted to the AP data input/output circuit SIO.

In other words, the pointer PNT is the data selector DSL
Together with this, it constitutes a column system selection circuit of the serial access port SAP.

The SAP data input/output circuit SIO includes four data output cover sofas provided corresponding to the SAP common data lines 5CDO to 5CD3. These data output buffers receive a timing signal φs from the SAP timing generation circuit STG.

is commonly supplied.

Each data output buffer sofa of the SAP data input/output circuit SIo is selectively put into an operating state by setting the timing signal φ3o to a high level. In this operating state, each data output bumper sends read data outputted from the data register DR via the corresponding SAP common data line 5CDO-3CD3 via the serial data output terminals SOO to S03.

The SAP timing generation circuit STG is connected to the image processing device G.
The various timing signals mentioned above are formed based on the serial clock signal SC supplied from the PU and the horizontal synchronization signal H3YC and vertical synchronization signal Vsyc supplied from the display device DPLY, and the serial access port S
Supplies each circuit of the AP.

FIG. 2 shows a timing diagram of one embodiment of the serial output mode of the multi-board RAM of FIG. Referring to the figure, an overview and characteristics of the serial output mode of the multiport RAM of this embodiment will be explained. Note that FIG. 2 exemplarily shows a portion of the serial output mode of the multi-board RAM in which the word line Wm at the final row address is transferred to the word line WO at the first row address.

In FIG. 2, the serial access port SAP of the multiport RAM is supplied with a serial clock signal SC from the image processing device GPU, and the display device DPL is supplied with a serial clock signal SC from the image processing device GPU.
From Y to horizontal synchronization signal H3YC and vertical synchronization signal vsyc
is supplied. Among these, the serial clock (R SC
is adapted to the ton trade of display devices DPLY, as described above. In addition, the horizontal synchronization signal H3YC is
It is kept at a high level periodically in accordance with the horizontal scanning of the electron beam in the display device DPLY, and for a relatively long period of time covering the horizontal retrace period of the electron beam. Furthermore, the vertical synchronization signal VSYC is transmitted to the display device DP.
It is set to a high level periodically in accordance with the vertical scanning of the electron beam in LY, and for a longer period of time covering the vertical advance period of the electron beam.

In the SAP timing generation circuit STG, although not particularly limited, the internal control signal syc is set to high level at the rising edge of the horizontal synchronization signal H3YC, and the timing signals φpr and φ3C are temporarily set to high level. On the other hand, in the RAP timing generation circuit RTG,
By setting the internal control signal syc to a high level,
The timing signal φsp is set to a high level, and a little later, the timing signals φX, φpa, and φdt are sequentially set to a high level.

In the serial access port SAP, the timing signal φpr is temporarily set to a high level, so that the pointer PNT is set to an initial state, and the first bit thereof is set to a logic "1".
” shift signal is set.

On the other hand, in the random access port (RAP), by temporarily setting the timing signal φ3C to a high level,
The SAP address counter SAC is incremented and its count value becomes "m". Furthermore, the read transfer mode is started by setting the timing signal φsp to a high level. That is, when the timing signal φsp is set to high level, the output signal of the SAP address counter SAC, that is, the internal address signals sxQ to sxi, is selected by the address multiplexer AMX and transmitted to the row address decoder RAD. Further, by setting the timing signal φX to a high level, the row address decoder RAD is put into an operating state. As a result, the word line Wm at the final row address of the memory array MARY is brought into a selected state, and the minute read signals of the n+1 memory cells coupled to this word line are output to the corresponding complementary data lines. These minute read signals are amplified by the corresponding unit amplification circuits of the sense amplifier SA when the timing signal φpa is set to a high level, and are converted into binary read signals. Then, the timing signal φdt
By setting the data to a high level, the data are taken into the corresponding latches of the data register DR all at once and held.

Next, in the random access port RAP, the refresh mode is started when the read transfer mode ends and the timing signal φsp is returned to the low level. That is, at the falling edge of the timing signal φ3p, the timing signal φrf is first set to a high level, and the timing signal φrc, not shown, is temporarily set to a high level. As a result, refresh address counter RFC is incremented, and refresh address counter R
A refresh operation is performed on the word line specified by FC.

Furthermore, at the random access port RAP, when the refresh mode ends and the timing signal φrf is returned to the low level, the RAP enable signal REN is set to the low level, and the random access port of the multi-port RAM is set to the low level for the image processing device GPU. It is notified that the RAP is accessible. This results in
The image processing device GPU can execute the random access mode until the horizontal synchronization signal H8YC is returned to low level and the RAP enable signal REN is returned to high level.

When the horizontal synchronization signal H3YC is returned to the low level, the SAP timing generation circuit STG of the serial access port SAP returns the internal control signal syc to the low level, and the timing signal φ3o is set to the high level. Furthermore, a timing signal φpc is generated in synchronization with the serial clock signal SC. In the RAP timing generation circuit RTG, when the internal control signal syc is set to a low level, the RAP enable signal REN is returned to a high level, and the random access mode by the image processing device GPU is prohibited.

In the serial access port SAP, when the timing signal φ30 is set to a high level, the SAP data input/output circuit 310 is put into an operating state. At this time, the pointer PNT is set to the initial state as described above, and the data selector DSL is supplied with a register selection signal for selecting the first 4 bits of the data register DR.

Therefore, when the SAP data input/output circuit SIO is brought into operation, the first to fourth data registers DR
The read data co held in the latch is transmitted to the SAP data input/output circuit 310 via the SAP common data lines 5CDO to 5CD3, and is further transmitted to the display device DP via the SAP data output terminals 800 to SO3.
Sent to LY.

Hereinafter, the pointer PNT performs a shift operation according to the timing signal φpc, and thereby a series of stored data c
O~cn are the above SAP data output terminals 800~30
3 to the display device DPLY.

When the serial output operation of a series of stored data regarding the word line Wm is completed and the horizontal synchronization signal H3YC and the vertical synchronization signal vsyc are set to high level at the same time, the internal control signal syc is set to high level again in the SAP timing generation circuit STG. The timing signals φpr and φsr are temporarily set to high level. In addition, in the RAP timing generation circuit RTG, when the internal control signal syc is set to high level, the timing signal φ3p is set to high level again, and with a slight delay, the timing signals φs, φpa, and φdt are sequentially set to high level. level.

In the serial access port SAP, the above-mentioned timing signal φ3r is temporarily set to high level, so that the SAP
The address counter SAC is set to an initial state, and its count value becomes "0".

As a result, the random access port RAP starts the read transfer mode for the word uAWO at the first row address, and the read data of fi+1 memory cells coupled to the word line WO is transferred to the data register DR.
be taken in. Furthermore, when these read transfer modes end, a refresh mode is executed by the random access port RAP, and when the refresh mode ends, the RAP enable signal REN is set to a low level. As a result, the image processing device GPU
The horizontal synchronization signal H3YC and vertical synchronization signal vsyc are both returned to low level and the RAP enable signal REN
The random access mode can be executed for a relatively long period of time until the is returned to a high level.

When both the horizontal synchronization signal H3YC and the vertical synchronization signal vsyC are returned to low level, in the SAP timing generation circuit STG, the internal control signal syc is returned to low level, and the timing signal φ30 is set to high level.

Furthermore, a timing signal φpc is generated in synchronization with the serial clock signal SC.

As a result, the RAP enable signal REN is returned to high level, the random access mode by the image processing device GPU is prohibited, the SAP data input/output circuit SIO is activated, and a series of stored data CO related to the word line WO is ~Cn serial output operation is started.

As mentioned above, the multiport RAM of this embodiment has
A pointer PNT is provided to sequentially select the complementary data lines of the memory array MARY, and a pointer SA is provided to sequentially select the word lines of the memory array MARY.
A P address counter SAC is provided. The serial access port SAP of the multi-board RAM is supplied with a serial clock signal SC that matches the dot rate of the display device DPLY, and a horizontal synchronization signal H3Y.
C and vertical synchronization signal vsyc are the display device DPL.
Supplied directly from Y. The pointer PNT of the multi-board RAM is incremented in accordance with the timing signal φpc formed based on the serial clock signal SC, and brought to an initial state in accordance with the timing signal φpr formed based on the horizontal synchronization signal H3YC. Ru. Further, the SAP address counter SAC is incremented in accordance with a timing signal φsc formed based on the horizontal synchronization signal H3YC, and brought to an initial state in accordance with a timing signal φ3r formed based on the vertical synchronization signal vsyc. . In other words, in the serial access port SAP of the multi-board RAM of this embodiment, the step operation and initialization of the address selection circuit accompanying the serial output operation of the series of image data are performed using the serial clock signal SC, the horizontal synchronizing signal H3YC, and the vertical synchronizing signal H3YC. It is performed autonomously by monitoring the synchronization signal vsyc, and does not require control by the image processing device GPU.
Therefore, the processing load on the image processing device GPU is reduced,
As the processing capacity is increased, the dot rate of the image system will be accelerated.

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device such as a multi-port RAM used as an image memory, the following effects can be obtained.

That is, (1) A multi-port RAM, etc. is provided with an address counter that sequentially specifies word lines, and the multi-port RAM, etc. is directly connected to a display device without going through an image processing device.
It autonomously transfers read data to the serial access port, initializes the column selection circuit, and increments the address counter in accordance with the horizontal synchronization signal supplied from the display device, and initializes the address counter in accordance with the vertical synchronization signal. By doing so, it is possible to simplify the control of the serial output mode regarding image data.

(2) According to the above (11), it is possible to directly control the serial output mode of multi-port RAM, etc. by the display device.

(3) The above items (11 and (2)) have the effect of further speeding up the ton trading of the image system.

(40) Items (1) and (2) above have the effect of reducing the processing load on the image processing device.

(5) Items (1) to (brown terms) have the effect of increasing the processing capacity of the image processing device and improving the performance of the image system.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not fixed to the above-mentioned examples and can be changed in various ways without advancing the gist of the invention. For example, in FIG. 1, the pointer PNT of the serial access port SAP can be replaced by an address counter and a decoder that sequentially designate complementary data lines. Moreover, conversely, the SAP address counter SAC can be replaced with a pointer provided in parallel with the row address decoder RAD, for example. If refresh operations and random accesses by the image processing device are all performed during the horizontal synchronization signal H3YC or vertical synchronization signal vsyC, and access to the memory array MARY is not required during the serial output period, the data register DR may be deleted. can.

Random access port RAP may be replaced with a serial input port having serial input functionality.

The memory array MARY may be composed of a plurality of memory mats or may be composed of static memory cells.

The multiport RAM may input/output storage data in units of 1 bit, 2 bits, or 8 bits. In FIG. 2, the read transfer mode and the refresh mode may be executed by changing their order, and the RAP enable signal REN may be set to a high level when it is enabled. In FIG. 3, the serial clock signal SC may be supplied from the display device DPLY to the multi-board RAM.
(Multi-Baud) RAM shown in the figure, the configuration and the second
Various embodiments may be adopted, such as the combination of control signals shown in the figure and the configuration of the image system shown in FIG. 3.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to a multi-board RAM used as an image memory, which is the background field of application of the invention, but it is not limited to this (for example, The present invention can also be applied to various semiconductor storage devices such as serial ROMs that have only a serial output function. Can be widely used in equipment.

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application are briefly explained as follows. That is, a multi-port RAM or the like is provided with an address counter that sequentially specifies word lines, and the read data transfer operation to the serial access port, initialization of the column system selection circuit, and the above-mentioned address counter are performed according to the horizontal synchronization signal supplied from the display device. By autonomously performing the stepping operation and initializing the address counter according to the vertical synchronization signal, control of the serial output mode regarding image data can be simplified. As a result, the processing load on the image processing device can be reduced, its processing capacity can be increased, and the tonne trade of the image system can be speeded up.

[Brief explanation of the drawing]

The first TyJ is a multi-boat RA to which this invention is applied.
FIG. 2 is a timing diagram showing an example of the serial output mode of the multi-board RAM shown in FIG.
FIG. 4 is a connection diagram showing an example of an image system using the multi-board RAM shown in FIG.
FIG. 2 is a tangent Vt diagram showing an example of an image system using the . MPRAM...multi-baud) RAMSRAP...random access port, sAP...serial access port, MARY...memoria 1/-(, RAD...
・Row address decoder, AMX...Address multiplexer, RFC...Refresh address count, RAB...Row address buffer, SAC...S
AP address address counter A...Sense amplifier, C
8W...Column switch, CAD...Column address decoder, CAB...Column address buffer, R
IO...RAP data input/output circuit, RTG...R
AP timing generation circuit, DR...data register, DSL...data selector, PNT...pointer, SO...data output circuit for SAP, STG...S
AP timing generation circuit. GPU ・Image processing device, DPLY ・00 ice play device.

Claims (1)

[Claims] 1. A memory array consisting of a plurality of data lines and word lines arranged orthogonally and a plurality of memory cells arranged in a grid at the intersections of the data lines and word lines;
a column system selection circuit that is brought to an initial state in accordance with a reset signal and sequentially brings the data lines to a selected state by performing a stepping operation in accordance with a first clock signal; a row-related selection circuit that sequentially selects the word lines by performing a stepping operation in accordance with the clock signal of the display device; a timing generation circuit that receives a horizontal synchronization signal of the display device to form the first reset signal and the second clock signal, and further receives a vertical synchronization signal of the display device and forms the second reset signal. A semiconductor memory device comprising: 2. The semiconductor memory device has a multi-port R that includes a random access port that randomly inputs and outputs storage data in units of one bit or multiple bits, and a serial access port that serially outputs storage data in units of word lines.
AM, and the column system selection circuit is included in the serial access port, and the serial access port further includes a data register that captures and holds stored data read out in word line units according to a predetermined timing signal. 2. The semiconductor memory device according to claim 1, wherein said timing generation circuit further forms said timing signal based on said horizontal synchronization signal. 3. The semiconductor memory device operates in a read transfer mode of serially output storage data, a refresh mode of storage data, and a random access mode using the random access port during a period in which the horizontal synchronization signal or the vertical synchronization signal is valid. A semiconductor memory device according to claim 1 or 2, characterized in that the semiconductor memory device executes the following steps.