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JPH02110948A - Semiconductor device and its mounting - Google Patents

Semiconductor device and its mounting

Info

Publication number
JPH02110948A
JPH02110948A JP26164988A JP26164988A JPH02110948A JP H02110948 A JPH02110948 A JP H02110948A JP 26164988 A JP26164988 A JP 26164988A JP 26164988 A JP26164988 A JP 26164988A JP H02110948 A JPH02110948 A JP H02110948A
Authority
JP
Japan
Prior art keywords
electrodes
thickness
wiring board
mounting
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26164988A
Other languages
Japanese (ja)
Inventor
Hiroaki Fujimoto
博昭 藤本
Kenzo Hatada
畑田 賢造
Takao Ochi
岳雄 越智
Yoichiro Ishida
洋一郎 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP26164988A priority Critical patent/JPH02110948A/en
Publication of JPH02110948A publication Critical patent/JPH02110948A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase the degree of deformation of bump electrodes due to pressing in the case of mounting and to contrive to make possible an increase in the density of the mounting without causing the failure of an electrical connection by a method wherein a semiconductor element provided with the bump electrodes, whose sectional configurations in their thickness directions are formed into an almost quadrangle and whose sizes are made smaller than their thicknesses, is connected to a wiring board. CONSTITUTION:An insulating substrate 7 having conductor wirings 8 and a semiconductor element (an LSI chip) 10 provided with bump electrodes 6, which have one side or a diameter smaller than their thicknesses and have an almost quadrangular section in their thickness directions, are fixed to each other with an insulative resin 9 in such a way that the wirings 8 and the electrodes 6 are made to coincided with each other and they electrically come into contact and are connected to each other. Moreover, the resin 9 is applied on the parts of the wirings 8 provided on the wiring board 7 and after the element 10 provided with the electrodes 6, which have one side or a diameter smaller than their thicknesses and have an almost quadrangular section in their thickness directions, is fixed by pressure making their electrodes 6 coincide with the wirings 8 on the region of the resin 9 spread on the board 7, the resin 9 is hardened and with the element 10 fixed on the board 7, the wirings 8 and the electrodes 6 are electrically connected to each other.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体装置及びその実装方法に係り、特にマ
イクロコンピュータやゲートアレイ等に使用する多電極
、狭ピッチのLSIチップを実装する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device and its mounting method, and particularly relates to a method of mounting a multi-electrode, narrow-pitch LSI chip used in microcomputers, gate arrays, etc. .

(従来の技術) 従来、半導体装置の製造分野で、LSIチップ等の半導
体素子をフェースダウンして、直接回路基板に面実装す
るMBB(マイクロバンプボンディング)と呼ばれる実
装技術がある。
(Prior Art) Conventionally, in the field of manufacturing semiconductor devices, there is a mounting technique called MBB (micro bump bonding) in which a semiconductor element such as an LSI chip is face-down and surface-mounted directly onto a circuit board.

第3図は、そのMBB実装技術によって実装するLSI
チップの突起電極の形成を示す工程断面図である。
Figure 3 shows an LSI mounted using the MBB mounting technology.
FIG. 3 is a process cross-sectional view showing the formation of protruding electrodes on the chip.

まず、第3図(a)のように、半導体素子とじてのLS
Iチップを形成した半4体ウェハ21の電極22を有す
る面に保護膜23を設けて、 Ti−Pd−Au。
First, as shown in FIG. 3(a), the LS as a semiconductor element
A protective film 23 is provided on the surface of the semi-quartet wafer 21 on which the I-chip is formed and has the electrode 22, and is made of Ti-Pd-Au.

Cr−Au等のバリアメタル24を蒸着によって形成さ
せ、その後、フォトリソグラフィー技術によりメツキレ
ジスト25を形成する。なお、その厚みは通常、1μ醜
ないし2μl程度である。
A barrier metal 24 such as Cr-Au is formed by vapor deposition, and then a plating resist 25 is formed by photolithography. Note that the thickness is usually about 1 μl to 2 μl.

その後、同図(b)に示すように、Auti−電気メツ
キして突起電極26を形成させ1次に、同図(c)に示
すように、フォトエツチングにより不要部のバリアメタ
ル24を除去する。ここで、突起電極26の厚さは10
μmないし30μm、大きさは50μmφないし100
μ閣φ程度であり、配列ピッチは100IJ11ないし
300μm程度で、断面形状は同図(c)でわかるよう
に、メツキレジスト25以上の厚み(図では高さ)では
横方向にもメツキが成長するため、底面部突起を有する
入角形状を呈している。
Thereafter, as shown in the figure (b), protruding electrodes 26 are formed by auto-electroplating, and then, as shown in the figure (c), unnecessary portions of the barrier metal 24 are removed by photoetching. . Here, the thickness of the protruding electrode 26 is 10
μm to 30μm, size is 50μmφ to 100
The pitch is approximately 100IJ11 to 300μm, and the cross-sectional shape is shown in the same figure (c). If the thickness of the plating resist is 25 or more (height in the figure), the plating will grow in the lateral direction as well. Therefore, it has an angular shape with a bottom protrusion.

このようなバンプ形状では、高密度実装のために突起電
極26の微細化を行う場合、その底面寸法を極めて小さ
くしなければならないが、そうすることによる強度の低
下は免れず、また、電極のメツキが横方向に成長するた
め、微細化に伴い厚みを小さくする必要があり、それに
より配線基板へ実装時の加圧時による突起電極の変形度
が小さくなり、配線基板上の導体配線との接触不良の原
因を生ずることになる。
In such a bump shape, when miniaturizing the protruding electrodes 26 for high-density mounting, the bottom dimension must be made extremely small, but this inevitably reduces the strength of the electrodes. Since the plating grows laterally, it is necessary to reduce the thickness with miniaturization, which reduces the degree of deformation of the protruding electrodes when pressure is applied during mounting on the wiring board, and improves the connection with the conductor wiring on the wiring board. This will cause poor contact.

第4図は、上述のように形成したLSIチップを配線基
板に実装する工程を示す図で、21ないし26までの符
号は第3図と同じものを示している。
FIG. 4 is a diagram showing the process of mounting the LSI chip formed as described above on a wiring board, and the reference numerals 21 to 26 are the same as those in FIG. 3.

まず、第4図(a)において、27はLSIチップを実
装する配線基板で、セラミック、ガラス等よりなり、そ
の面上にはLSIチップを搭載、接続する導体配線28
を有し、紫外線(以下、UV線と略す)硬化性または熱
硬化性の絶縁性樹脂29が図示のように塗布される。導
体配線28にはCr −Au 。
First, in FIG. 4(a), 27 is a wiring board on which an LSI chip is mounted, and is made of ceramic, glass, etc., and conductive wiring 28 on which the LSI chip is mounted and connected.
An ultraviolet (hereinafter abbreviated as UV ray) curable or thermosetting insulating resin 29 is applied as shown in the figure. The conductor wiring 28 is made of Cr-Au.

^D、 Cu、  I T O(Indium Tin
 0xide)等が、また、絶縁性樹脂29にはエポキ
シ系、アクリル系等の樹脂が用いられる。
^D, Cu, ITO(Indium Tin
For the insulating resin 29, an epoxy resin, an acrylic resin, or the like is used.

次に、同図(b)のように、Au等からなる突起電極2
6を有するLSIチップ30を、その突起電極26と導
体配線28を対向し位置合わせして搭載し、配線基板2
7の絶縁性樹脂29が塗布されている領域に加圧ツール
31を用いて圧着する。この時、LSIチップ30の突
起電極26は塑性変形し、同時に導体配線28との間に
介在する絶縁性樹脂29が突起電極26の周囲に押出さ
れて、突起電極26と導体配線28が電気的に接触、接
続される。この状態で絶縁性樹脂29を硬化させた後、
同図(c)のように加圧ツール31を撤去すれば、LS
Iチップ30は配線基板27に硬化した絶縁性樹脂29
により固着されるとともに、変形した突起電極26と導
体配線28は電気的接触を良好に保って固定され、LS
Iチップ3oの配線基板27への実装が終了する。
Next, as shown in the same figure (b), a protruding electrode 2 made of Au etc.
6 is mounted with its protruding electrodes 26 and conductor wiring 28 facing each other and aligned, and mounted on the wiring board 2.
The pressure tool 31 is used to press the area where the insulating resin 29 of No. 7 is applied. At this time, the protruding electrodes 26 of the LSI chip 30 are plastically deformed, and at the same time, the insulating resin 29 interposed between the protruding electrodes 26 and the conductor wiring 28 is pushed out around the protruding electrodes 26, so that the protruding electrodes 26 and the conductor wiring 28 are electrically be contacted and connected to. After curing the insulating resin 29 in this state,
If the pressure tool 31 is removed as shown in FIG. 3(c), the LS
The I chip 30 is a hardened insulating resin 29 on the wiring board 27.
At the same time, the deformed protruding electrode 26 and the conductor wiring 28 are fixed while maintaining good electrical contact, and the LS
The mounting of the I-chip 3o onto the wiring board 27 is completed.

(発明が解決しようとする課題) 従来、上述のようにLSIチップ等の半導体素子の実装
は、突起電極26をその厚みより極めて薄いメツキレジ
スト25を用いて形成しているため(第3図)、狭ピッ
チ、多ピンのLSIチップの実装に対応させて、突起電
極の微細化を図る場合、以下に述べるような問題がある
(Problems to be Solved by the Invention) Conventionally, as mentioned above, when mounting semiconductor elements such as LSI chips, the protruding electrodes 26 are formed using the plating resist 25 which is much thinner than the protruding electrodes (FIG. 3). When attempting to miniaturize the protruding electrodes in response to the mounting of narrow-pitch, multi-pin LSI chips, there are problems as described below.

(a)突起電極底面の突起、つまりメツキレジストの開
孔部の寸法をも極めて小さくする必要があり、その構成
では、突起電極とバリアメタルとの密着度及び突起電極
の強度が低下する。
(a) It is necessary to make the size of the protrusion on the bottom surface of the protruding electrode, that is, the size of the opening in the plating resist, extremely small, and in this configuration, the degree of adhesion between the protruding electrode and the barrier metal and the strength of the protruding electrode decrease.

(b)突起電極形成時のメツキは横方向にも成長するか
ら、突起電極の厚みが薄くなり、そのため配線基板へめ
加圧時の変形度が不足し、LSIチップ内の突起電極の
厚みのバラツキや配線基板の平面度の不均衡が突起電極
の変形によっては吸収できず、電気的な接触不良を生ず
る。
(b) Since the plating during the formation of the protruding electrodes also grows in the lateral direction, the thickness of the protruding electrodes becomes thinner, resulting in insufficient deformation when pressurizing the wiring board, which reduces the thickness of the protruding electrodes in the LSI chip. Variations and imbalances in the flatness of the wiring board cannot be absorbed by deformation of the protruding electrodes, resulting in poor electrical contact.

(c)上記(b)の接触不良を回避するため、突起電極
の厚みを大きくすれば、突起電極の微細化が困難になり
、多ピン、狭ピッチの半導体装置には対応できず、例え
ば厚み10μmの時、突起電極のサイズは25μlが限
度となり、50μmピッチ以下のLSIへの対応は困難
である。
(c) In order to avoid the poor contact described in (b) above, if the thickness of the protruding electrode is increased, it will be difficult to miniaturize the protruding electrode, and it will not be possible to cope with semiconductor devices with a large number of pins or a narrow pitch. When the pitch is 10 μm, the size of the protruding electrode is limited to 25 μl, making it difficult to support LSIs with a pitch of 50 μm or less.

本発明は、上述のような問題を解決した半導体装置の実
装方法を提供することを目的とする。
An object of the present invention is to provide a method for mounting a semiconductor device that solves the above-mentioned problems.

(課題を解決するための手段) 本発明は上記の目的を、突起電極形成時のメツキレジス
トの厚みを突起電極の厚みと同程度とし、突起電極の厚
み方向の断面形状をほぼ四角形として、厚みよりもサイ
ズを小さくした突起電極によりLSIチップを配線基板
に接続するようにして達成する。
(Means for Solving the Problems) The present invention has achieved the above-mentioned objects by making the thickness of the plating resist at the time of forming the protruding electrodes to be approximately the same as the thickness of the protruding electrodes, and making the cross-sectional shape of the protruding electrodes in the thickness direction approximately square. This is achieved by connecting the LSI chip to the wiring board using protruding electrodes that are smaller in size.

(作 用) 以上のように構成する本発明によれば、突起電極の微細
化によってもメツキレジストの厚みが突起電極の厚みと
同程度であるから、従来のように横方向へのメツキの成
長がなく、したがって、厚みが大きく、サイズの小さい
突起電極が得られ、それによって配線基板へ半導体素子
としてのLSIチップを実装する場合の加圧による変形
度が大きくなり、したがって、電気的接続の不良を生ず
ることなく実装の高密度化が可能になる。
(Function) According to the present invention configured as described above, the thickness of the plating resist is approximately the same as the thickness of the protruding electrode even by miniaturization of the protruding electrode, so that the plating does not grow in the lateral direction as in the conventional method. Therefore, a protruding electrode with a large thickness and a small size can be obtained, which increases the degree of deformation due to pressure when mounting an LSI chip as a semiconductor element on a wiring board, and therefore leads to poor electrical connection. This makes it possible to increase the density of packaging without causing problems.

(実施例) 以下、本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例の突起電極の形成工程の断面
図、第2図はLSIチップの配線基板への実装方法を示
す図である。
FIG. 1 is a cross-sectional view of the process of forming a protruding electrode according to an embodiment of the present invention, and FIG. 2 is a diagram showing a method of mounting an LSI chip on a wiring board.

まず、第1図(a)に示したように、LSIチップを形
成する半導体ウェハ1の電極2を有する面に保護膜3を
設けて、Ti−Pd−Au、 Cr−Au等のバリアメ
タル4を蒸着によって形成させ、その後、フォトリソグ
ラフィー技術によりメツキレジスト5を形成する。バリ
アメタル4の厚みは通常。
First, as shown in FIG. 1(a), a protective film 3 is provided on the surface of a semiconductor wafer 1 on which an LSI chip is formed, and a barrier metal 4 such as Ti-Pd-Au, Cr-Au, etc. is provided. is formed by vapor deposition, and then a plating resist 5 is formed by photolithography. The thickness of barrier metal 4 is normal.

0.5μmないし1.0μ−程度であり、メツキレジス
ト5の厚みは10μmないし20μI程度、サイズは5
μ罹φないし15μ園φ程度である。
The thickness of the plating resist 5 is about 10 μm to 20 μI, and the size is about 5 μm to 1.0 μm.
It is approximately μ to 15μ φ.

メツキレジスト5は、粘度の高いポジレジスト等を使用
することにより、−回のスピンコードにより10μlな
いし20μmの厚さが得られる。なお、露光は密着露光
、投影露光その他で行い、使用する波長は3fr5nm
でも十分可能であり、露光量はメツキレジストの厚みが
10μI、サイズがlOμmφの時、300mJないし
450mJ程度である。
The plating resist 5 can have a thickness of 10 .mu.l to 20 .mu.m by using a positive resist with high viscosity or the like by -times of spin cord. In addition, exposure is performed by contact exposure, projection exposure, etc., and the wavelength used is 3fr5nm.
However, the exposure amount is about 300 mJ to 450 mJ when the thickness of the plating resist is 10 μI and the size is 10 μmφ.

次に、同図(b)に示すように、 Auを電気メツキし
て突起電極6を形成させるが、メツキはメツキレジスト
5の表面までとし、突起電極6の厚みをメツキレジスト
5に揃え、メツキの横方向への成長を防止して、突起電
極6の大形化を回避する。
Next, as shown in FIG. 6(b), Au is electroplated to form the protruding electrode 6, but the plating is done up to the surface of the plating resist 5, the thickness of the protruding electrode 6 is made equal to the plating resist 5, and the plating is done until the surface of the plating resist 5 is aligned. This prevents the protrusion electrode 6 from growing in the lateral direction, thereby avoiding an increase in the size of the protrusion electrode 6.

メツキ電流密度は0.03IIA/+a2で1Op11
の厚みを得るために約40分を要する。
Metering current density is 0.03IIA/+a2 and 1Op11
It takes about 40 minutes to obtain a thickness of .

次に、同図(c)に示すように、メツキレジスト5を除
去し、フォトエツチングして不要部めバリアメタル4を
除去して突起電極6を得る。
Next, as shown in FIG. 4C, the plating resist 5 is removed, and unnecessary portions of the barrier metal 4 are removed by photo-etching to obtain protruding electrodes 6.

この方法によれば、突起電極6は厚さ10μmの、3μ
園φないし5μ園φのものの形成が可能で、したがって
、5μIないし10IAmピッチの突起電極6を形成す
ることができ、多ピン、狭ピッチのLSIチップに十分
対応可能である。
According to this method, the protruding electrode 6 has a thickness of 10 μm and a thickness of 3 μm.
It is possible to form protruding electrodes 6 with a pitch of 5 μI to 10 IAm, and it is possible to form protruding electrodes 6 with a pitch of 5 μI to 10 IAm, which is sufficient for LSI chips with a large number of pins and a narrow pitch.

以上のように形成したLSIチップの配線基板への実装
方法を、第2図を参照して説明する。
A method for mounting the LSI chip formed as described above onto a wiring board will be explained with reference to FIG.

まず、第2図(a)のように、ガラス、セラミック等か
らなる配線基板7の、導体配線8を含む領域に絶縁性樹
脂9を塗布する。配線基板7の厚みはO,lonないし
2.0mm程度であり、導体配線8はCr−Au、 A
D、 I T O等で形成され、厚みは0.1μmない
しl060μI程度である。また、絶縁性樹脂9はアク
リル、エポキシ等の光硬化性または熱硬化性の樹脂が使
用され、その塗布はデイスペンサーあるいは印刷塗布等
により行う。
First, as shown in FIG. 2(a), an insulating resin 9 is applied to a region of the wiring board 7 made of glass, ceramic, etc., including the conductor wiring 8. As shown in FIG. The thickness of the wiring board 7 is about O.lon to 2.0 mm, and the conductor wiring 8 is made of Cr-Au, A
It is formed of D, ITO, etc., and has a thickness of about 0.1 μm to 1060 μI. Further, as the insulating resin 9, a photocurable or thermosetting resin such as acrylic or epoxy is used, and the coating is performed using a dispenser, printing, or the like.

次に、同図(b)のように、Au、Al1等で形成され
、底面寸法が厚みより小さい突起電極6を有するLSI
チップ10を、その突起電極6と導体配線8を一致させ
て、上記絶縁性樹脂9の塗布領域に搭載する。突起電極
6の厚みは10μmないし20μI程度で、寸法は5μ
園φないし15μmφ程度である。また、そのピッチは
10μmないし100μm程度である。
Next, as shown in the same figure (b), an LSI is formed of Au, Al1, etc. and has a protruding electrode 6 whose bottom dimension is smaller than its thickness.
The chip 10 is mounted on the area where the insulating resin 9 is applied, with the protruding electrodes 6 and the conductor wirings 8 aligned. The thickness of the protruding electrode 6 is about 10 μm to 20 μI, and the dimension is 5 μm.
The diameter is approximately 15 μm to 15 μm. Moreover, the pitch is about 10 μm to 100 μm.

次に、LSIチップ10を加圧ツール11により、電極
あたり約0.5gないし5g程度の力で加圧する。この
時、突起電極6と導体配線8の間に介在する絶縁性樹脂
9は押出され、突起電極6と導体配線8は電気的に接触
、接続される。なお、この時、突起電極6は寸法より厚
みが大きいため容易に変形して、その厚みのバラツキや
配線基板7の平面度の不均衡が吸収され、数百ピンある
いは数千ピンの接続、実装においても、容易に歩留りの
高い電気的接続が得られる。
Next, the LSI chip 10 is pressurized with a force of approximately 0.5 g to 5 g per electrode using the press tool 11. At this time, the insulating resin 9 interposed between the protruding electrode 6 and the conductor wiring 8 is extruded, and the protruding electrode 6 and the conductor wiring 8 are electrically contacted and connected. At this time, since the protruding electrode 6 is thicker than its dimensions, it is easily deformed, and variations in its thickness and imbalance in the flatness of the wiring board 7 are absorbed, allowing connection and mounting of hundreds or thousands of pins. Also, electrical connections with high yield can be easily obtained.

次に、上記加圧した状態で絶縁性樹脂9を、それがtJ
V線硬化性樹脂であれば、配線基板7の透明、不透明に
従って、その裏面またはT、SIチップ10の側面から
UV線を照射して硬化させる。この樹脂の硬化後、同図
(c)のように加圧ツール11を撤去すれば、突起電極
6と導体配線8が良好な接触を保って電気的に接続され
た、配線基板7にLSIチップ10が強固に固定されて
なる半導体装置が形成される。
Next, in the pressurized state, the insulating resin 9 is
If it is a V-ray curable resin, depending on whether the wiring board 7 is transparent or opaque, UV rays are irradiated from the back side of the wiring board 7 or from the side of the T or SI chip 10 to cure the resin. After the resin has hardened, if the pressure tool 11 is removed as shown in FIG. A semiconductor device in which 10 is firmly fixed is formed.

なお、絶縁性樹脂9によるLSIチップ】0の配線基板
7への固定は、T A B (Tape Automa
tedllondjng)であってもよい。
Note that the LSI chip 0 is fixed to the wiring board 7 by the insulating resin 9 using T A B (Tape Auto
tedllondjng).

(発明の効果) 以上、詳細に説明して明らかなように、本発明は、突起
電極を、そのIすみと同程度のメツキレジストを用いた
メツキにより形成していること、また、突起電極の厚み
方向の断面形状がほぼ四角形で、底面寸法よりも厚みの
方を大きくして実装するので、以下のような効果を有す
る。
(Effects of the Invention) As is clear from the above detailed explanation, the present invention provides that the protruding electrode is formed by plating using a plating resist of the same extent as the I corner of the protruding electrode. Since the cross-sectional shape in the thickness direction is approximately rectangular and the thickness is larger than the bottom dimension, it has the following effects.

(a)突起電極形成のメツキによる横方向への成長がな
いので、突起電極の厚みは十分I’Xい状態で微細な突
起電極が形成され、例えば10μmの厚さで3μIφな
いし5μlφの寸法のものが得られるから、10μmピ
ッチ以下の接続、実装が可能になり、従来例に比しほぼ
1桁高い高密度実装が可能になる。
(a) Since there is no lateral growth due to plating in the formation of protruding electrodes, fine protruding electrodes are formed with a sufficiently thin thickness of I'X, for example, with a thickness of 10 μm and dimensions of 3 μIφ to 5 μlφ. This makes it possible to connect and package at a pitch of 10 μm or less, making it possible to achieve high-density packaging that is approximately one order of magnitude higher than that of conventional methods.

(b)突起電極は、底面寸法より厚みが大きいため、L
SIチップの加圧時に容易に変形し、極めて小さい加重
で突起電極の寸法のバラツキ、あるいは配線基板の平面
度の不均衡が吸収されるから、LSIチップを損傷する
ことなく数百ないし数千ピンのLSIチップを接続、実
装させることが可能で、容易にLSIの高密度実装を行
うことができる。
(b) Since the protruding electrode is thicker than the bottom dimension, L
The SI chip is easily deformed when pressure is applied, and variations in the dimensions of protruding electrodes or imbalances in the flatness of the wiring board are absorbed with extremely small loads, so hundreds to thousands of pins can be formed without damaging the LSI chip. It is possible to connect and mount several LSI chips, and it is possible to easily perform high-density mounting of LSIs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の突起電極形成の工程を示す
断面図、第2図は一実施例のLSIチップ実装工程を示
す断面図、第3図は従来の突起電極形成工程を示す断面
図、第4図は従来のLSIチップ実装工程を説明する断
面図である。 1・・・半導体ウェハ、 2・・・電極、 3・・・保
護膜、 4・・・バリアメタル、 5・・・メツキレシ
ス1〜.6・・・突起電極、 7・・・配線基板、 8
・・・導体配線、 9・・・絶縁性樹脂、10・・・L
SIチップ、 11・・・加圧ツール。 竿 、4マ 図 特許出願人 松下電器産業株式会社
FIG. 1 is a sectional view showing the process of forming protruding electrodes according to one embodiment of the present invention, FIG. 2 is a sectional view showing the LSI chip mounting process of one embodiment, and FIG. 3 is a sectional view showing the conventional process of forming protruding electrodes. 4 is a cross-sectional view illustrating a conventional LSI chip mounting process. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... Electrode, 3... Protective film, 4... Barrier metal, 5... Metsukiresis 1~. 6... Projection electrode, 7... Wiring board, 8
...Conductor wiring, 9...Insulating resin, 10...L
SI chip, 11...pressure tool. Rod, 4-ma diagram patent applicant Matsushita Electric Industrial Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] (1)導体配線を有する絶縁性基板と、一辺または直径
が厚みより小さい、ほぼ四角形の厚み方向の断面を有す
る突起電極を設けた半導体素子とを、上記導体配線と突
起電極とを一致させて、それらの間が電気的に接触接続
されるように絶縁性樹脂により固着されていることを特
徴とする半導体装置。
(1) An insulating substrate having a conductive wiring and a semiconductor element provided with a protruding electrode having an approximately rectangular cross section in the thickness direction with one side or diameter smaller than the thickness, by aligning the conductive wiring and the protruding electrode. , a semiconductor device characterized in that they are fixed with an insulating resin so that they are electrically connected.
(2)突起電極が、ほぼ四角形の厚み方向の断面を有し
、かつ断面の一辺の長さまたは直径が厚みより小さいこ
とを特徴とする請求項(1)記載の半導体装置。
(2) The semiconductor device according to claim (1), wherein the protruding electrode has a substantially rectangular cross section in the thickness direction, and the length or diameter of one side of the cross section is smaller than the thickness.
(3)配線基板に有する導体配線の部分に絶縁性樹脂を
塗布する工程と、一辺または直径が厚みより小さい、ほ
ぼ四角形の厚み方向の断面を有する突起電極を設けた半
導体素子を、その突起電極を上記配線基板に塗布した絶
縁性樹脂領域の導体配線に一致させて圧着する工程と、
前記絶縁性樹脂を硬化させ、半導体素子を配線基板に固
着するとともに、上記導体配線と突起電極とを電気的に
接続する工程とを含むことを特徴とする半導体装置の実
装方法。
(3) The process of applying insulating resin to the conductor wiring portion of the wiring board, and the step of applying an insulating resin to the conductor wiring portion of the wiring board, and attaching the semiconductor element with a protruding electrode having an approximately rectangular cross section in the thickness direction with one side or diameter smaller than the thickness. a step of matching and crimping the conductor wiring in the insulating resin area applied to the wiring board;
A method for mounting a semiconductor device, comprising the steps of curing the insulating resin, fixing the semiconductor element to the wiring board, and electrically connecting the conductor wiring and the protruding electrode.
JP26164988A 1988-10-19 1988-10-19 Semiconductor device and its mounting Pending JPH02110948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26164988A JPH02110948A (en) 1988-10-19 1988-10-19 Semiconductor device and its mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26164988A JPH02110948A (en) 1988-10-19 1988-10-19 Semiconductor device and its mounting

Publications (1)

Publication Number Publication Date
JPH02110948A true JPH02110948A (en) 1990-04-24

Family

ID=17364840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26164988A Pending JPH02110948A (en) 1988-10-19 1988-10-19 Semiconductor device and its mounting

Country Status (1)

Country Link
JP (1) JPH02110948A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525422B1 (en) 1997-01-20 2003-02-25 Sharp Kabushiki Kaisha Semiconductor device including bump electrodes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197857A (en) * 1982-05-14 1983-11-17 Hitachi Ltd Semiconductor device and manufacture thereof
JPS60262430A (en) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197857A (en) * 1982-05-14 1983-11-17 Hitachi Ltd Semiconductor device and manufacture thereof
JPS60262430A (en) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525422B1 (en) 1997-01-20 2003-02-25 Sharp Kabushiki Kaisha Semiconductor device including bump electrodes
US6933607B2 (en) 1997-01-20 2005-08-23 Sharp Kabushiki Kaisha Semiconductor device with bumps on electrode pads oriented in given direction
US7005741B2 (en) 1997-01-20 2006-02-28 Sharp Kabushiki Kaisha Liquid crystal display device and/or circuit substrate including bump electrodes and electrode pads

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