JPH01500318A - Time-limited programmable data protection system for programmable logic devices - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] For programmable logic devices Time-limited programmable data protection system (technical field) The present invention relates to a programmable logic device (PLD), and more specifically, to a programmable logic device (PLD). Programmed data, such as data that defines the architecture, is illegally modified. Concerning techniques to prevent this from occurring.

(Background of the invention) PLDs allow users to turn on-circuit (on-circuit) specific functions for specific applications. - circuit) for an application through a fuse or switch. constructing a second resilient logical architecture that performs a specific function; Can be done. You can easily purchase this PLD just like a normal logic gate device. In addition, it can also be made to order like a gate element. PLD Typically, many fuses or switches are used in manufacturing and programming. To facilitate ramming, these fuses or switches may be one or To Ma) Ricks, also known as Andare or Orare. It is assembled. The second problem with using conventional PLDs is system design. After devising a formula that explains how to implement it with the hardware, the The formula is input into the PLD programming device. And then program When you put a PLD into the device that does not have a disconnecting the corresponding fuse to execute the desired logic function in the system; Alternatively, it outputs a signal to set the corresponding switch.

To prevent reading of data programmed into the device's AND array, Polar PLI), MOS F, PROIA PLD with security fuse circuit It is known to provide Especially in bipolar devices, the switch element is It uses a used link (fused 1 ink) and cannot be erased once it is disconnected. do not have. Cells used in PLDs that can be erased with ultraviolet light can be erased, but this If you do that, the fuse will also be erased.

It uses electrically erasable cells and is compatible with programmable arrays and architecture. For PLDs that can be adapted to multiple specific logic devices with U.S.A. related to the invention titled ``Improved Programmable Logic Device'' assigned to the assignee of Ming Dynasty. It is disclosed in National Patent Application No. 707.662, and the device disclosed therein is , it can replace other PLDs due to its versatility.

For reference, the name of the invention is ``Programmable Data Machine for Programmable Logic Devices''. For example, the security circuit disclosed in the patent application for “Secure Protection Circuit” Manufacturers of reprogrammable logic devices using erasable cells may The device can be adapted to the architecture and the user can Protect your device by preventing the modification of protected data such as chat data. It is possible to prevent the architecture from being modified. However, in some applications, Even if security fuses are set by the vendor, the device architecture is not defined by the user. It can be programmed or, if the manufacturer does not set fuses, the Users cannot repeatedly modify the architecture or protected data. It may be desirable to provide a programmable PLD with a security circuit with specifications that allow Ru.

Therefore, it can be configured even after the device has been manufactured, and the user can only configure the logic once. You can program the logic configuration, and then A programmable architecture protection module for programmable PLDs that cannot be modified. It is an advance in technology that a high-speed circuit is now provided.

Furthermore, if enabled during device manufacturing, users of Pl,D can The data can be programmed, but then the protected data It cannot be recreated and unless enabled, it can be repeated many times. A time-limited programmable architecture that allows data to be reprogrammed repeatedly. It is desirable to have a built-in data protection circuit.

(Disclosure of invention) According to the present invention, a programmable logic device is configured with a predetermined number of electrically erasable cells. By doing so, the aforementioned advantages can be realized. The protective fuse system is programmed Provided in the Mable Logic Device, memory cells can be programmed only once. It can be fixed. This system activates the fuse in response to a protective fuse actuation signal. It includes an enable circuit that outputs an enable signal. Decoder in memory cell Since the circuit is connected, the cell to be programmed is selected in response to the cell selection signal. is selected. A protection fuse responsive to a fuse enable signal and a cell selection signal. A noise circuit is also included in the system. This protection fuse circuit Programming of a storage cell only once after is set, i.e., enabled. However, after that, the cell selection function by the decoder is disabled and the cell selection function is disabled. is connected to the decoder circuit so that no

(Brief explanation of the drawing) The foregoing and other advantages of the present invention will be apparent from the preferred embodiments illustrated in the accompanying drawings. It will become clear from the detailed description of the example.

FIG. 1A shows a programmable cable incorporating the architectural protection fuse of the present invention. Figure 1B is a block diagram showing the PLD (program logic device) shown in Figure 1A. Schematic diagram of a typical output logic macrocell with an output logic circuit (mubble logic device) , Figure 2 shows the limits for protecting selected programmable cells in a PLD. A block diagram of the programmable protection fuse system, Figure 3, is a block diagram of the system shown in Figure 2. Schematic diagram of the protective fuse enable circuit consisting of Figure 4 is a partial schematic diagram of the protective fuse circuit of the system of Figure 2; Figures 5 and 6; is a schematic diagram of each row decoder logic used in the preferred embodiment. .

(Example) The present invention is a novel protection fuse system for programmable logic devices. . In the following description, the present invention will be described with reference to logic circuits and blocks of devices so that the present invention may be easily understood. The explanation will be given using specific examples such as lock circuits, but those skilled in the art will be able to understand It is clear that the present invention can be practiced without giving specific examples. On the other hand, the present invention In order to avoid complicating the explanation, we will refer to well-known circuits and devices. Therefore, I will not explain this in detail.

FIG. 1A shows a partial circuit block of a PLD incorporating a protective fuse circuit according to the present invention. A diagram is shown. The embodiments disclosed herein define the logical architecture of a PLD. Although intended to protect programmable data, the present invention generally protects programmable data. To protect setting data in PLD using grammable data cells. It is clear that it is applicable.

The PLD shown in Figure 1A is assembled into a centipede-shaped package using CMO3 manufacturing technology. It is made up of. This PLD has multiple electrically programmable cells arranged in rows and columns. It is composed of an AND matrix 10 which is . Cell columns (not shown) form a product term (without an inverter) and ) constitutes an AND logic combination of signals from the row input lines that are input to Ru. Place a cell at the intersection of each row input line and each column, that is, the product term, and This selectively connects any row input line to the corresponding column input line. Out The power logic circuit 40 outputs the product term from the output bin as the logic output of the device. be. Therefore, the user can program cells or bits in the user-configured portion of array 10. By programming, any input signal results in a logical output of the device. You can decide on the water. In that sense, it is possible to program AND arrays. This is known in the art, for example, as described in the book rPAL HandbookJ. (Published by Monolithic Memo-ries, 1883. 5 pages (Chapter 1, page 11).

In the detailed description of the present invention, the logical architecture of the illustrated PLr) is The state of the data bits stored in the architecture row and the rXORj row of the array It is decided by. The bits in the XOR row invert the output lines of the PLD. It has the function of outputting either an inverted logic output or a non-inverted logic output. Ru. Therefore, if there are 8 output lines of the PLD, the 8 bits of the XOR row are It will be determined whether the inverter of each output line is activated. This implementation In the example, there are 74 data bits in the architecture row, and the remaining output circuit addresses are - architecture, that is, the logic output bus and mechanism on which the output circuit 40 of the PLD is constructed. This will determine the architecture that defines the functionality.

For example, in FIG. 1B, an output logic macrocell (OLMC) 5 including an output circuit 40 0 is shown schematically. In this example, eight product terms are supplied to cell 40. However, in circuit 40, this is increased by 8 times, and 64 pieces are generated from AND array 10. A product term is now provided. In normal user mode, the 8-bit 52, the outputs of the eight sense amplifiers corresponding to the eight product terms are set to 0IJIC. 50. The output of OLMC50 is brought out on pin 54, but the combination (asynchronous) state or consistent (registered) (synchronous) state. sets the output signal to active high or active low, respectively. Both The communication enable signal OE is connected to all synchronous outputs of the device or A product term can also be used to output an output enable control output.

The configuration requirements for the output circuit of the PLD are determined by the architecture stored in the architecture row. control by programming bits in the character control word. architect Control pin 1 - Output is always on/off by ACO and 8 AC1 bits (as input) and with a common OE term, or individually from the product term. It is controlled in three states (tristate). Also, the architecture control bits are , via multiplexer 56, determines the source of the array feedback ring. In addition, through another multiplexer 60, either the combined output or the matched output can be selected. Choose one. The SYN bit indicates whether the PLD has a matching output function or not. Or, decide if you only have combinatorial output capabilities. 8 pieces The XOR bit determines the polarity of each device's output.

The action of OLMC is obvious to those skilled in the art, so it will not be explained here. It shall not be detailed.

Having explained the types and locations of data to be protected, the present invention Although limited to protecting architectural data at specific locations within D It is not an example, so it is just an example.

In a preferred embodiment, the matrix of PLD data cells are electrically erasable floating It consists of a gate transistor. These floating gate transistors Depletion mode and enhancement mode, which become conductive and non-conductive, respectively, during diagnostics. mode. Data cells are floating gates) and lunges In addition to stars, cells that are opened and closed by appropriate input lines to select specific cells. Equipped with a select transistor. The memory cells in each row are select the cells in a particular row and set the gate of each cell's floating gate transistor. Programming is completed by applying appropriate programming voltages to the gate, source, and drain. The corresponding floating gate transistor is placed into depletion mode according to the state of the signal data. This can be set by setting it to mode (continuous during diagnosis). Therefore, selected Only certain cells in a row are selected for programming. If so, the state is set to "conduction during diagnosis". These cells are the user The user specifies programming data to create a floating gate during programming mode. The selection is made by determining the level of voltage applied to the transistor. This hand The sequence is repeated for each active row of array 10.

In such PLDs, high voltage (20 volts) signals are applied to certain bins of the device. Applying EDT puts the device into edit mode. Edit mode, the row decoder for each row of matrix 10 is activated and If not, reconfigure the device to pin functionality. Become. In edit mode, the instrument's six input bin signals are A 6-bit word RAG (row address gate) that specifies the address is defined. Ru. Thus, for example, the row decoder 20.30 (FIG. 1) may decipher the specific RAG word that selects each row. To each row decoder The inputs are the RAG word and each user-accessible memory cell in the array. The CLR signal activated by the user when clearing or deleting the file position. It will be. Another input to the XOR row decoder 20 is when the user Protection fuse activated when protecting AND array cell and XOR line There is a USF signal, which is a signal issued by the circuit.

Architectural protection fuse 35 indicates that the protection fuse is enabled during manufacturing. If the user has access to the architecture to program the architecture bits It is provided to allow one-time access to the architecture row. made If the manufacturer did not set the protective fuses, the user may Programming can be repeated repeatedly. This kind of architecture The configuration bits determine the configuration of the logic output circuit 40 and the configuration of the logic output circuit 40. and its relationship to the index matrix. Therefore, the architecture If output VSF of protection fuse 35 is active, for programming The ability of decoder 30 to select architectural rows is disabled. has been done.

A circuit block diagram of the time-limited programmable protection fuse system is shown in FIG. child The fuse system is protected from protection if the system was enabled at manufacture. programmed cell location, and then the cell will never be programmed again. Allows users to perform a one-time programming cycle to prevent It has become.

The advantage of this fuse circuit, which can be programmed for a limited time, is that the programmable logic device manufacturers can build their devices to be user-programmable. Once there, the user can program the desired logic configuration once and for all. and can then be loaded into the logical configuration so programmed. You can keep the Also, as a manufacturer, you should set up a protective fuse. Or, you can decide for yourself whether it is better not to set it, and you have decided not to set it. This allows users to repeatedly change the configuration data that defines the logical configuration. Wear.

In FIG. 2, the protection fuse 35 is connected to a protection fuse enable circuit 100, It is composed of a protection fuse circuit 300. Protection fuse enable circuit 10 0 supplies the protection fuse enable signal SFE to the protection fuse circuit 300. Thus, the protection fuse circuit 300 is enabled. Then the protective fuse circuit 300 is a protection fuse for the decoder 30 containing architecture data in this embodiment. supply the signal VSF.

Protection fuse enable circuit An example of this protection fuse enable (SFE) circuit 100 is schematically shown in FIG. Shown schematically. PLDs are explained as being assembled using CMOS manufacturing technology. However, the SF2 circuit uses NMOS transistors 109.111.113.177 , ]19.12]. These transistors are turned on (t urn-on) Doped with arsenic as an impurity so that the gate voltage threshold is negative. It is what was done.

Transistors 109, 111, 113 and inverter 107 are connected to node 106. A connected high impedance voltage pull-up circuit 110 is configured.

This pull-up circuit 110 operates at node 106 when transistor 105 is non-conductive. is pulled up to the potential of node 112 (20 volts), but node 106 is grounded. , that is, when transistor 105 conducts, the current 20 volts to node 106 is applied. It is designed to cut off the voltage supply. Transistor 117.119.121 and inverter 115 are similar voltage pull-up circuits 1 connected to notebook 116. It consists of 16. However, when node 122 is grounded, pull-up circuit 1 16, the node potential cannot be made higher than the ground potential. Plua like this Since the top-up circuit is well known, it will not be described in detail here.

Transistor 125 is a data storage element of SFE circuit 100 and is a floating gate transistor. It is a type N-channel field effect transistor. Regarding floating gate transistors It is well known as a semiconductor device, and its characteristics are described in 1. S, M, published by John Wiley & 5ons in 969 rPhysics or Sem1conductor Device by Sze It is detailed in Chapter 10 of s:. Floating gate transistor in this example The transistor operates in either enhancement mode or deblation mode. The well-known Fowler-Nordheim tunnel effect was used to determine the cropping pattern. is now used. The floating gate has an acid Since it is isolated by the thickness of the chemical source 1 (100 people), as long as there is a sufficient electric field, Charge flows between the drain and the floating gate.

As discussed below, floating gate transistor 125 is erased or enhanced. When set to SMOTE (non-conducting during diagnostics), the output of the protective fuse enable circuit The power SFE goes high and the l’LD architecture row data is repeatedly programmed. You will be able to ram. On the other hand, floating gate transistors When set to fuse (conducting during diagnosis), the output SF of the protection fuse enable circuit With E going low, protection fuse circuit 300 is enabled.

The input signals to the NOR gate 101 are CLF, EDT, SFE signals, and S This is an output signal from the inverter 151 of the FE circuit 100. to these gates If all input signals are low, the output signal from NOR gate 101 will be high.

The output of NOR gate 101 at node 102 is connected to one input of NOR gate 103. input to the power terminal. This NOR gate 103 also receives input from node rP21J. A signal is provided to the other terminal. This node uses the device's gui package (d The wafer probe is used only before performing device die packaging. Wafer probe pad (%afer probe) d) protected from

As will be described later, the node P21 turns off the transistor 105 and turns the transistor 105 off. Override to make the node 106 high level by using the amplifier circuit 1.10. This is what causes the action to take place. P2] is forced high, a signal appears at node 104. Since the output of the NOR gate that is The action of the gate causes node 106 to go high.

If node P21 is low, NOR gate 103 outputs the output of NOR gate 1.01. This results in the signal at node 102 being inverted. This allows logical or Since the action has been performed, if P21 is low, the state of node 104 is It is a logical OR of CLR, EDT, and SFE.

The output 104 of gate 103 is applied to the gate of transistor 105. and if its output 104 is high, it will cause transistors 125 and 113 to conduct. I'll have to let you through. Transistor 125.11 in pull-up circuit 110 Node 106, which is connected to the gate of No. 3, is then grounded.

If the output of gate 1-103 is low, transistor 105 is non-conducting and the node Node 106 is never grounded, so the potential at node 106 is The pull-up circuit 110 pulls it up to +20 volts.

When transistor 105 is conductive, pull-up circuit 116 110 and node 106.1 Similarly, for node 122, It works. However, in a circuit where node 122 is grounded, transistor 123 , ]25.127 and the second circuit via transistor 131. There are two types.

Transistor 123 is connected to act as a diode and is electrically erased. In order to configure the freely programmable data storage cell 124, a transistor '25 and are used together. The state of the memory cell 124 is diagnosed by the inverter 115. This is done when node 106 is grounded (transistor 105 is conductive) and transistor resistor 127 is conductive (signal ASG applied to its gate is +2.5 volts) , transistor 131 becomes non-conductive (its gate is grounded), then . The state of node 122 changes depending on the state of storage cell 124. In other words, When the floating gate transistor 125 is in the enhanced mode erased, the transistor Transistor 125 becomes non-conductive. At that time, node 122 is connected to pull-up circuit 1 1.6 causes the output of inverter 115 at node 133 to go high. The force becomes low.

On the other hand, if transistor 125 is set to depletion mode, The gate of the transistor is grounded and conductive. Therefore, if transistor 127 also becomes conductive, , node 122 goes low, and in such a state, the input at node 133 The output of inverter 115 goes high.

Node 133 connected to the output of inverter 115 is connected to Connected to latch 140. On the other hand, the output of the latch 140 is the output of the SFE circuit. a force signal SFE, which is inverted by an inverter 151 to become SFE; It is input to the Noah gate 101. Therefore, if EDT becomes high, signal SFE becomes latched in place, the state of node 133 as long as EDT is high. It does not depend on the state of node 133, no matter how it changes thereafter.

protection fuse circuit A schematic diagram of the protection fuse circuit 300 is shown in FIG. This circuit 300 is a floating game A voltage source consisting of an N-channel transistor 325 and a select transistor 323 It is composed of electrically erasable cells 324. Node 322 of cell 324 has a signal It is grounded via a transistor 331 that is opened and closed by SFH. This protection The fuse circuit 300 includes transistors 317, 319, 321 and an inverter 3. A high voltage pull-up circuit 316 consisting of circuit 11 of FIG. It works in the same way as described for 6.

The output of inverter 315 at node 333 is provided to latch 340, which The output from circuit 340 is provided to one terminal of NOR gate 345. noah gate 34 The other input terminal of 5 is connected to the signals SFE, P (if the device is not in edit mode) active) is entered.

The output VSF from the NOR gate 345 constitutes the output signal of the protection fuse circuit 300. has been completed.

Cells 324 are arranged throughout array 10 to form a programmable array. This figure shows only a portion of what can be similarly provided.

Circuit 300 operates as follows. The cell 324 is the select transistor 32 A high signal is applied to the gate of 3, i.e., the signal ARC) I l? 01 is logical If it is at the correct level, it will be selected. Transistor 325 has a voltage applied to its gate. Inter-rogate with nominal +2.5 volt signal MCGI It will be done. Therefore, when cell 323 is "selected" and transistor 325 is diagnosed, , transistor 323 becomes conductive. Transistor 325 is in depletion mode. It is conductive when in mode, but becomes non-conductive when erased to enhance mode.

When the device is in normal user mode, signal ASG is nominally +2°5 volts; The transistor 327 is turned on. The potential at node 322 is It changes depending on the state of the transistor 325 at the time. For example, transistor 325 is conductive, node 322 is at ground potential, and the cell at node 322 The sensed output of becomes high. On the other hand, transistors If terminal 325 is non-conducting, node 322 will be pulled up by the action of pull-up circuit 326. , is pulled high and the sense output of cell 324 at node 323 is becomes low.

Cell 324 is selected for programming at the same time that the architecture row is selected. selected. In other words, when the signal ARCHROW goes high, the select transistor 323 becomes conductive and connects the gate of floating gate transistor 325. The MCGI signal connected to the terminal is grounded. The signal ASG is also grounded and the gate transistor The resistor 327 is made non-conductive.

In such a state, the potential at node 322 becomes transitional when signal SFE is high. As long as the star 331 is conductive, it remains at the ground level. This allows the transistor This prevents data 325 from being set to deblation mode.

When the SFE circuit is enabled by programming the SFE bit, , signal SFE goes low, opening transistor 331. This allows the When the architecture row is selected for next programming, transistor 325 can now be set to depletion mode. So select transistor 323 is pulled to a high level of +20 volts, transistor 327.33 1 is opened and signal MCGI is grounded, the potential at node 322 is It rises due to the pull-up action of resistors 319 and 321. The inverter 315 , flips low as the potential at node 122 increases, thus transistor 31 7 is opened, the potential at node 322 rises to +20 volts. transis The gate of 325 is grounded and the drain is 20 volts to enhance mode. voltage threshold of transistor 323, i.e. approximately 18 volts. For example, electrons flow from the floating gate to the drain and deplace transistor 325. mode. In this mode, cell 324 has 2.5 If diagnosed by volt signal MCGI, continuity is detected by inverter 315. When this happens, the node 322 is grounded. Input of inverter 315 is grounded When it reaches 1 novel, its output goes high.

protection fuse row decoder Row decoder 145, which selects the protection fuse enable function, is shown in FIG. Ru. This decoder 145 basically performs OR decoding according to the RAG row selection signal. (the action of the OR-AND compound gate 133 in FIG. 3) It is something. The deblation transistor 137 has a node connected to the transistor 13. 6 and the transistor 135a=135f when not grounded, the node A voltage pull-up effect is performed on 135g. The inverter 138 is 35g, and the node 132 is connected to the transistor 131 (first It is connected to the gate in Figure 3). Therefore, if you select the SFE line, the transistor The transistors 135a and 135r are open, and the transistor 137 is connected to the node 135g. The voltage at the node 132 is raised, and the node 132 becomes low level accordingly. Opposition If the SFE row is not selected and EDT is high, node 135g is grounded. However, node 132 goes high, thus transistor 131 is closed.

architecture row decoder A schematic diagram of the architectural row decoder 30 is shown in FIG. This decoder 30 is Decipher the row address gate (RAG) row selection signal and extract the protected information. In other words, in this example, the row containing architecture data is selected. Ru. Generally, selecting rows is done by programming the data in a particular row. , or search is done to confirm. Therefore, this decoder 30 has RAG A NOR operation is performed depending on the word and the EDT signal. Transistor 2 (15, 21 0 and depletion transistor 215.220.225 are high impedance This constitutes a high voltage pull-up circuit. Therefore, node 250 is grounded. If not, the potential at node 250 will be reduced by the action of this high voltage pull-up circuit. , raised to a high level.

If the device is in edit mode, the signal EDT is high or Register 247 is closed. "Bulk erase" CLR is low and therefore transistor 246 is open. and node 250 has +20 regardless of the RAG address. being pulled up by the bolt. Each transistor 240-245 is If there is an appropriate RAG word that selects the target row, it is opened so that node 250 There is no room for grounding through the transistors 240 to 245, and the transistor 248 does not close, node 250 remains pulled high.

Node 250 is a terminal to which the output of the row decoder is output, and is used to record the architecture row. Since it is connected to each select transistor consisting of memory cells, programming When searching or confirming a search, each memory cell in that row is selected.

If the potential at node 250 is high, transistor 249 will close, thus Floating tracks in a rumble cell matrix (e.g. cell 324 shown in FIG. 4) A node MCG11 . connected to the gate of a storage element made of a transistor. :MCGφ is Supplied. The MCGφ signal is set to an appropriate voltage level when diagnosing the state of the user array cell. bell (↑2.5 volts), so if there is a high signal at node 250, the CG Increasing I to +20 volts erases the memory cells of the architectural row to be erased. You can choose.

If VSF is low, i.e., if the architecture protection fuse is cleared, the decode Transistor 248 of reader 30 is open, so node 250 is high if selected. It becomes a. However, if the protection fuse is set, VSF will go high and the Register 248 is closed. In this case, node 250 is connected to transistor 24 8.247, and regardless of RAG word memorial service, Prevents storage cells in the architecture row from being selected.

When the PLD is in a bulk erase cycle, cLR goes low and transistor 24 6 is developed. At this time, node 250 has VSF high. If it is, it is pulled high regardless of the state of the RAG word. deer However, if the protection fuse signal VSF is high, the architecture line To initialize the state of the SFE circuit, cancel the bulk erase cycle of the PLD chip. The wafer is packaged once during the wafer probe stage of chip assembly. For example, node P21 is forced high from an inaccessible wafer pad.

The NOR gate 103 outputs a high output if both of its inputs are low. Therefore, one input (P21) to this Noah gate 103 is forced. when it is pulled high, its output goes low and the gate of transistor 105 , it becomes low and becomes non-conductive.

If transistor 105 is non-conductive, node 106 is never grounded and the front Since the voltage is raised to the above potential, the output of the inverter 107 is switched to low. As a result, transistor 109 is opened. On the other hand, transistor 111 is closed and transistor 111 is closed. transistors 111 and 113 are also closed, and the node connected to the gate of transistor 125 is closed. The voltage on node 106 increases to 120 volts.

In this situation, and the device is in edit mode, cell 124 floating gate transistor 125 is "erased" so that transistor 127.13 By closing 1, the enhancement mode is set. of transistor 127 The ASF signal at the gate is at 5 volts, closing transistor 127. has been completed. In edit mode, the EDT signal is high; in this case, The protection fuse row is not selected and therefore transistor 13 is not selected as described above. Since the gate of 1 is high, transistor 131 is closed. transis The drain and source of transistor 125 connect transistors 127 and 131, which are conducting. If the gate of the transistor is +20 volts, Electrons flow from the drain line to the floating gate, thus strongly enhancing the transistor. Set to mode. In this case, the positive gate voltage required to close the transistor is The pressure threshold is at least 6-7 volts. The gate of transistor 125 is set during diagnosis. Since it is grounded, the transistor is non-conducting. On the other hand, node 12 2 (high, the output of inverter 115 at node 133 is low .

The SFE signal and the output of inverter 118 are high.

Fuse circuit operation The architecture protection fuse circuit addresses the protection fuse row and cells 125 setting the transistor 124 in the deceleration mode (conducting during diagnosis). It can be activated by When the protection fuse row is selected, the The output of the decoder circuit is low. This opens the transistor 131. , therefore, there is no room for node 122 to be grounded via transistor 131. Ru.

To set transistor 25 to depletion mode, transistor 10 5 is closed to drive node 106 low. Pulling node 106 low is caused by PL After packaging D, I could no longer access Bad P21. It can only be done later. The EDT signal in edit mode is low. On the other hand, SF The E signal remains low until circuit 100 is enabled. However, C The LR signal is low only during a clear cycle by the user; He's high outside. If both inputs to NOR gate 103 are low, the Transistor 105 is closed, and the gate of transistor 125 is grounded. It is. Similarly, the signal ASG goes low and the transistor! Opened 27 There is.

Under these conditions, the potential at node 122 is the same as transistor 119 . It is rising due to the pull-up effect of 121. Along with this, the inverter 115 switches low, transistor 117 opens, thus reducing the voltage at node 122. The voltage becomes 120 volts. The gate of transistor 125 is grounded, and the drain is grounded. , → 20 volts minus the voltage threshold when the device is in enhanced mode. voltage, about 18 volts, electrons flow from the floating gate to the drain. , sets the transistor to depletion mode. You are now in normal user mode. If so, the transistor has its gate grounded and the inverter 115 When selected by , it becomes conductive, pulling node 122 low. On the other hand, inverter 1 ]5's input is low, the inverter provides a high output.

The output of inverter 115 is supplied to latch 140 via inverter 118. Therefore, after storing the input state, the latch 140 stores the EDT state in the edit mode. When the signal becomes clear, it indicates the input state and outputs r2 output SFE.

Conversely, if EDT is low, the latch is transparent. This latch When the disconnection voltage changes to the programming condition, SF in edit mode This prevents the E signal from changing.

If the SFE signal is high, regenerative cancellation (regenerat 1v), which will be described later, will occur. eearse) and enable the protection fuse circuit 300. SFE Once enabled, circuit 100 cannot be erased.

Action of the protective fuse system The protective fuse stem 300 operates as follows. That is, SFE enable Assume that the circuit 100 operates and outputs a low level signal SFE. Then, S FE signal) - Since transistor 331 becomes non-conductive, node 322 is released. will be sourced. In this state, cell 324 indicates that the architecture row has been selected. In other words, the output of the row decoder 30, ARCHROW (no. 8), goes high. Then, the signal MCGI that drives the gate of the floating gate tranostor 325 is programmed. Becomes conductive when grounded during ramming. The cell 324 is once in a conductive state (diagnosis When set to node 341 (output of node 340), the state of the cell's data is set to The output of the NOR gate 345 (signal VSF) becomes high, and the fifth Transistor 248 of row decoder 30 shown becomes conductive. transis When the gate of gate 248 is driven high, signal ARCHRoW is pulled low. and thus the cells in the architecture row will not be programmed again. This prevents the device architecture from being altered.

Elimination of regenerative SFE after assembly Once the SFE circuit is “erased”, the PLD architecture is created from the original logic state. can be configured or reconfigured.

iii losses from the floating gate enable the protection fuse circuit 300 Therefore, the "degenerate concave state" of the SFE circuit becomes worse. ) L.

It is important to avoid this. This is achieved with the regenerative elimination function after assembly. It is possible. This regeneration elimination function is performed when all inputs to the NOR gate 101 of the circuit 100 are low. , that is, SFE goes low (erased) and the device is in "clear" mode ( SFE = CIJ = 0), the transistor 131 is closed, and k (i.e., protection fuse row is not selected).

When these conditions are met, node 102 goes high, opening transistor 105. This causes node 106 to go high and reach +20 volts, so The cell is erased to its floating gate potential in enhanced mode. This regeneration erasure is , each time the user selects the clear function of the device, and SFE is not high. sometimes done. PLI), when the user performs a "bulk erase" cycle (at this time, E Both DT and CLR are low. ) to erase all address locations in memory. It is now possible to do so. When performing regenerative erase, SFE is high and gate 10 Since the output of 1 remains low, the programmed cell 124 of the SFE circuit will not be deleted. That is, if both inputs to gate 103 are low For example, its output goes high, closing transistor 105 and closing the floating gate. The gate of the gate transistor 125 is grounded. Turn on the transistor To erase to hance mode, the gate must be brought to a high level programming voltage. The memory cells are never erased because they need to be removed. Therefore, regenerative consumption When the erase function is used, it only affects the erased cells of the SFE circuit. Ru.

reduced diagnostic voltage Floating gate of transistor 125 brought about by packaging in high temperature environment. i! A countermeasure against load loss is to increase the continuous output voltage of the memory cell 124, that is, the diagnostic voltage. Obtained by decreasing. Generally, cells 124 of the SFE circuit are connected to the PLD. When packaged, the cells of the SFE circuit are erased. For example, the manufacturer may allow SFE circuit 100 to be enabled after assembly. SFE Transistor 125 of storage cell 124 of circuit 100 is configured to read from this type of storage cell. While a nominal +2.5 volt gate potential is used to If the gate potential of is at ground potential, it is read out, ie, diagnosed. transition Since the charge loss from the floating gate of star 125 occurs during the enhancement mode, The required gate voltage threshold required to close the transistor is reduced. Therefore, Decreasing the cell diagnostic voltage from -2.5 volts to 0 volts reduces charge loss due to high temperature. It allows you to have some leeway in the face of loss.

If you package the PLD and then enable the SFE circuit 100, the SF Cell 124 of the E circuit cannot be erased. In other words, the logic state of the circuit When the fuse is enabled, i.e., when SFE is low, the memory The transistor 125 is not erased. This is the effect of Noah Gate This is because the state of the input to the gate is as described above. follow Thus, the protective fuse in the preferred embodiment , protected data can be reprogrammed only once. Ru.

Up to this point, the protected information in the PLD has been selectively printed only once. A new protection circuit that can be programmed was explained.

Of course, I would like to make it possible to program protected data again. It is possible for the PLD manufacturer to determine whether the PLI (PLI) is come. In addition, it is possible to use and arrays that are not protected by the protection system. The cell can be reprogrammed even if the protection system is activated.

The embodiments described above are merely illustrative of specific embodiments illustrating the principles of the invention. stomach. Other variations will readily occur to those skilled in the art without departing from the scope of the invention. This is something that can be considered.

F/G, 4 (V

Claims (1)

[Claims] 1. Multiple input lines through which input signals are sent and output logic circuits that provide logical outputs of the device. an electrically programmable circuit connected between said input line and the output logic circuit; for each state of said cell of the first group, which input signal is connected to the logic of the device. to the array that is supposed to determine which output will result, Its state is adapted to determine the logic architecture of said output logic circuit. a cell array also comprising a second group of cells and time-limited programming of said second group of cells; consisting of a protective fuse system that selectively allows The protective fuse system includes: An enabler that outputs a protective fuse enable signal in response to a protective fuse activation signal. bull circuit and Programs to a state determined by programming data in response to a cell selection signal. selection means for selecting the second group of cells for merging; responsive to a front leg fuse enable signal and the cell selection signal; connected to the selection means and only once after said enable circuit is enabled. allows programming of the second group of cells, but thereafter the cells are programmed. a protective shield for disabling said selection means to prevent it from being selected for programming; A programmable logic device consisting of a fuse circuit and a fuse circuit. 2. The device according to claim 1, wherein the selection means is output to the device. A circuit for decoding a cell address signal, which responds to a predetermined cell address signal. consists of a decoder circuit that responds to 3. Claim 2, wherein the cells of the array are arranged in rows and columns. The second group of cells consists of cells in a predetermined row, and the cell address is The row is specified by the state of the bus signal, and the decoder circuit The predetermined row is selected in response to an address signal. 4. Claim 3, wherein the decoder means a decoder for selecting cells in said predetermined row for programming in response to a fuse signal; shall be constructed with disabling means for disabling the operation of the 5. 4. The decoder circuit according to claim 4, wherein the decoder circuit The disable means performs a NOR action on the response signal. is set high by the protection fuse signal, disabling the function of the decoder. consists of the input to the Noah decoder. 6. Claim 1, wherein the output logic circuit is a combinational output. consisting of an output means for selectively outputting force or matching output, selected from the second group of cells; state of the cell in which the logic output is inverted or not. That you are supposed to decide whether or not. 7. A program that allows a given group of electrically programmable cells to be programmed only once. A protective fuse system in a programmable logic device, comprising: Enable that outputs a fuse enable signal in response to a protective fuse activation signal circuit and selecting said predetermined group of cells for programming in response to a cell selection signal; , a decoder circuit connected to the predetermined group of cells, and a fuse enable signal. is responsive to the cell selection signal, is connected to the selection means, and is connected to the selection means; Programming the second group of cells only once after the enable circuit is enabled. programming, but after which the cell is selected for programming. and a protective fuse circuit for disabling the selection means to prevent A protective fuse system consisting of: 8. Claim 7, wherein the programmable logic device comprises: consisting of an array of electrically programmable cells arranged in rows and columns; a group of cells in a given row of the array; The selection signal comprises a row address signal, and the decoder circuit comprises a row address signal. deciphering means for decoding the code, and wherein said circuit decodes the row address of said predetermined row. be responsive to a specific row address signal that specifies the row address. 9. 9. The device according to claim 8, wherein the decoder means a decoder selects cells in the row for programming in response to a fuse signal; shall consist of disabling means to disable the 1σ. 9. The device according to claim 9, wherein the decoder circuit It performs a NOR action on the address signal, and the disable hand a stage is set high by the protection fuse signal to disable the function of the decoder. consisting of an input to a Noah decoder that enables 11. 7. The device according to claim 7, wherein the device comprises a device package. The enable circuit is comprised of a semi-group die provided in a floating gate as a storage element. a cell to be programmed in response to the cell selection signal; a select transistor gate to select the floating gate transistor; acts in the first state when a diagnostic signal is applied to its gate, or electrically erasable nonvolatile device adapted to act in a second state when a signal is applied sexual memory cells, erasing the storage element to the first state before assembling the die into the package; erasing means; a program that sets the storage element to the second state in response to the protective fuse activation signal; logging means, detecting the state of the memory element, and detecting the state of the memory element; state and a diagnostic signal is applied to the gate of the storage element. and a detection means that outputs a fuse enable signal. 12. 12. The device according to claim 11, wherein the erasing means erases the die. A wafer probe pad that can be electrically accessed only before assembly into the package. and the memory element in response to an erase signal applied to the wafer probe pad. The device is configured with means for erasing the child to the first state. 13. Claim 11, wherein the die is placed in the package. after being incorporated, and only when the storage element is in the first state. responsively selectively regeneratively erasing the memory element to the first state; a regenerative eraser that prevents the storage element from being erroneously set to the second state; a stage is provided in the enable circuit. 14. The device according to claim 11, which prevents the charge loss effect due to high temperature. Foreleg floating gate transistors with reduced diagnostic signal levels to provide more headroom. Further, a means for diagnosing dysstasis is provided. 15. The device according to claim 7, wherein the protective fuse circuit comprises: A floating gate transistor as a storage element and a programmable transistor in response to the cell selection signal. and a select transistor gate for selecting the memory element to be programmed. The floating gate transistor is configured to perform a first operation when a diagnostic signal is applied to its gate. a voltage that is adapted to act in a second state and act in a second state when a diagnostic signal is applied. a mechanically erasable non-volatile memory cell; activating the storage element in response to the fuse enable signal and the cell selection signal. programming means for setting a second state; and programming means for setting the storage element to a second state. an output detector that outputs a protective fuse signal depending on the state of the memory element when It must consist of a means of output. 16. The device according to claim 15, wherein the select transistor is , is adapted to respond to a cell selection signal for selecting a cell in said group, and said fuse The enable circuit responds to the enable signal until the enable signal is output. Disabling means are further provided for disabling said programming means in response. that it is 17. Selectively protect a predetermined group of programmable data from modification. A programmable logic device having a protective fuse system that applies a plurality of input lines through which input signals are sent and an electrical program connected to said input lines; Consisting of rammable cells, an array consisting of a first cell group and a second cell group, and a freely configurable array. architecture, connected to said array and connected to said architecture; outputting a logical output of the device according to the state of the input signal and the state of the first cell group; after the system is enabled by the output logic circuit and the fuse actuation signal. a protective fuse system selectively permitting timed programming of said second group of cells; It consists of The array determines which input signals result in the logic output in the state of the first group of cells. The first and second cell groups are configured to determine whether Repeated programming by the user until the system is enabled A programmable logic device that consists of things that are designed to be