JPH0136907B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to a logic analyzer with a comparison function.

BACKGROUND OF THE INVENTION With the development of microprocessor and computer technology, logic technology has become commonplace in various electronic devices. Measuring instruments for developing, adjusting, and repairing electronic equipment using logic technology include oscilloscopes, logic probes, and logic analyzers.
In particular, a logic analyzer stores input logic signals (data) of multiple channels in a storage means such as a random access memory (RAM), and displays the data stored in this storage means on a display means such as a cathode ray tube (CRT). The logic analyzer has two display modes, one of which is to display the logic signal in the signal waveform. The other is a state display mode that displays stored data as words (including numbers) in binary, octal, hexadecimal, etc. Especially the state display mode. In this case, it is not possible to display all the data stored in the storage means due to the relationship between the display area of the display means and the size of the characters, and only the data in the selected address range of the storage means is displayed.

Conventional logic analyzers have various functions, one of which is a comparison function (compare mode). This function is particularly used in the state display mode, in which the input logic signal and the reference logic signal respectively stored in the first and second storage means are displayed on the display means for comparison. Traditional logic analyzers facilitate this comparison by
The display of different portions of the input and reference logic signals is brightness modulated or black and white is inverted, or markers are added to the display of different portions. However, because conventional logic analyzers generally compare the input logic signal and the reference logic signal, it is difficult to identify parts of the reference logic signal of particular interest from the selected comparison range of the input logic signal. It was difficult.

OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide a logic analyzer that identifies portions of an input logic signal within a selected comparison range of input logic signals that match selected desired portions of a reference logic signal.

SUMMARY OF THE INVENTION According to the logic analyzer of the present invention, a selection means selects a desired portion, for example, data at a desired address, from a reference logic signal, and also selects a comparison range of an input logic signal. If the data of the selected reference logic signal has a plurality of addresses, the order of the addresses may be changed as necessary. On the other hand, the comparison display control means compares the selected desired portion and the input logic signal within the comparison range,
The display of the input logic signal displayed on the display means is controlled according to the comparison result. This display control utilizes brightness modulation and markers in addition to black and white inversion (brightness inversion). Further, the start address and end address of the comparison range of input logic signals, and specific characters near the input logic signals within this comparison range, indicating that the input logic signals are within the comparison range, are also displayed on the display means. Thus, portions of the reference logic signal of particular interest can be identified from the input logic signal.

Embodiments of the Invention Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The probe 10 has eight chips and detects eight channels of input logic signals from the device under test. The eight channels of logic signals from the probe 10 are supplied to a comparator 12, and the level of the input logic signal is converted into a logic system (eg, TTL system) suitable for each block in FIG. The output of the comparator 12 is supplied to an acquisition storage circuit 14 made up of a high-speed RAM, etc., and a trigger circuit 16 made up of a word recognizer (a circuit for detecting a predetermined word), a counter, etc. Block 1
4 and 16 are connected to bus 20 (including data, address and control buses). The start/stop control circuit 22 starts the storage operation of the storage circuit 14 in response to a command from the bus 20, and stops this storage operation in response to an output from the trigger circuit 16. The central processing unit (CPU) 24 is, for example, a commercially available
It is a Z80A type microprocessor and operates as various processing means such as comparison display control means. A read-only memory (ROM) 26 is a firmware storage circuit that stores data processing contents of the CPU 24, and a RAM 28, which is a storage means, operates as a temporary storage circuit for the CPU 24 and also includes a display RAM area. These CPU 24, ROM 26, and RAM 28 are also connected to the bus 20. The keyboard 30 has a plurality of keys, is used for selecting a desired part, and other controls and inputs, and is connected to the bus 20. The keyboard 30 thus operates as a selection means. A display control circuit 32 is connected to the bus 20 and generates a luminance signal, horizontal and vertical scanning signals based on data in the display RAM area of the RAM 28, and displays data on a raster scanning type CRT 34 serving as display means. Clock pulse generator 36 generates clock pulses at frequencies responsive to commands from bus 20.
Pulses are supplied to blocks 14, 16, etc. still,
The clock frequencies of blocks 24, 26, 28, and 30 are fixed at, for example, 4MHz (when CPU 24 is Z80A).

When storing an input logic signal, first the keyboard 30 is used to set the clock frequency, trigger word, and number of trigger delay clocks.
These setting data are stored in the first area of the RAM 28 via the bus 20 and the CPU 24 (RAM
28), the trigger circuit 16 and clock pulse generator 36 are set. Next, when a write start command is supplied from the keyboard 30 to the start/stop control circuit 22 via the bus 20 and the CPU 24,
This circuit 22 places the acquisition storage circuit 14 in a write mode and initiates a write operation. As mentioned above, the input logic signal from probe 10 is sent to block 12.
The data are sequentially stored at different addresses in the memory circuit 14 via the memory circuit 14. Note that the address of the memory circuit 14 is designated by an address signal from an address generator (not shown). After the word recognizer in trigger circuit 16 detects the trigger word from the input logic signal as described above, and the counter counts a set number of clocks, it generates an output signal. In response to this output signal, the start/stop control circuit 2
2 stops the write operation of the memory circuit 14. Thus, storage of the logic signal into the storage circuit 14 is completed.

When a transfer command is input from the keyboard 30,
The CPU 24 transfers the memory contents of the memory circuit 14 to the second memory of the RAM 28 based on the firmware of the ROM 26.
Transfer to area. This second area operates as a first storage means, and the logic signal stored in this first storage means becomes a reference logic signal. In this case, it is desirable that the logic signal detected by the probe 10 be a signal from the reference device.

Next, the logic signal from the device under test is stored in the acquisition storage circuit 14 in the same manner as described above. When a display command is input from the keyboard 30, the CPU 24
Based on the firmware of the ROM 26, the storage contents of the storage circuit 14 are transferred to the third area of the RAM 28. This third area operates as a second storage means,
The logic signal stored in this second storage means becomes the input logic signal. Further, the keyboard 30 is used to select a state display mode and a display area (select which part of the memorized logic signal under test is to be displayed), and the code of the selected display mode and display area is stored in the RAM 28. The information is stored in one area via the bus 20 and the CPU 24.
Based on firmware of ROM26, CPU24
converts the logic signal in the third area of the RAM 28 corresponding to the selected display area to, for example, binary character font information (code signal) and sends it to the RAM 28.
is stored in the display RAM area. Display control circuit 32
is a conventional circuit, which includes a ROM that stores the shapes of characters and symbols, a shift register that converts the parallel output of this ROM into a serial signal and generates a Z-axis (luminance) signal, and a vertical and horizontal scanning signal generator. Contains. The display control circuit 32 controls the display of the RAM 28.
The contents of the RAM area are repeatedly read out and the logic signals are displayed on the CRT 34 as a state table of "1" and "0".

When the comparison mode is selected using the keyboard 30, a display as shown in FIG. 3 is displayed on the CRT 34.
This display is performed by the operation described below. "1" displayed on the left half of the CRT34 screen
and "0/" are the logic states of the selected logic signals in the third area of RAM 28, and are displayed by the operation described above. In addition, "ACQ" (simplification of ACQuisition) on the left half of the display means the (intake) input logic signal, and the display below "CH=0/
1234567'' indicates a channel signal of each logic signal and corresponds to each chip of the probe 10. That is, the display below each channel number is the data for that channel. These “ACQ” and channel numbers are based on the ROM26 firmware.
It is displayed via the display RAM area by the operation of the CPU 24. Also, on the left side of the display “197, 198…20/8,
20/9'' indicates the address of the third area of the RAM 28, and the CPU 24 displays the address according to the firmware of the ROM 26 in accordance with the code of the display area stored in the first area of the RAM 28.

In the present invention, a comparison operation can be performed using data of a plurality of addresses among the reference logic signals as one pattern. First, data at a desired address is selected from the reference logic signal using the keyboard 30. In the embodiment, addresses 39, 45, and 41 are selected in this order. When selecting an address, all reference logic signals may be displayed in a scroll mode, and the display of the address selected with the keyboard 30 may be inverted in black and white. Transfer the selected address to RAM28
The address information is stored in the first area of , and displayed on the CRT 34 together with the data at these addresses as shown in the right half of FIG. After this, the order of the addresses may be changed as necessary. In addition, "REF" on the upper right half of the display
(Simplification of REFerence) means the reference logic signal, and the display below it "CH=0/1234567" indicates the channel number. These display contents are also stored in the display RAM area of the RAM 28 as font information.

Data at these three addresses becomes one reference pattern. Based on the firmware in the ROM 26, the CPU 24 compares the data at address 39 in the second area of the RAM 28 with the data at each address in the third area. To do this, first store the data of channel 0 at address 39 in the second area of RAM 28 in the first temporary storage circuit of CPU 24, and then
Data of channel 0 of area address 0
Stored in the second temporary storage circuit of the CPU 24,
The comparison is performed using the exclusive OR function of 4. If the data of channel 0 matches, RAM28
Channel 1 of addresses 39 and 0 in the second and third areas are compared, and only when the data of channel 1 also match, the next channel is sequentially compared. If you detect a channel that does not match among channels 0 to 7, immediately
A comparison is made with address 1 of the third area of the RAM 28, and the comparison is sequentially repeated for each channel until an address of the third area that matches the data of address 39 of the second area is detected. When the CPU 24 detects an address in the third area that matches the address 39 in the second area, it then compares the data at the address 45 in the second area and the data at the address next to the matched address in the third area. Here, if the next address in the third area does not match the address 45 in the second area, the address 39 in the second area and each address in the third area are compared again. Only when the next address in the third area matches the address 45 in the second area, the next address in the third area is compared with the address 41 in the second area. If this comparison does not result in a match, the process starts again from the comparison of address 39 in the second area. If this comparison results in a match, it means that the reference pattern has been detected. in this way
The CPU 24 performs a comparison operation to determine whether the data (pattern) of the selected address in the second area continuously matches the data in the third area, and also inverts the display of the portion that matches the reference pattern in black and white.
Note that this black-and-white reversal may be performed by the CPU depending on the comparison result.
Step 24 is performed by changing the attribute information accompanying the font information in the display RAM area corresponding to the matched content based on the firmware of the ROM 26. In FIG. 3, the display surrounded by a frame means black and white inversion.

The CPU 24 also counts the total number of matched pattern parts and the number of matched pattern parts up to the cursor (three horizontal bars indicated at the address 203, the position of which is controlled by the keyboard 30), and The result is displayed on the top line as “CMPR
"PATER=13/13" is displayed. “CMPR
PATER" (simplification of CoMPaRe PaTtERn) indicates the pattern comparison mode, and "13/13" indicates that the total number of reference patterns is 13 and that the cursor position (address 203 in the example) is the 13th reference pattern. It shows. Therefore, if the cursor position is address 205, the display will be "↑13/13".

2nd line of display “CMPR WDO=0/-20/6”
indicates that a comparison operation is being performed between the start address 0 and the end address 206. That is, “CMPR WDO” (CoMPaRe
WinDow simplification) means the comparison range, and “0/-
20/6'' indicates the address range. This address is selected by the keyboard 30 and
It is stored in the first area of RAM28. Therefore, the total number of matched patterns is the number within this comparison range. Additionally, when the CPU 24 determines that the address of the displayed data is within this comparison range based on the firmware in the ROM 26, it inserts a specific character "C" to the left of the address (as font information in the display RAM area of the RAM 28). (remember) and display. Therefore, the measurer can easily determine the comparison range. In this example, since the comparison range is addresses 0 to 206, addresses 207, 20
The letter "C" is not displayed on the left side of 8,209.

In the above description, the display of the portion of the input logic signal that matches the reference pattern is inverted in black and white, but the display of the portion of the input logic signal that differs from the reference pattern may be inverted in black and white. Further, the number of addresses in the reference pattern may be any number other than three.

Effects of the Invention As described above, according to the logic analyzer of the present invention, a part of particular interest is selected from the reference logic signal, and it is compared as one pattern with the input logic signal within the selected comparison range. .
Then, the display of the input logic signal is controlled according to the comparison result. Thus, it is easy to identify portions of the reference logic signal of particular interest from a selected range of input logic signals. Furthermore, since the comparison range of input logic signals is selected by the start address and end address, selection of the comparison range is facilitated. In addition, specific characters indicating that the signal is within the comparison range are also displayed near the start address and end address and the input logic signal within the comparison range, so that it can be quickly determined which part is being compared.

Modifications of the Embodiments Although only preferred embodiments of the present invention have been described above, those skilled in the art will understand that various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the signal detected by the probe was used as the reference logic signal, but it may be input from the keyboard, or the signal detected by the probe may be partially corrected using the keyboard. In addition to the CRT, flat display devices such as liquid crystal displays and plasma displays, and XY plotters can also be used as display means. Furthermore, when displaying the input and reference logic signals, a set of three or four channels may be displayed in octal or hexadecimal notation, and the number of probe chips, ie, the number of channels, may be any number. In addition to black and white inversion of the display, brightness modulation and markers can also be used to indicate different or equal portions of the input and reference logic signals. Also, when comparing the reference pattern and the input logic signal, if the first address content and the last address content of the reference pattern are equal, the data of one address may overlap in two reference patterns in the input logic signal. . In this case, if it is assumed that the pattern matches the reference pattern only when the cursor moves to the first address of the reference pattern, no problem will occur in the measurement.

[Brief explanation of drawings]

1 is a block diagram of a preferred embodiment of the logic analyzer of the present invention, FIG. 2 is a diagram showing the contents of the storage means 28 of FIG. 1, and FIG. 3 is a table of the display means 34 of FIG. 1. It is a figure which shows an example. 24: comparison display control means, 28: storage means, 3
0: selection means, 34: display means.

Claims (1)

[Scope of Claims] 1. A first storage means for storing a reference logic signal; a second storage means for storing an input logic signal; and selecting a desired portion from the reference logic signal stored in the first storage means. Along with the above second
selection means for selecting a comparison range of the storage means based on a start address and an end address; and at least the input logic signal stored in the second storage means and the desired portion of the reference logic signal selected by the selection means; display means for displaying specific characters indicating that the start address and the end address selected by the selection means and the input logic signal within the comparison range are within the comparison range; The desired portion of the selected reference logic signal is compared with the input logic signal stored within the comparison range of the second storage means selected by the selection means, and the display is performed according to the comparison result. and a comparison display control means for controlling the display of the input logic signal of the means.