JPH03202783A - Logic analyzer - Google Patents

Abstract

PURPOSE:To display in graphic format even when a code system is different from a straight binary code by selecting the code system of digital signals to be measured among a plurality of code systems. CONSTITUTION:When an item of a display code selecting field 29 which selects and sets a code system to be assigned to a data axis 26 is changed through manipulation of a keyboard 21, the plotting position of the data axis 26 can be changed. When the intended display mode is input through the keyboard 21, a CPU 19 reads out the data of an acquisition memory 14 in accordance with a program of a ROM 20. Then, the coordinates corresponding to the data axis 26 and those corresponding to a memory address axis 27 are obtained in straight binary code 25. An address indicating signal is sent to a reference memory 18 and stored there. Thereafter, an address corresponding to a video RAM 15 is calculated, and the plot data is written in the calculated address of the video RAM 15. The plot data is displayed at a display device 17 by a display control circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic analyzer used for determining the logic of digital circuits, measuring timing, and the like.

Conventional technology As microprocessors are used in digital circuits, measurement devices that can judge the logic of digital circuits and measure timing have become important, and practical measurement devices that can meet these demands have become important. The logic analyzer has been transformed into a logic analyzer.

Conventional logic analyzers detect a specific event in the input digital signal from the device under test, and then use the clock of the device under test (external clock) or the clock generated by the clock generator built into the logic analyzer. , by storing a specific event and an input digital signal continuously in time series in a memory, and plotting it on rectangular coordinates with the coordinate axes of the memory address stored in this memory and the data value of the input digital signal. (hereinafter referred to as a graphic format display), so that the process of change in data values as a function of the order of data occurrence can be recognized in a graphical image.

A typical example where observation using this graphic format display is effective is observation of a digital signal after converting an analog signal to digital using an analog/digital converter.

By taking the digital signal into the logic analyzer using a clock synchronized with the digital signal after analog/digital conversion and displaying it in a graphic format, the change process of the digital signal series can be easily recognized visually as an analog waveform image.

In this way, even with the conventional logic analyzer described above, when observing a digital signal after analog/digital conversion, a digital/analog converter is added to the transmission path of the digital signal, and the analog signal after digital/analog conversion is measured using an oscilloscope. A digital signal sequence can be accurately and easily displayed in a graphic format as an analog waveform image without using alternative methods such as observation.

Problems to be Solved by the Invention However, in the conventional logic analyzer described above, the code system assigned to the data axis of the graphic format display is a straight binary code, so the code system for the digital signal series is a code based on complement representation or a binary coded 10 code. If the data is different from a straight binary code such as a hexadecimal code, there is a problem that the data stored in the memory cannot be displayed accurately and easily in a graphic format.

The present invention solves these conventional problems,
The object of the present invention is to provide an excellent logic analyzer that can perform graphic format display even when the data axis is a code system other than straight binary code.

Means for Solving the Problems In order to achieve the above object, the present invention provides a display code selection field for selecting and specifying a code system to be assigned to the data axis of a graphic format display, and selects a digital signal to be measured from among a plurality of code systems. It is configured so that a series of code systems can be selected and specified, and a graphic format display can be performed according to the selected code system.

Therefore, according to the present invention, by changing the item in the display code selection field that selects and specifies the code system to be assigned to the data axis, the data plot position in the data axis direction can be changed, which is not possible in the past. It has the effect of displaying a digital signal sequence in a graphic format using a code using complement representation, a binary coded 10 code, etc., and making it possible to observe it accurately and easily.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. 1
is a probe, which guides a digital signal output from an object to be measured (not shown) to a comparator in the probe 1, compares the threshold voltage sent from the digital/analog converter 2 with the comparator, and converts the signal according to the comparison result. and logically formats it into high level and low level.

3 is a clock selection circuit that selects an external clock outputted from the probe 4 as a sampling clock or an internal clock generated by a clock generator 5 built into this logic analyzer as a sampling clock, and 6 is this clock selection circuit. The above probe 1 is selected by the sampling clock selected in step 3.
This is a sample/latch circuit that samples and latches the logically shaped 11-level and low-level digital signals output from the 11-level and low-level digital signals. 7 is clock selection circuit 3
This is a glitch detection circuit that detects glitches in the sampled signal output from the sample/latch circuit 6 between the sampling clocks selected in .

Reference numeral 8 denotes a word detection circuit that compares a preset word with a sampled signal output from the sampling/latch circuit 6, and outputs a detection signal when the two match.

9 is an edge detection circuit that detects the rising or falling edge of the sampled signal output from the sampling latch circuit 6; 10 is a detection signal output from the glitch detection circuit 7 and a detection signal output from the word detection circuit 8; The detection signal output from the edge detection circuit 9 and the detection signal output from the edge detection circuit 9 are combined in a preset combination,
The trigger circuit 10 outputs a detection signal, and reference numeral 11 indicates an address at which the trigger detection circuit 10 outputs a detection signal and starts counting operation, and stops the counting operation when a preset delay number is counted. It is a counter.

12 is a memory address counter that counts the output of the delay counter 11 and stops counting at the same time as the delay counter 11 stops counting; 13 is a memory address counter that counts the output of the delay counter 11; /Stores the sampled signal output from the latch circuit 6,
This buffer memory finishes storing and outputting the sampled signal at the same time as the counting operation of the memory address counter 12 ends.

14 stores the data transferred from the buffer memory 13 upon completion of the storage operation of the buffer memory 13, and the stored data is sent to the central processing unit 19 (described later) according to display formats such as state display timing display and graph display. It consists of an acquisition memory that is processed by the CPU (hereinafter referred to as the CPU) and transfers the processing results to the video random access memory 15 (hereinafter referred to as the video RAM).

16 is a display control circuit that constantly reads the contents of the video RAM 15 and generates a video signal, a horizontal synchronization signal, and a vertical synchronization signal to be displayed on the display device 17; 18 is a display control circuit that reads the contents of the video RAM 15; This is a reference memory that temporarily stores the contents of the acquisition memory 14 when transferring the contents to the acquisition memory 14.

19 controls a series of operations of the logic analyzer of the present invention using a keyboard 21 according to a program stored in a read-only memory 20 (hereinafter referred to as ROM).
The above-mentioned CPU 22 monitors the information input by the operation of the CPU 19 and the hardware logical state, and writes the data required when the CPU 19 performs a series of processes.
This is a work random access memory (hereinafter referred to as RAM) that performs reading.

Note that 23 is a digital/analog converter 2, a clock selection circuit 3. Glitch detection circuit 7° Word detection circuit 8. Edge detection circuit 9. Trigger detection circuit 10. Delay counter 11. Memory address counter 12. Acquisition memory 14° Video RAM 15. Reference memory 18. ROM20. Keyboard 21. RAM22
This is a data bus for transmitting data between the CPU 19 and the CPU 19.

24 is a digital /address converter 2. Clock selection circuit 3. Glitch detection circuit 7. Word detection circuit 8.
Edge detection circuit 9. The third one is a detection circuit 10, a delay counter 11. Memory address counter 12. Acquisition memory 14. Video RAM15. Display control circuit 16, reference memory 18. ROM20
．． Keyboard 21. This is an address bus for transferring address data between the RAM 22 and the CPU 19.

Next, the operation of the above embodiment will be explained. In the above embodiment, the digital signal input to the probe 1 is compared with the threshold voltage sent from the digital/analog converter 2 by the comparator in the probe 1, and is logically shaped into high level and low level and sampled/latched. It is sent to circuit 6.

On the other hand, the clock selection circuit 3 selects whether to use the external clock sent from the probe 4 as the sampling clock or to use the internal clock generated by the clock generator 5 as the sampling clock.

In this way, the sampling clock selected by the clock selection circuit 3 is sent to the sample latch circuit 6, and this sampling clock causes the sample/latch circuit 6 to
samples and latches the signal input from probe l.

The glitch detection circuit 7 detects glitches in the sampled signal for the sampling clock based on the control signal sent from the CPU 19 through the data bus 23, and sends the detection signal to the detection circuit 10.

Further, the word detection circuit 8 compares a preset word and the signal sampled by the sample/latch circuit 6 based on a control signal sent from the CPU 19 through the data bus 23, and when the two match, triggers a detection signal. The signal is sent to the detection circuit 10.

Furthermore, the edge detection circuit 9
Based on the control signal sent from the PU 19, the sample/latch circuit 6 detects the rising or falling edge of the sampled signal, and the bird sends the detection signal to the detection circuit 10.

The trigger detection circuit 10 includes a sample/latch circuit 6, a word detection circuit 8. The detection signal from the edge detection circuit 9 is sent to the CPU 1 through a preset combination data bus 23.
Synthesize based on the control signal sent from 9,
The bird sends a detection signal to the delay counter 11.

The delay counter 11 is connected to the CPU through the data bus 23.
Based on the control signal sent from 19, the delay number counting operation is started in response to the trigger detection signal, and when the preset delay number is counted, the counting operation is stopped.

The count value of the delay counter 11 is sequentially output to the memory address counter 12.
2 counts based on the control signal sent from the CPU 19 through the data bus 23, specifies the address of the buffer memory 13, and sends the sampled signal output from the sample/latch circuit 6 to the specified address of the buffer memory 13. Save the address.

When the delay counter 11 stops counting by counting the set delay number as described above,
The memory address counter 12 also stops its counting operation at the same time, and the storage operation of the signal sampled by the sample/latch circuit 6 into the buffer memory 13 is completed.

That is, the glitch detection circuit 7. Word detection circuit 8. Edge detection circuit 9. The trigger detection circuit 10 detects a certain event from among the digital signals input to the sample circuit 6 until the trigger detection circuit 10 outputs a detection signal and the delay counter 11 counts the set delay number. It will be detected.

When the storage operation of the buffer 7 memory 13 is completed, the CP
A write signal is sent from U19 to the acquisition memory 14 through the data bus 23, and the address bus 2
An addressing signal is sent through 4, and all the signals stored in the buffer 7 memory 13 are written to the acquisition memory lj 14 at the memory address 28 specified by this addressing signal, as shown in FIG.

FIG. 2 is a graphic format display screen displayed on the display device 17, and displays the contents of the acquisition memory 14 shown in FIG.

In Fig. 2, 25 is a strut binary code, 2
6 is the data axis of the straight binary code 25.

27 is a memory address axis, and a memory address 28 is shown. Reference numeral 29 is a display code selection field for selecting and specifying a code system to be assigned to the data axis 26. A display code selection field 29 is used to select and specify a code system for the digital signal series to be measured from among a plurality of code systems by operating the keyboard 21. Display in graphic format according to the code system.

The data stored in the acquisition memory 14 is 4
A bit analog/digital converter (not shown) converts the triangular wave from analog to digital, and the output is [2
This is a digital signal sequence that is the complement code of '' and is stored, and the code for each sample is 1.
This is an ideal example of a step-by-step change.

Next, a case in which data in the acquisition memory 14 is displayed on the display device 17 will be described.

By operating the keyboard 21 to change the items in the display code selection field 29 for selecting and specifying the code system to be assigned to the data axis 26 shown in FIG. 2, the data plot position in the direction of the data axis 26 can be changed.

In this way, when displaying the data stored in the acquisition memory 14 on the display device 17, when a key input for this display mode is made from the keyboard 21, the CPU
19 sends a read signal through the data bus 23 and an address designation signal through the address bus 24 to the acquisition memory 14 in accordance with the program in the ROM 20, and reads out the data in the acquisition memory 14. The data stored in the acquisition memory 14 is displayed in a graphic format on the display device 17 according to the format of display such as state display, timing display, graph display, etc. based on the control signal sent from the CPU 19 through the data bus 23. For this purpose, the memory address and data value of the acquisition memory 14 are
By plotting on orthogonal coordinates defined as the memory address axis 27 and the data axis 26, the coordinates corresponding to the data axis 26 and the coordinates corresponding to the memory address axis 27 of the straight binary code 25 shown in FIG. 2 are determined.

Next, a write signal is sent from the CPU 19 to the reference memory 18 through the data bus 23, and an address designation signal is sent to the reference memory 18 through the address bus 24, and this reference memory 18 is addressed, and the data read from the acquisition memory 14 is temporarily memorize.

Next, the CPU 19 calculates an address corresponding to the video RAM 15, sends a write signal from the CPU 19 to the video RAM 15 through the data bus 23, and sends an address designation signal through the address bus 24 to write the plot data to the address of the video RAM 15 calculated above. Write.

The plot data written in the video RAM 15 is constantly read by the display control circuit 16 and output as a video signal and a horizontal synchronization signal.

The vertical synchronization signal is transferred to the display device 17, thus producing the graphic display shown in FIG. 2 on the display device 17.

In the embodiments shown in FIGS. 2 and 3, the code systems for the input digital signal series and the graphic format display are different, so that the changing process of the digital signal series is not correctly displayed.

FIG. 4 shows an example of a graphic format display on the display device 17 when the input digital signal series and the code system of the graphic format display match.

In the case of 2, if the item in the display code selection field 29 is selected and specified as "2's complement" using the keyboard 20, C
The PU 19 reads the data in the acquisition memory 14 according to the program in the ROM 20, and determines the coordinates corresponding to the data axis 26 and the coordinates corresponding to the memory address axis 27 of the complement code 30 shown in FIG. , once stored in the reference memory 18, the video R
Calculate the address corresponding to AM15 and write the plot data to the above address.

Thereafter, in the same manner as in the above embodiment, the display control circuit 16 reads out the data written in the video RAMI 5 and causes the display device 17 to display the graphic format shown in FIG. 4.

Effects of the Invention As is clear from the above embodiments, the present invention has the following effects.

(1) A display code selection field is provided to select and specify the code system to be assigned to the data axis of the graphic format display, and the code system for the digital signal series to be measured is selected and specified from among multiple code systems. It is possible to accurately display in a graphic format digital signals of code systems that could not be supported in the past, such as codes using complement representation and binary coded decimal codes.

(2) Complicated operations such as replacing certain bits of multiple bits that make up one data or inverting the logical polarity to make data other than straight binary code correspond to the data axis of straight binary code. By simply selecting and specifying the items in the display code selection field, the specified code system is displayed in a graphic format without having to do anything, so it can be operated efficiently and easily.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a logic analyzer according to an embodiment of the present invention, Fig. 2 is an explanatory diagram of a graphic format displayed on a display device in the logic analyzer, and Fig. 3 is a storage content of an acquisition memory in the logic analyzer. FIG. 4 is an explanatory diagram of another graphic format displayed on the display device of the same logic analyzer. 1.4... Probe, 2... Digital/analog converter, 3... Clock selection circuit, 6... Sample/latch circuit, 7... Glitch detection circuit, 8...
・Tori is the detection circuit, 9... Word detection circuit, 10...
・Edge detection circuit, 11...Delay counter, 12
...Memory address counter, 13...Buffer memory, 14...Acquisition memory, 15...Video RAM 116...Display control circuit, 17...Display device, 18...Reference memory, 19 ...CPU, 20...ROM, 21...Keyboard, 22...RAM, 25...Straight binary code, 26...Data axis, 27...Memory address axis, 28... Memory address, 29...Display code selection field, 30...2's complement code.

Claims (1)

[Scope of Claims] Means for detecting a certain specific event in an input digital signal; a memory for storing the input digital signal that is chronologically continuous with the event; The data stored in the memory is plotted on Cartesian coordinates with the data axis and the memory address as the memory address axis, and the code system to be assigned to the data axis is selected from among multiple code systems. A logic analyzer equipped with means for displaying the data in the memory in a graphic format using a code system.