JPH0132998B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument equipped with an automatic performance device that follows the tempo of manual performance only when the tempo of manual performance on the keyboard is within a predetermined range with respect to a reference tempo. It is designed to control the tempo of automatic performance.

2. Description of the Related Art Hitherto, electronic musical instruments have been known that automatically generate musical tones or display keys pressed to assist manual performance using a keyboard. Furthermore, in this type of electronic musical instrument, it has already been proposed to control the tempo of automatic performance (musical tone generation or key depression display) so as to follow the tempo of manual performance.

However, with this type of tempo control method, if the timing of manual performance keys is pressed too early, too late, or if no keys are pressed, the tempo of automatic performance changes unnecessarily, hindering smooth performance practice. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel electronic musical instrument that prevents unnecessary changes in the tempo of automatic performance.

The electronic musical instrument according to the present invention controls the tempo of automatic performance by following the tempo of manual performance when the tempo of manual performance is within a predetermined range with respect to the reference tempo, but otherwise controls the tempo of automatic performance. This is characterized by controlling the tempo so that it does not change beyond a predetermined limit value (maximum value or minimum value).Hereinafter, an embodiment shown in the accompanying drawings will be described in detail.

FIG. 1 shows the circuit configuration of an electronic musical instrument equipped with an automatic performance device according to an embodiment of the present invention.

A recording medium 10a such as a magnetic tape is attached to the lower margin of the musical score 10, and the recording medium 10a
Musical score data corresponding to the musical score content is recorded.

The musical score data reading control circuit 12 is connected to the recording medium 10a.
The system reads the musical score data from the melody data memory 14 and the accompaniment data from the melody data memory 14 and the accompaniment data memory 16 and stores them therein. In order to control such transfer and storage operations, a write address signal is used. WAD, write command signals WT ₁ and WT ₂ , and address selection signals AS ₁ and AS ₂ are sent out. Furthermore, the musical score data reading control circuit 12 reads tempo data TED indicating a reference tempo from the recording medium 10a and supplies it to the tempo control circuit 13.

The memories 14 and 16 are both RAMs (random access memories), and are supplied with address signals from corresponding selector circuits 18 and 20. Selector circuit 18
and 20 are address selection signals AS ₁ and 20, respectively.
The selector circuit 18 performs a selection operation according to AS ₂ , and if the selection signal AS ₁ is “1”, the control input SA
is “1” and selects input A, and if selection signal AS ₁ is “0”, control input SB is selected by inverter 18a.
is “1” and input B is selected. Furthermore, if the selection signal AS ₂ is "1", the selector circuit 20 receives the control input.
If SA is "1" and input A is selected, and selection signal AS ₂ is "0", control input SB is selected by inverter 20a.
is “1” and input B is selected.

When the musical score 10 is inserted into the receiving port of the data reader included in the musical score data reading control circuit 12 and the data reading operation is started, the memory 14 enters the write mode in response to the write command signal _WT1 , and the memory 14 is supplied with a write address signal WAD from a selector circuit 18 which is in a state of selecting input A in response to selection signal _AS1 . For this reason, the memory 14
Melody data corresponding to the melody progression of the musical score 10 is written in the format shown in FIG. 2. That is, the melody data written at this time expresses the melody tones to be generated by a combination of an 8-bit key code KC and an 8-bit length code LNG, and each key code KC is expressed as an example for the note name _C3 . The upper 2 bits are the identification code,
The lower 2 bits are the octave code, the remaining 4 bits are the note code, and each length code is
LNG is the top 2 as shown in the example for an eighth note.
The bit is an identification code, and the remaining 6 bits are a note length code. Rests are key code KC
It is expressed by setting all 6 bits other than the identification code bit to "0". After writing the last melody data, an end code FNS in which all 8 bits are "1" is written into the memory 14. Note that the upper two bits of this end code FNS are also an identification code.

After writing the end code FNS, memory 1
6 enters the write mode in response to the write command signal WT ₂ , and the memory 16 enters the input A in response to the selection signal AS ₂ .
A write address signal WAD is supplied from the selector circuit 20 which is in a state of selecting. For this reason,
Accompaniment data corresponding to the progression of accompaniment (chords or bass notes) of the musical score 10 is written in the memory 16 in a format as shown in FIG. In other words, the accompaniment data written at this time uses an 8-bit key code KC and an 8-bit length code to represent the chord to be generated.
Expressed in combination with LNG, each key code KC has the upper two bits as an identification code, the lower two bits as a chord type code, and the remaining four bits as a root note code, as shown in the example for C _major (CM). It's summery. Here, the chord type code is "00" for major, "01" for minor, and "10" for seventh. Further, in each length code LNG in the accompaniment data, the upper two bits are an identification code, and the remaining six bits are a note length code, as illustrated for a half note.

After the series of data reading/writing operations as described above, the start switch _SW0 of the start/stop control circuit 22 is turned on to operate the melody data reading circuit 24 and the accompaniment data reading circuit 26. That is, when the start switch _SW0 is turned on, the on signal is differentiated by the differentiating circuit 28 in synchronization with the system clock signal φ and is converted into the start signal ΔSTRT. The start signal .DELTA.STRT sets the RS flip-flop 30, so that the flip-flop 30 sends out a performance mode signal PLAY whose output Q is "1". At this time, since the input signal of the inverter 32 is "0", the output signal of the inverter 32 = "1" is supplied to the AND gate 36 via the OR gate 34. Therefore, when the performance mode signal PLAY="1" is generated, the AND gate 36 becomes conductive and supplies the clock signal φ to the address counter 38.

Address counter 38 receives start signal ΔSTRT
When reset by , the first read address signal RAD ₁ is supplied to the selector circuit 18 as input B. At this time, the selector circuit 18 receives the selection signal
Input B is selected due to AS ₁ = “0”,
A first read address signal RAD ₁ is supplied to the memory 14. Therefore, the key code data corresponding to the first melody tone is read out from the memory 14, the upper 2 bits of which are sent to the identification code detection circuit 40, and the remaining 6 bits of the melody key code (octave code and note) are sent to the identification code detection circuit 40. The code signals are respectively applied to latch circuits 42 which are timed by the clock signal φ.

The identification code detection circuit 40 generates a key code detection signal MK in response to the first key code data from the memory 14, and the latch circuit 42 latches the first melody key code signal in response to this key code detection signal MK. The melody key code signal MKC from the latch circuit 42 is transmitted to the display section 44.
supplied to

The display section 44 is provided with a display control circuit 46 which receives the melody key code signal MKC as an input, and this display control circuit 46 receives the output of the display select switch _SW1 from the AND gate 48 which is conductive in response to the performance mode signal PLAY. When the enable signal EN is supplied in response to the input, the light emitting elements in the light emitting element group 52 provided along the key arrangement of the keyboard 50 are selectively controlled to light up to visually display the key to be pressed. It's summery. Therefore, if the first melody key code signal MKC indicates the note name C ₃ as in the example shown in FIG. 2, the light emitting element corresponding to the C ₃ key lights up to instruct the key to be pressed.

After the key press display corresponding to the first melody tone starts as described above, when the counter 38 counts the clock signal φ, the memory 14
Length code data corresponding to the first melody tone is read out from. Of the read data at this time, the upper 2 bits of the identification code signal are supplied to the identification code detection circuit 40, and the remaining 6 bits of the melody code length code signal are supplied to the latch circuit 54 which is timed by the clock signal φ. . Then, since the identification code detection circuit 40 generates the length code detection signal ML in accordance with the first length code data from the memory 14, the latch circuit 54 generates the length code detection signal ML according to the first length code data from the memory 14. Latch accordingly. Further, since the length code detection signal ML at this time is supplied to the inverter 32, the output signal of the inverter 32 becomes "0", thereby temporarily stopping the counting operation of the counter 38.

Thereafter, at a time delayed by about 2 bit times of the clock signal φ from the generation point of the start signal ΔSTRT, the two-stage D clock timed by the clock signal φ
- Flip-flop 56 generates restart signal ΔSTRT'. This restart signal ΔSTRT' makes the AND gate 36 conductive via the OR gate 34, so that the counter 38 starts again.
The clock signal φ from AND gate 36 is counted. Therefore, the key code data and length code data corresponding to the second melody tone are sequentially read out from the memory 14, and in response to this, the identification code detection circuit 40 outputs the key code detection signal MK and the length code detection signal MK. Generate ML sequentially. At this time, the key code detection signal MK causes the first melody key code signal to be transferred from the latch circuit 42 to a similar latch circuit 58, and the latch circuit 4
2 to latch the second melody key code signal. Also, the length code detection signal ML at this time
is a latch circuit 54 to a similar latch circuit 6.
0, the first melody code length code signal is transferred, the latch circuit 54 is made to latch the second melody code length code signal, and the counting operation of the counter 38 is temporarily stopped via the inverter 32 as in the previous case.

The melody key code signal MKC corresponding to the second melody tone from the latch circuit 42 is displayed on the display section 4.
Since the second melody tone is supplied to the second melody tone, the display section 44 displays the pressed key corresponding to the second melody tone, as in the previous case. Also, at this time, a melody key code signal corresponding to the first melody tone is output from the latch circuit 58.
Since MKC' is supplied to the automatic melody sound signal forming circuit 62, this circuit 62 receives the performance mode signal.
When the enable signal EN is supplied from the AND gate 64, which is conductive in PLAY, in response to turning on the sound generation select switch _SW2 , a melody sound signal is electronically synthesized according to the melody key code signal MKC' and output. The signal is supplied to a speaker 68 via an amplifier 66. Therefore, the first automatic melody sound is played from the speaker 68 with a delay of one tone relative to the key depression display.

On the other hand, the melody note length code signal MLG corresponding to the first melody note from the latch circuit 60 is supplied to the tempo control circuit 13. Tempo control circuit 1
3 is a melody note length code signal MLG and a melody key code signal as will be described later with reference to FIG.
MKC, key code signal KKC, tempo data
It generates the tempo clock signal TCL and readout control signal NEXT based on TED and performance mode signal PLAY, and the first melody note length code signal.
For MLG, the first readout control signal NEXT is generated when the key corresponding to the second melody tone is to be pressed. This first read control signal NEXT is an AND
Since the gate 80 supplies the signal to the AND gate 36 via the OR gate 34, the counter 38 outputs an AND signal.
Counting of the clock signal φ from gate 36 is restarted. Therefore, the key code data and length code data corresponding to the third melody tone are sequentially read out from the memory 14, and the latch circuits 58 and 4
A second melody key code signal and a third melody key code signal are latched in the latch circuits 60 and 54, respectively, and a second melody key code signal and a third melody key code signal are latched in the latch circuits 60 and 54, respectively. be done. Therefore, the automatic melody sound signal forming circuit 62 forms a melody sound signal for the second melody sound, and the display unit 4
4, a key press corresponding to the third melody tone is displayed, and the tempo control circuit 13 performs an operation to generate a second readout control signal based on the second melody note length code signal. and,
The above-mentioned operations are repeated in the same manner, thereby achieving an automatic key press display based on the data stored in the memory 14 and an automatic performance of a melody note delayed by one note with respect to this display.

Note that the end code data is finally read out from the memory 14, and in response to this, the identification code detection circuit 40 generates the end code detection signal FN. This end code detection signal FN is applied to the flip-flop 30.
As a result, the performance mode signal PLAY becomes "0" and a series of data reading from the memory 14 is completed.

The key switch circuit 82 includes a large number of key switches each linked to a large number of keys on the keyboard 50, and supplies a key code signal KKC indicating the pressed key to the manual performance sound signal forming circuit 84 and the aforementioned tempo control circuit 13. It's becoming like that. The manual performance sound signal forming circuit 84 electronically synthesizes a melody sound signal corresponding to the pressed key in response to the key code signal KKC from the key switch circuit 82, and supplies the synthesized melody sound signal to the speaker 68 via the output amplifier 66. Therefore, the speaker 68 also produces melody sounds by manual performance.

In this case, if manual performance practice is performed using the keyboard 50, it is possible to efficiently practice performance while listening to the above-mentioned automatic performance sound and/or while viewing the automatic key press display by the light emitting element group 52. When practicing this kind of performance,
Automatic accompaniment of chords or bass notes and/or automatic rhythm accompaniment as described below can also be used as appropriate.

In the accompaniment data reading circuit 26, since the input signal of the inverter 86 is "0" when the start switch SW ₀ is turned on, the output signal of the inverter 86 = "1" is ANDed through the OR gate 88.
It is supplied to the gate 90. Therefore, start switch SW ₀ is turned on and the performance mode signal is output.
When PLAY="1" is generated, AND gate 90
A clock signal φ is supplied from the address counter 92 to the address counter 92.

Address counter 92 receives start signal ΔSTRT
When reset by , the first read address signal RAD ₂ is supplied to the selector circuit 20 as input B. At this time, the selector circuit 20 is in a state of selecting input B with the selection signal AS ₂ =“0” and supplies the first read address signal RAD ₂ to the accompaniment data memory 16. For this reason, the memory 16
The key code data corresponding to the first accompaniment note is read out, and the upper 2 bits of the identification code signal are sent to the identification code detection circuit 94, and the remaining 6 bits of the accompaniment key code (chord type code and root note code) signal are sent to the identification code detection circuit 94. are respectively supplied to a latch circuit 96 timed by a clock signal φ.

Identification code detection circuit 94 generates key code detection signal AK in response to the first key code data from memory 16, and latch circuit 96 latches the first accompaniment key code signal in response to this key code detection signal AK.

Thereafter, when the counter 92 counts the clock signal φ, the length code data corresponding to the first accompaniment tone is read out from the memory 16 in the same manner as the previous time. Of the read data at this time, the upper 2 bits of the identification code signal are supplied to the identification code detection circuit 94, and the remaining 6 bits of the accompaniment note length code signal are supplied to the latch circuit 98 which is timed by the clock signal φ. . Then, since the identification code detection circuit 94 generates the length code detection signal AL in accordance with the first length code data from the memory 16, the latch circuit 98 generates the length code detection signal AL according to the first accompaniment note length code signal. Latch accordingly. Further, the length code detection signal AL at this time is supplied to the inverter 86. Therefore, the output signal of the inverter 86 becomes "0" and is passed through the OR gate 88 to the AND
Gate 90 is made non-conductive. Therefore, counter 9
The counting operation of step 2 is temporarily stopped.

After this, the restart signal ΔSTRT′ mentioned above is OR
Since AND gate 90 is made conductive via gate 88, counter 92 again counts the clock signal φ from AND gate 90. Therefore, the key code data and length code data corresponding to the second accompaniment tone are sequentially read out from the memory 16, and in response to this, the identification code detection circuit 94 outputs the key code detection signal AK and the length code detection signal AK. AL
occur sequentially. The key code detection signal AK at this time causes the latch circuit 96 to transfer the first accompaniment key code signal to a similar latch circuit 100, and also causes the latch circuit 96 to latch the second accompaniment key code signal. In addition, the length code detection signal AL at this time causes the latch circuit 98 to transfer the first accompaniment note length code signal to a similar latch circuit 102, and causes the latch circuit 98 to latch the second accompaniment note length code signal. Further, as in the previous case, the counting operation of the counter 92 is temporarily stopped via the inverter 86.

As a result of the above operations, the latch circuit 100 begins to send out the first accompaniment key code signal AKC, and the latch circuit 102 comes to send out the first accompaniment note length code signal ALG. and,
This first accompaniment note length code signal ALG is supplied to the comparator circuit 104 and compared with the count output K of the tempo counter 106. Here, tempo counter 1
06 is reset by the start signal ΔSTRT from the OR gate 108 and then counts the tempo clock signal TCL from the tempo control circuit 13. Therefore, the comparison circuit 104 determines whether the counted value of the counter 106 is the first accompaniment note. long code signal
When the value corresponding to the note length indicated by ALG is reached, a match signal EQ is generated.

Since the match signal EQ at this time resets the counter 106 via the OR gate 108, the counter 106 counts the tempo clock signal TCL again after being reset. Further, since the coincidence signal EQ is supplied from the AND gate 110, which is turned on by the length code detection signal AL, to the AND gate 90 via the OR gate 88, the counter 92 is
Counting of the clock signal φ from gate 90 is restarted. Therefore, the key code data and length code data corresponding to the third accompaniment note are sequentially read out from the memory 16, and the latch circuits 100 and 96
2nd accompaniment key code signal and 3rd accompaniment key code signal respectively.
The second accompaniment key code signal is latched, and the second accompaniment note length code signal and the third accompaniment note length code signal are latched in the latch circuits 102 and 98, respectively. As a result, the second accompaniment key code signal AKC is sent out from the latch circuit 100, and the second accompaniment note length code signal ALG is sent out from the latch circuit 102.
Comparison circuit 104 measures the note length of the second accompaniment tone. The above-mentioned operations are repeated in the same manner, so that the accompaniment data is successively read from the memory 16, so that the accompaniment key code signal AKC is sent out from the latch circuit 100 one after another. Note that the reading of data from the memory 16 ends before the end data is read from the memory 14, and the counter 92
The end data is read from 4 and the performance mode signal is sent.
When PLAY returns to "0", the counter 38 stops advancing at the same time.

The accompaniment key code signal AKC sent out from the accompaniment data reading circuit 26 as described above is supplied to the automatic accompaniment tone signal forming circuit 112. The automatic accompaniment sound signal forming circuit 112 generates an enable signal EN from the AND gate 114 which is conductive in response to the performance mode signal PLAY in response to the turning on of the sound generation select switch _SW3 .
is supplied, the accompaniment key code signal AKC
The accompaniment tone signal is electronically synthesized based on the rhythm selection data (not shown), and the accompaniment tone signal includes a chord signal corresponding to a plurality of chord constituent notes, and a bass that matches the chord and rhythm to be generated. It is designed to generate sound signals. and,
The transmission timing of each accompaniment sound signal from the automatic accompaniment sound signal forming circuit 112 is controlled in conjunction with the rhythm according to the accompaniment timing signal AT from the rhythm pattern generation circuit 116.
The accompaniment signal from circuit 112 is supplied to speaker 68 via output amplifier 66 . Therefore, automatic accompaniment sound is also produced from the speaker 68.

The rhythm pattern generation circuit 116 is configured to generate a rhythm pattern signal RP in addition to the accompaniment timing signal AT described above in response to the tempo clock signal TCL from the tempo control circuit 13, and this rhythm pattern signal RP is generated by the rhythm sound source circuit 118.
supplied to The rhythm sound source circuit 118 drives an appropriate rhythm sound source according to the rhythm pattern signal RP to generate a rhythm sound signal, and this rhythm sound signal is also supplied to the speaker 68 via the output amplifier 66. Therefore, the automatic rhythm sound is also produced from the speaker 68.

FIG. 4 shows an example of the display and performance operations of the above-mentioned electronic musical instrument, where A indicates the note progression of the musical score,
B indicates the key press display timing, and C indicates the automatic performance timing of the melody and accompaniment. According to FIG. 4, it can be clearly seen that the key press display precedes the automatic melody tone by one note.

Next, the configuration and operation of the tempo control circuit 13 will be explained with reference to FIG. The manual tempo setting circuit 120 sends tempo data indicating a reference tempo appropriately set by manual operation to the selector circuit 1.
22 as input A,
As input B of the selector circuit 122, tempo data TED is supplied in the form of parallel data from a register circuit 124 that stores the tempo data TED supplied in the form of serial data from the musical score data reading control circuit 12 described above. Selector circuit 12
2, when the selection signal SA or SB is set to "1" by the select switch SW ₄ , if SA="1", the tempo data is sent from the manual tempo setting circuit 120, and if SB="1", the tempo data is sent from the register circuit 124. tempo data is supplied to the selector circuit 126 as input B.

Since the performance mode signal PLAY is “0” before turning on the start switch SW ₀ mentioned above, the AND
The output signal of the gate 128 is "0", and the output signal of the inverter 130 whose input is this output signal = "0" is "1". Since the selector circuit 126 receives the output signal of the inverter 130 as the selection signal SB for selecting input B, the tempo data as input B is not sent to the comparison circuit 132 before the start switch SW ₀ is turned on. supply

The clock signal source 134 is a high speed clock signal φ ₁
and generates a low-speed clock signal φ ₂ , and φ ₁
has a frequency several times as large as φ ₂ . These clock signals φ ₁ and φ ₂ are supplied to selector circuit 136 as inputs A and B, respectively. The selector circuit 136 selects the output Q of the R-S flip-flop 138.
is received as the selection signal SA and this output Q
The selection signal is the signal inverted by the inverter 140.
It is now received as SB, and before the start switch SW ₀ is turned on, it is a performance mode signal.
Since the signal = "1" obtained by inverting PLAY = "0" by the inverter 142 resets the flip-flop 138 via the OR gate 144, SB =
In response to "1", the clock signal φ ₂ as input B is selected and supplied to the counter 146.

The counter 146 counts the clock signal φ ₂ from the selector circuit 136 and supplies the count output to the comparator circuit 132. Therefore, the comparator circuit 132 compares the tempo data from the selector circuit 126 and the count output from the counter 146, and when they match, generates a match signal EQ. This match signal EQ is delayed slightly by the D-flip-flop 148 and then resets the counter 146, so that the counter 146 again counts the clock signal φ ₂ after being reset. and,
The count data of the counter 146 is transmitted to the select circuit 12.
When the tempo data from No. 6 match, the match signal EQ is generated again, and the same operation is repeated thereafter. As a result, the comparison circuit 132 outputs a match signal.
EQ will be generated periodically in response to the standard tempo. Since the output signal of the NAND gate 150 is "1" before the start switch SW ₀ is turned on, the coincidence signal EQ generated in this way is an AND gate that is conductive due to this output signal = "1". 152 as a tempo clock signal TCL.

In this way, before the start switch _SW0 is turned on, the tempo clock signal TCL is generated in a form having a frequency corresponding to the reference tempo, so that the automatic rhythm sound is produced from the speaker 68 at the reference tempo. Therefore, the performer only has to turn on the start switch _SW0 in order to start playing at the same tempo as this automatic rhythm sound.

When the start switch SW ₀ is turned on, the performance mode signal PLAY becomes "1" as described above. This signal PLAY="1" releases the reset of the counter 156 via the inverter 154. At this time, the output signal of the counter 156 = "0" makes the AND gate 160 conductive via the inverter 158, so the counter 156 becomes in a state where it can count the read control signal NEXT from the AND gate 160.
Here, the counter 156 receives the read control signal NEXT
Since the counter 156 generates an output signal = "1" when two pieces are counted,
AND gate 12 until NEXT counts 2
The output signal of the selector circuit 12 is “0”, and the output signal of the selector circuit 12
6 is a comparison circuit 1 for tempo data corresponding to input B.
32 will continue to be supplied.

Furthermore, the flip-flop 138 is reset and released by the performance mode signal PLAY=“1”.
Since the reset state continues until the first key is pressed, the selector circuit 136 continues to send out the clock signal φ ₂ corresponding to the input B.

Furthermore, even if the performance mode signal PLAY becomes "1", the output signal of the inverter 162 remains unchanged from the comparison circuit 16.
Since 4 does not become "1" until input A becomes equal to input B, the AND gate 152 continues to send out the tempo clock signal TCL in accordance with the reference tempo as before.

Therefore, the counter 166 receives the performance mode signal.
Inverter 168 and OR by PLAY="1"
After the reset is released via gate 170, the tempo clock signal TCL corresponding to the reference tempo is counted, and the counting output is supplied as input A to comparison circuit 164. As input B of the comparison circuit 164, a melody note length code signal MLG corresponding to the first automatic melody tone is supplied at the same time as the first automatic melody tone is generated. Therefore, the comparison circuit 164 compares both inputs A and B, and when A<B, it supplies the output signal = "1" to the inverter 162, and when A = B, the output signal = "1" is supplied to the AND gate 172. , 174, 176, and 178, and resets the RS flip-flops 138 and 180 with the output signal = "1" corresponding to A=B.

By the way, the performer listens to the automatic rhythm sound played at the standard tempo, looks at the key press display corresponding to the first melody sound as necessary, and then starts the first melody sound almost at the same time as the first automatic melody sound is generated. Press the corresponding key. In this case, the key code signal
KKC corresponds to the first melody sound,
Since the melody key code signal MKC corresponds to the second melody tone, the comparison circuit 182 which receives both signals KKC and MKC as inputs receives a matching signal.
Does not generate EQ.

After this, almost at the same time as the comparison circuit 164 generates the output signal = "1" corresponding to A=B, that is, at the end of the duration (note length) of the first melody note, the output signal corresponding to the second melody note is generated. When you press the key,
Since the key code signal KKC corresponds to the second melody tone, the comparator circuit 182 generates a coincidence signal EQ. At this time, the key code signal
The OR gate 184, which receives KCC as an input, detects the depression of the key corresponding to the second melody tone and supplies an any key-on signal AKO="1" to the AND gate 186, making it conductive. Therefore, the comparison circuit 18
The match signal EQ from EQ.

Differentiating circuit 190 differentiates the output signal of OR gate 188 to generate the first key-on signal KON. This key-on signal KON is AND gate 1
76 to OR gate 192, which in turn outputs the first read control signal.
Send NEXT.

Note that when the melody key code signal MKC indicates a rest, the rest detection circuit 194 outputs the signal =
Generates “1” and supplies it to AND gate 172.
Since the output signal of the AND gate 172 at this time acts in the same manner as the output signal generated from the AND gate 186 when a key is pressed, the read control signal NEXT is also generated when a rest is detected.

On the other hand, during the period from the time when the first melody code length code signal MLG is supplied to the comparator circuit 164 until the time when the OR gate 192 generates the first readout control signal NEXT, the counter 196 receives the signal from the variable frequency divider circuit 198. The frequency-divided output pulses are counted, and the counted output is input B to the selector circuit 200, and input A is input to the comparator circuits 202 and 204.
Supplied as follows. In this case, frequency divider circuit 1
98 divides the clock signal φ ₂ by a frequency division ratio corresponding to the note length indicated by the first melody note length code signal MLG, and supplies the divided output pulse to the counter 196 . The frequency dividing circuit 198 is provided to increase the frequency division ratio for longer notes and to make the number of clock pulses per note the same for all notes.

As the input B of the comparison circuit 202, the lower limit tempo data MIN which is 0.5 times the tempo data from the selector circuit 122 is supplied from the lower limit setting circuit 206, and as the input B of the comparison circuit 204, the tempo data from the selector circuit 122 is supplied. The upper limit tempo data multiplied by 1.5 is supplied from the upper limit setting circuit 208. Then, the comparison circuit 204 compares the inputs A and B, and outputs a signal = "1" corresponding to A≦B.
is supplied to the AND gate 210 and the comparison circuit 202
compares inputs A and B and supplies an output signal=“1” to the AND gate 210 when A≧B. Therefore, the AND gate 210 indicates that the comparator circuit 202
In response to generation of the output signal ="1" corresponding to ≧B, the output signal ="1" is supplied to the AND gate 212 to make it conductive. The fact that the AND gate 210 generates the output signal = “1” in this way means that
This means that the manual performance tempo was within a predetermined range relative to the reference tempo.

As mentioned above, the differentiating circuit 190 generates the first key-on signal KON at the time when the second key should be pressed according to the standard tempo, so this signal KON
causes RS flip-flop 214 to be set via AND gate 212. The output Q=“1” of this flip-flop 214 is a selection signal for selecting input B to the selector circuit 200.
Since the count output of the counter 196 is supplied as SB, the count output of the counter 196 is supplied to the latch circuit 216 via the selector circuit 200, and the first read control signal NEXT
It is latched by the latch circuit 216 in response to this. Immediately after this latch, the counter 196 is reset in response to the first read control signal NEXT,
After the reset, the frequency divided output pulses from the frequency dividing circuit 198 are counted again. Also, the first read control signal NEXT is sent to the counter 1 via the OR gate 170.
Since the counter 166 is reset, the counter 166 again counts the tempo clock signal TCL after the reset. Furthermore, the first read control signal NEXT
causes flip-flop 214 to be reset via D-flip-flop 218.

The above is the operation when the key press timing corresponding to the second melody note matches the timing at which the second key should be pressed according to the standard tempo, but if the key press is too early, too late or
The operation when a key is not pressed is as follows.

First, the case where the key is pressed too quickly will be explained separately in case 1 and case 2, as shown in FIG. Case 1 is a case where the key-on signal KON is generated before the count value of the counter 166 reaches a value 0.5 times the maximum count value N corresponding to the note length. In this case, the key-on signal KON from the differentiating circuit 190 causes the flip-flop 138 to be set via the AND gate 220, which is rendered conductive by the output signal corresponding to A<B from the comparator circuit 164 = "1". . At this time, the output Q=“1” of the flip-flop 138 is the selection signal.
Since it is supplied to the selector circuit 136 as SA,
The selector circuit 136 selectively sends out the high speed clock signal _φ1 . For this reason, the counter 14
The counting speed of 6 increases and the tempo clock signal
Since the frequency of TCL becomes high, the counter 166
counting speed increases. Also, the key-on signal
Since KON sets the flip-flop 180, the output Q of the flip-flop 180 is "1".
is applied to AND gate 178 through D-flip-flop 222, causing it to conduct. After this, when the comparator circuit 164 generates an output signal = "1" corresponding to A=B, this output signal = "1"
It is sent out as read control signal NEXT via AND gate 178 and OR gate 192. Also,
Output signal from comparison circuit 164 at this time = “1”
causes flip-flops 138 and 180 to be reset. Resetting flip-flop 138 causes selector circuit 136 to selectively send out low-speed clock signal φ ₂ .

Read control signal generated in this way
NEXT resets counter 196, but
Prior to this reset, the count output of the counter 196 is supplied as input A to a comparator circuit 202 and compared with lower limit tempo data MIN as input B.
Since A<B before the key-on signal KON is generated, the comparator circuit 202 supplies an output signal=“1” corresponding to A<B to the AND gate 224, making it conductive. Therefore, when the key-on signal KON is generated, this signal KON is transmitted to the AND gate 22.
RS flip-flop 226 is set via 4. At this time, the output Q = "1" of the flip-flop 226 is supplied to the selector circuit 200 as the selection signal SA for selecting input A, so the selector circuit 200 selects the lower limit tempo data MIN as input A and locks the latch. circuit 216
supply to. Therefore, the latch circuit 216 latches the lower limit tempo data MIN in response to the read control signal NEXT. At the same time, the read control signal NEXT
causes the counter 166 to be reset, so that the counter 166 counts the tempo clock signal TCL again after the reset. In this case, the tempo clock signal TCL is generated based on the low speed clock signal _φ2 because the flip-flop 138 is reset by the output signal corresponding to A=B from the comparison circuit 164.

Next, case 2 is a case where the key-on signal KON is generated when the count value of the counter 166 reaches a certain value between NX0.5 and N, as shown in FIG. In this case as well, the key-on signal
Since the flip-flop 138 is set in response to KON, the frequency of the tempo clock signal TCL increases as in case 1. Also,
The method of generating the read control signal NEXT is also the same as in case 1. However, the read control signal NEXT
The data latched by the latch circuit 216 in response to this is different from case 1 and is the count output of the counter 196. This is because, as described above, the AND gate 210 generates the output signal = "1" when the key-on signal KON is generated.

Next, as shown in Figure 6 Case 3, the counter 1
A case will be described in which the key-on signal KON is generated when the count value of 66 should reach a certain value between N and NX1.5. In this case, when the count value of the counter 166 reaches N, the comparison circuit 16
Since the output signal corresponding to A<B of 4 becomes "0", the output signal of the NAND gate 150 becomes "0", and the sending of the tempo clock signal TCL from the AND gate 152 is stopped. Therefore, the counter 166 stops counting at the count value N, and the count value does not increase beyond N (in FIG. 6, the count values above N are shown for convenience of explanation). At this time, the output signal of the comparison circuit 164 corresponding to A=B becomes "1", and this state continues while the counter 166 is stopped. After this, the count value becomes
If the key-on signal KON is generated before reaching NX1.5, this signal KON will be connected to AND gate 176 and
It is sent out as read control signal NEXT via OR gate 192. In addition, since the output signal = "1" from the AND gate 210 makes the AND gate 212 conductive, the key-on signal KON is output from the AND gate 21.
2 to set the flip-flop 214. Therefore, the count output of the counter 196 is supplied to the latch circuit 216 via the selector circuit 200 and latched therein in response to the read control signal NEXT.

Next, as shown in Figure 6 Case 4, the counter 1
A case will be described in which the key-on signal KON is not generated even when the count value of 66 should reach NX1.5. In this case, as in case 3, when the count value reaches N, the counter 166 stops counting. Then, when the count value should reach NX1.5, the comparison circuit 204 outputs an output corresponding to A>B based on the comparison between the count output of the counter 196 as input A and the upper limit tempo data MAX as input B. Generates signal = “1”. This output signal = “1” is the AND gate 174 and OR gate 192
while causing the RS flip-flop 228 to be set. The output Q=“1” of this flip-flop 228 is a selection signal for selecting input C.
Since it is supplied to the selector circuit 200 as SC,
Selector circuit 200 selects upper limit tempo data MAX as input C and supplies it to latch circuit 216. Therefore, the latch circuit 216 latches the upper limit tempo data MAX in response to the read control signal NEXT.

After the first readout control signal NEXT is generated from the OR gate 192 as described above, a melody note length code signal MLG corresponding to the second melody tone is generated, and a melody key code signal MKC corresponding to the melody key code signal MKC is generated. A sound corresponding to the th melody tone is generated. Then, when the performer presses the key corresponding to the third melody tone at an appropriate timing as before, the second readout control signal NEXT is generated in the same manner as described above. In this case, the count value of the counter 166 is
If no key is pressed before NX1.5 should be reached, the second read control signal NEXT will be output to the comparator circuit 2.
It is generated in response to the output signal=“1” corresponding to A>B from 04.

At this time, the selector circuit 200 sends the lower limit tempo data MIN, the count output of the counter 196, or the upper limit tempo data MAX depending on whether the key press timing is early, appropriate, or late, so the latch circuit 216 is sent the second The output data from the selector circuit 200 is latched in response to the read control signal. Also, at this time, the output data of the selector circuit 200 is supplied to the averaging circuit 230 as input A, and the previous latch data from the latch circuit 216 is supplied to the latch circuit 230 as input B. Therefore, the averaging circuit 230 has inputs A and B.
The average processing of (A+B)/2 is applied to the signals and the resultant signals are supplied to the latch circuit 232. Therefore, latch circuit 232 latches the average data from average circuit 230 in response to the second read control signal NEXT and supplies it as input A to selector circuit 126. Note that the averaging circuit 230 is provided to prevent the tempo from changing frequently.

On the other hand, when the second read control signal NEXT is generated, the counter 156 generates an output signal="1". This output signal = “1” is the inverter 15
8 to make the AND gate 160 non-conductive, and the AND gate 128 to the selector circuit 1.
26 as a selection signal SA for selecting input A. Therefore, the selector circuit 126 selects the average data from the latch circuit 232 instead of the tempo data corresponding to the reference tempo from the selector circuit 122 and supplies it to the comparison circuit 132.

When the comparison circuit 132 is supplied with the average data from the latch circuit 232, the tempo clock signal
The TCL frequency is now determined according to the average value of the past two manual performance tempos, and the tempo of the various automatic performances mentioned above (musical sound generation or key press display) is variably controlled to follow the manual performance tempo. Ru. However, the tempo follow-up control in this case is not performed indefinitely, but is performed only within the variable range of the frequency of the tempo clock signal TCL. That is, the tempo clock signal
The highest frequency of TCL is determined by the high-speed clock signal φ ₁ and the lower limit tempo data MIN, and the lowest value is determined by the low-speed clock signal φ ₂ and the upper limit tempo data MAX. Therefore, the tempo of automatic performance is also determined by the highest frequency of the signal TCL It has a maximum value and a minimum value corresponding to the lowest frequency, respectively, and is controlled to follow the tempo of manual performance only within the range between the maximum value and the minimum value.

As described above, according to the present invention, the tempo of automatic performance is controlled by following the tempo of manual performance only when the tempo of manual performance on the keyboard is within a predetermined error range with respect to the reference tempo. Therefore, the following excellent effects can be obtained.

(1) It is possible to prevent the tempo of automatic performance from increasing abnormally if the key press timing is too early.

(2) If the key press timing is too late or no key is pressed, the automatic performance will not be stopped and will continue at a very slow tempo.

(3) Since the tempo variation range of automatic performance is limited, when practicing with automatic performance (musical sound generation or key press display), practice will not be interrupted by unnecessary tempo fluctuations. gone,
Improves practice efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic musical instrument according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the formats of melody data and accompaniment data, respectively, and FIGS. FIG. 5 is a detailed circuit diagram of the tempo control circuit of the electronic musical instrument, and FIG. 6 is a diagram for explaining the operation of the circuit shown in FIG. 5. DESCRIPTION OF SYMBOLS 10... Music score, 10a... Recording medium, 12... Music score data reading control circuit, 13... Tempo control circuit, 14
...melody data memory, 22...start/stop control circuit, 24...melody data reading circuit,
44...Display section, 50...Keyboard, 120...Manual tempo setting circuit, 122, 126, 136, 200
...Selector circuit, 124...Register circuit, 13
2,164,182,202,204...Comparison circuit, 134...Clock signal source, 146,166,
196... Counter, 206... Lower limit setting circuit, 20
8... Upper limit setting circuit.

Claims (1)

[Scope of Claims] 1. A keyboard, a musical sound generating means for generating a musical sound corresponding to a key pressed on the keyboard, a means for generating a tempo clock signal, and a means for automatically generating a musical sound or a key pressed based on the tempo clock signal. The electronic musical instrument is equipped with automatic performance means for performing display, and data generation means for generating reference tempo data indicating a reference tempo, and automatic performance means for performing manual performance using the keyboard based on the reference tempo data and key press signals from the keyboard. a determining means for determining whether the tempo is within a predetermined range with respect to the reference tempo; and based on an output signal from the determining means, if the tempo of the manual performance is within the range, the automatic performance is performed. the tempo of the automatic performance by the means to follow the tempo of the manual performance, and to prevent the tempo of the automatic performance from changing beyond a predetermined limit value when the tempo of the manual performance is not within the range; An electronic musical instrument characterized by comprising: control means for controlling the frequency of a tempo clock signal. 2. The electronic musical instrument according to claim 1, wherein the data generating means includes means for setting a reference tempo based on a manual operation. 3. In the electronic musical instrument according to claim 1, the data generating means includes a storage device that stores the reference tempo data, and a readout circuit that reads the reference tempo data from the storage device. An electronic musical instrument featuring