JPH01320554A - Memory readout circuit - Google Patents

Abstract

PURPOSE:To accelerate processing speed by re-arranging and outputting a specific bit in data read out from each of plural memory elements on which continuous memory addresses are allocated sequentially in prescribed sequence decided in advance. CONSTITUTION:When a perpendicular readout indicating signal to a controller 5 is valid, the controller 5 outputs chip select signals (105-108) to the memory elements (1-4) in spite of the contents of address signals 102 and 103 of low-order two bits, and outputs a driver select signal 113 to a driver 10. Here, only the most significant order bits of the data stored in the cells (1-4) are inputted to the driver 10 sequentially as perpendicular readout data (114-117). Thereby, it is possible to output the most significant order bits stored in continuous four addresses represented by an address signal 101 simultaneously, and to reduce the number of times of readout of the data from a memory in case of performing a bit test by a microprocessor, therefore, the processing speed can be accelerated.

Description

TECHNICAL FIELD The present invention relates to a memory read circuit, and more particularly to a memory read circuit used in an information processing device.

Conventionally, this type of memory successive readout circuit has a structure in which data from a memory designated by the same memory address is read out at once.

Conventional memory read circuits have a structure in which memory data specified by the same memory address is read out one after another at one time, so a microprocessor reads out one bit of data at a specific location from consecutive memory locations. When performing a bit test in which processing is performed repeatedly, the process of reading out one bit of data at a specific position for each memory address must be repeated, which has the disadvantage of impairing the speed of processing.

The present invention has been made to eliminate the drawbacks of the conventional lanterns as described above, and the present invention has been made to eliminate the drawbacks of the conventional lanterns as described above.
An object of the present invention is to provide a memory read circuit that can reduce the number of times data is read from a memory and improve processing speed when performing a test.

Summary of the Invention A memory read circuit according to the present invention comprises a plurality of memory elements to which consecutive memory addresses are sequentially assigned, and a specific bit of data read from each of the plurality of memory elements in a predetermined order. It is characterized by having an output means for rearranging and outputting.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 9, a memory read circuit according to an embodiment of the present invention includes memory elements 1 to 4, a controller 5, drivers 6 to 10 It is composed of:

Here, in FIG. 1, only the read portion of the memory is shown, and the write portion of the memory is omitted.

Further, the bit width of data stored in the memory is 4 bits.

Memory element 1 has addresses 4n (n=o, 1..

2, . . . ) are stored, and the memory element 2 stores data indicated by address 4n+1. Also, address 4n+2 is stored in memory element 3.
The data indicated by address 4n+3 is stored in the memory element 4.

An address signal 101 and chip select signals 105 to 108 from the controller 5 are input to the memory elements 1 to 4, respectively, and data specified by these address signals 101 and chip select signals 105 to 108 are input to the memory elements 1 to 4. is output from.

Drivers 6 to 10 each receive data from memory elements 1 to 4 and a driver select signal 109 from controller 5.
~113 are input, and driver select signals 109~
The data of the corresponding memory elements 1 to 4 from the drivers 6 to 10 specified by 113 are read data 118 to 1.
It is output as 20.

The controller 5 has an address signal 102 of the lower two bits.
．． 103 and a vertical read instruction signal 104 are input, and chip select signals 105 to 108 are output to the memory elements 1 to 4 based on these lower two bit address signals 102 and 103 and the vertical read instruction signal 104, and the drivers 6 to 10 driver select signals 109 to 113
Output.

Next, the operation of one embodiment of the present invention will be explained.

First, when the vertical read instruction signal 104 to the controller 5 is not valid, the controller 5 sends chip select signals 105 to 10 to the memory elements 1 to 4 selected by the lower two bits of the address signal 102 and 103.
8 is output, and driver select signals 109-112 are output to drivers 6-9 corresponding to the memory elements 1-4.

That is, the lower 2 bits of the address signal 102.103
If 'o, o', the chip select signal 105 is output to the memory element 1, the driver select signal 109 is output to the driver 6, and the data stored in the memory element 1 is read out as data 118 to 121. Output.

The lower 2 bits of address signals 102 and 103 are “0°1”.
”, the chip select signal 106 is sent to the memory element 2.
is output, and a driver select signal 110 is output to the driver 7.
is output, and the data stored in the memory element 2 is output as read data 118-121.

The lower 2 bits of the address signal 102.103 are 1°0"
If so, the chip select signal 107 is output to the memory element 3, the driver select signal 111 is output to the driver 8, and the data stored in the memory element 3 is output as read data 118-121.

The lower 2 bits of address signals 102 and 103 are “1°1”.
'', the chip select signal 108 is sent to the memory element 4.
is output, and a driver select signal 112 is output to the driver 9.
is output, and the data stored in the memory element 4 is output as read data 118-121.

As a result, data indicated by address signals 101-103 is read from memory elements 1-4, and the data is read out from drivers 6-9 to data 118-121.
is output as

Further, when the vertical read instruction signal 104 to the controller 5 is valid, the controller 5 sends the chip select L- signal to the memory elements 1 to 4, regardless of the contents of the lower two bits of the address signal 102 and 103. 105-1
08 and outputs a driver select signal 113 to the driver 10.

Here, only the most significant bit of the data stored in each memory element 1 to 4 is stored in the driver 10 as vertical read data 11.
4 to 117 are input in order, and the driver 10
, vertical read data 114 from memory element 1 is output as read data 118, vertical read data 115 from memory element 2 is output as read data 119, and vertical read data 116 from memory element 3 is output as read data 120. Vertical read data 117 from memory element 4 is output as read data 121.

Therefore, the most significant bit of the data stored in each of the four consecutive addresses indicated by the address signal 101 can be output at once, and when a bit test is performed by a microprocessor, the number of times data is read from the memory can be reduced. can be reduced.

In this way, consecutive memory addresses are divided and allocated to a plurality of memory elements 1-=,-4, and those memory elements 1-=,-4 are allocated.
By outputting the lowest bit of the data stored in memory 4 from the driver 10 at a time in a predetermined order, the microprocessor does not read 1 bit of data at a specific location from consecutive memories. When performing a bit test in which processing is repeated, the number of times data is read from the memory can be reduced, and the processing speed can be increased.

Note that in one embodiment of the present invention, the memory is composed of four memory elements 1
~4, and the most significant bit of the data stored in each of memory elements 1 to 4 is output at once, but the number of memory elements may be any number, and the data stored in each memory element may be output at once. It is clear that any data can be output at any one time, but is not limited thereto.

As explained above, according to the present invention, specific bits of data read from a plurality of memory elements to which consecutive memory addresses are sequentially assigned are arranged in a predetermined order. By outputting the data instead, when a bit test is performed by a microprocessor, the number of times data is read from the memory can be reduced and the processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1 to 4... Memory element 5... Controller L-Roller 6 to 10... Driver

Claims (1)

[Claims] (1) A plurality of memory elements to which consecutive memory addresses are sequentially assigned, and an output means for rearranging and outputting specific bits of data read from each of the plurality of memory elements in a predetermined order. A memory read circuit comprising: