JPH01308050A - Method of forming contact having low resistance with aluminum material and low resistance contact and integrated circuit multilayer structure provided by the method - Google Patents

Abstract

PURPOSE: To utilize an obtained structure for forming a multilayer conductive pattern for VLSI circuit by selectively depositing tungsten in a via hole within an insulator that is laminated on aluminum on a substrate at a wafer temperature within a specific range. CONSTITUTION: A test structure pattern used for a first metal level in a CMOS process is executed. In the process, a wafer is oxidized, aluminum layer containing aluminum or silicon is laminated by sputtering, and bimetal level is formed on the layer. Then, silicon oxide layer is deposited by the plasma enhance PECVD and a via hole to a lower-layer metal is formed by projection lithography and reactive ion etching. Then, tungsten is selectively deposited onto a metal by hydrogen reduction of tungsten hexafluoride into it at approximately 350 deg.C or higher and approximately 450 deg.C or lower for preventing a hillock from being formed on an aluminum structure. Thus, a tungsten plug with a low-resistance contact can be provided in a via hole, thus manufacturing an ultra-large-scale integrated circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to integrated circuits, particularly those with a diameter of 1 micron or less, or 2 microns or less.
The present invention relates to a method used in the manufacture of integrated circuits having submicron diameter via holes. More specifically, the present invention relates to a method for selectively depositing tungsten to exhibit low contact resistance to aluminum, and structures produced by the method. Accordingly, the present invention provides a mechanism for achieving low resistance contacts between metallization layers in integrated circuit devices, particularly very large scale integrated circuit devices.

[Prior art and problems to be solved by the invention] As the dimensions of circuit features used in integrated circuits have become smaller than 1 micron, insulating materials are needed to electrically connect conductors in different layers. The problem of getting metal into via holes is becoming increasingly difficult. It is desirable to reduce the via hole dimensions along with the circuit feature dimensions to maximize the density of devices on the chip. On the other hand, the thickness of the insulating layer that insulates one conductor layer from the other generally cannot be reduced proportionally to the reduction in lateral dimension to account for glabellar capacitance and the like. This situation results in a via hole with a depth-to-diameter ratio of 1.
Or it has increased to a value of 1 or more. It is difficult to effectively fill via holes with such high aspect ratios with conductive plug material. For example, even with wide-angle physical deposition methods such as sputtering, it is difficult to cover the walls of the via hole with enough metal to fill the via hole and provide the desired reliable circuit. However, chemical vapor deposition (CV)
D) In particular, selective CVD, which starts growth on the underlying conductor at the bottom of the via hole without growing on the insulator surface, is one way to solve this problem. A thick selective tungsten growth method has been used to fill the via holes in which the molybdenum first metallization layer was used. These methods have been found to exhibit low contact resistance due to the use of molybdenum. These methods include, for example, R,W, 5toll
) and R.H.Wils
Proceedings of the Multi-Level Metallization, Interconnection and Contact Technology Symposium (on)
of the Syposium on Multi
evel MeLalliza-tion, InLe
rconnectron and Contact
Proceedings of the Electrochemical Society, Pennington, New Jersey, pp. 232, D.M. Brown (D.M.
, Brown) et al.
ters) EDL-8, 55 (1987). These methods use a first metal layer, for example aluminum, and in the future it is desirable to add another metal layer, which also requires via holes to the aluminum pattern. . Additionally, most integrated circuit fabrication methods use aluminum or aluminum alloys as the first metal level, and thus integrated circuit fabrication processes with two metal levels require via holes into the aluminum pattern. Therefore, it is certainly desirable now and in the future to form reliable low resistance contacts with aluminum or its alloys through via holes in the insulating layer.

A problem with making low resistance contacts to aluminum with a second aluminum level is that the surface aluminum oxide must be removed, usually by a sputter etching process, before depositing the second aluminum level in the via hole. Previously published literature (T, Moriya et al.), IEEE Technical Digest (IEEE Technical D4g)
esL), IEDM (IEEE, New York, 1
(983) p. 550) report that tungsten selectively deposited on aluminum results in high contact resistance. This high contact resistance has also been confirmed by other researchers. It is desirable to achieve low contact resistance between selectively deposited tungsten and aluminum so that selective tungsten growth methods can be used to fill via holes, particularly into aluminum patterns in integrated circuits. It will be done.

SUMMARY OF THE INVENTION In accordance with a preferred embodiment of the present invention, there is provided a method for forming a low resistance contact with aluminum through a via hole in an insulator layered over the aluminum (particularly in an integrated circuit wafer). The method consists of selectively depositing tungsten into the via hole at a wafer temperature of about 350° C. or higher, but the temperature used is high enough not to damage the aluminum.

Specifically, the present invention shows that contact resistance changes significantly at critical temperatures between about 275°C and 350°C. Additionally, the present invention is preferably practiced at temperatures below about 450° C. to prevent hillock formation in the aluminum structure.

According to the method of the invention, structures with unique properties can be obtained. Specifically, the structure obtained according to the invention has approximately 2
It is equipped with a tungsten plug that exhibits a contact resistance of less than x 10-aΩ-ctM. The method of the invention and the structures obtained thereby are particularly useful for forming multilayer conductive patterns for VLS 1 circuits.

Therefore, a first object of the present invention is to deposit tungsten within the via hole to form a low resistance contact with the aluminum and/or aluminum alloy at the bottom of the via hole. be.

A second object of the present invention is to fabricate a very large integrated circuit device using via holes with a high stripe ratio.

A third object of the present invention is to provide a method for filling via holes having a large depth-to-diameter ratio.

A fourth object of the invention is to provide an apparatus for forming low resistance contacts between conductive layers within an integrated circuit device.

A fifth object of the present invention is to improve the efficiency of manufacturing multilayer integrated circuit devices, particularly multilayer integrated circuit devices using aluminum or aluminum alloys.

In summary, it is an object of the present invention to selectively deposit tungsten into via holes that are approximately 1 micron or less in diameter or less than 2 microns in diameter to form a low specific contact resistance with the aluminum and/or aluminum alloy at the bottom of the via hole. However, the purpose of the present invention is not limited thereto.

EXAMPLE A 4 inch diameter wafer was oxidized and then a layer of aluminum or aluminum containing 1% silicon was deposited by sputtering to a thickness of approximately 5000 nm. Two metal levels were formed on the layer. CM
A test structure pattern is applied to the first metal level in the OS process. Next, 0.4 μm or 0
．． 8 μm thick silicon oxide layer
It was deposited by ECVD at a temperature of about 380°C. Vias into the underlying metal were formed by projection lithography and reactive ion etching. The resist used was removed in a non-exothermic enzyme plasma system, and the wafer was heated in a heated PR5100O (Haker Chemical Company, J.D., PA, USA).
T, Baker Chemical Company
) products). Immediately before loading the wafers into the tungsten deposition system, some of the wafers are soaked in 71 ml of fluoride water.
aluminum for 30 seconds in a 1% solution of
Removed people. This etching is followed by a wash with deionized water. These wafers will be referred to as etching wafers from now on. The remaining wafers undergo no further processing and are referred to as non-etched wafers. After this conditioning, the wafers were loaded into one of four reactors for selective deposition of tungsten on metal using hydrogen reduction of tungsten hexafluoride.

One of the four reactors is a cold wall experimental setup, hereinafter referred to as R. Two of the four reactors were modified cold wall reactors of the type in which tungsten silicide is commercially available for blanket tungsten deposition. The two reactors are hereinafter referred to as GI and G2. The fourth reactor was a hot wall tube furnace of conventional design. This reactor will be referred to as T hereafter. All of these reactors were heated to the desired temperature in a hydrogen atmosphere under pressures ranging from about 0.4 to 1.3 Torr. With the exception of the tube furnace where only 0.1 μm of tungsten was deposited, tungsten hexafluoride was introduced for a time selected to approximately fill the via holes in the oxide to the underlying metal. For the tube furnace, the wafer temperature was assumed to be the temperature of a thermocouple inserted in the sheath inside the furnace. For the other reactors, the wafer was placed on the heated surface and was therefore heated from only one side, so at reduced pressure the wafer temperature was significantly lower than the temperature of the heated surface. For the four reactors, the wafer temperature was determined by Broa
dbent & Ramller), Journal of the Electrochemical Society (
Journal of the Electroche
micalSociety), vol, 131.1
427 (1984). Following tungsten deposition, the wafer was cleaned with PR51000 and a 0.8 μm thick layer of aluminum was sputtered over the wafer, followed by patterning to complete the circuit suitable for electrical testing. Finally, the wafer is heated to 400°C in hydrogen.
was annealed for 1 hour at a temperature of .

The contact resistance of the metal-1/tungsten plug/metal=2 structure was measured with a 1.8 μm diameter via hole using a Kelvin structure and four-point measurements. Table I shows the average value of measurements at 35 points or more on each wafer for the methods indicated in the table. As can be seen from Table 1, the experimental results indicate the criticality of the temperatures and/or depositions used herein.

It can be seen that as the temperature and deposition rate increase, the measured resistance decreases until the temperature reaches about 350''C or the deposition rate reaches about 120 Å/m. Above these values, the resistance remains approximately constant.

It has been shown that the adjustment of the surface of the underlying layer is not a controlling factor in obtaining the desired low contact resistance. Moreover, there is no appreciable difference in the results between using aluminum and using an aluminum alloy containing 1% silicon.

It is also noted that significant hillocks in aluminum are formed in the high temperature process, but not in the process at temperatures below 450°C. This is consistent with what was expected for these temperatures. By using aluminum alloys with other elements or deposited structures with aluminum, higher temperatures and associated higher deposition rates can be used without excessive hillock formation. In any event, it is desirable that the method performed herein not be performed at temperatures high enough to damage the aluminum structure.

Specifically, the methods performed herein are performed at temperatures below about 600°C. It is further desirable that the methods of the present application be conducted at temperatures below about 450° C. to avoid the formation of hillocks.

A structure made by the method of the invention is illustrated in the accompanying drawings. Specifically, a lower level metallization pattern 12 of aluminum or an aluminum alloy is deposited on a color-containing material layer 15, an insulating material layer 15 is deposited on a substrate 10, and an insulating material layer 15 is deposited on a substrate 10.
is typically made of a semiconductor material such as silicon. Further, on the metallization pattern 12,
A moat material layer 11 is deposited, and this insulating material layer 1
1 typically consists of silicon oxide. Further, in accordance with the method of the present invention, tungsten plugs 14 are deposited within the via holes in the insulating material layer 11 to form low resistance contacts with the metallization pattern 12. An upper level metallization pattern 13 is deposited;
It is patterned and connected to the tungsten plug 14. The bidirectional helmetization pattern 13 may be made of aluminum or other conductive materials than aluminum conventionally used in the fabrication of VLS1 circuits. Specifically, the upper layer metallization pattern 13 is made of molybdenum.

(Effects of the Invention) The method of forming a low-resistance contact with aluminum or aluminum alloy of the present invention can be effectively and easily carried out using conventional VLSI manufacturing equipment. It extends the effectiveness of deposited tungsten and significantly facilitates the fabrication of micron and submicron circuits.
This makes a significant contribution to the production of multilayer conductive patterns using single-circuit aluminum or aluminum alloys. This is a particularly desirable requirement of the present invention since aluminum is a desirable metallization material even without multiple layers. The method of the invention and the structure produced by the method achieve all of the objects of the invention set forth above.

The present invention has been explained in detail using preferred embodiments above, but
Many modifications and variations of this invention can be made by those skilled in the art. However, all such improvements and changes are included within the scope of the claims of the present application and fall within the true spirit and scope of the present invention.

[Brief explanation of the drawing]

The drawing shows a multilayer structure manufactured by the method of the invention. Explanation of Symbols 10 Substrate 11 - Insulating material layer 12 - = - Lower helmet layer 1
3 - Upper level metallization 3-in pattern 14
---Tungsten Plug 15-----One Insulating Material Layer Patent Applicant General Electric Company Sub-Agent Patent Attorney Hei 1) Tadao] Q
-, -,, -1 plate 11 - Insulating material layer 12 - Lower layer metallization pattern 13 - Upper layer metallization pattern 14 - Tungsten plug 15 - Insulating material layer

Claims (17)

[Claims] (1) A method of forming a low resistance contact with an aluminum material through a via hole in an insulating layer stacked on the aluminum material on a substrate, wherein tungsten is deposited in contact with the aluminum material in the via hole. A method for forming a low resistance contact with an aluminum material comprising: a tungsten deposition step, the deposition step being performed at a temperature above about 350° C., but not so high as to damage the aluminum material. 2. The method of claim 1, wherein the deposition temperature is less than about 600°C. 3. The method of claim 1, wherein the deposition temperature is not so high as to cause hillock formation. (4) The deposition temperature is lower than about 450°C.
A method for forming a low-resistance contact with an aluminum material as described in . The aluminum material of claim 1, further comprising: (5) pretreating the wafer in an acid bath to selectively etch the aluminum material through the via hole prior to the tungsten deposition step. low resistance contact formation method. (6) The method of forming a low resistance contact with an aluminum material according to claim 5, wherein the acid bath is hydrofluoric acid. 7. The method of claim 1, wherein said tungsten deposition is performed in a hot wall reactor. 8. The method of claim 1, wherein the tungsten deposition is performed in a cold wall reactor. (9) The method of forming a low resistance contact with an aluminum material according to claim 1, wherein the aluminum material contains silicon. 10. The method of claim 9, wherein the silicon is present in an amount of about 1 weight percent. 11. The method of claim 1, wherein said tungsten deposition step is performed at a deposition rate greater than about 120 Å/m. 12. The method of claim 1, wherein the tungsten deposition step is selective. (13) In a method of forming a low resistance contact with an aluminum material through a via hole in an insulating layer stacked on an aluminum material on a substrate, tungsten is deposited in contact with the aluminum material in the via hole. A low resistance contact made by a method of forming a low resistance contact with an aluminum material comprising a tungsten deposition step performed at a temperature above about 350° C. but not so high as to damage the aluminum material. (14) an aluminum material layer including a conductive pattern; an insulating layer stacked on the conductive pattern, having at least one via hole, and deposited to expose at least a portion of the aluminum material; Approximately 2×10＾-＾8Ω-
and a tungsten plug deposited within the via hole exhibiting a specific contact resistance of less than or equal to cm^2. 15. The multilayer structure for an integrated circuit according to claim 14, wherein the aluminum material contains silicon. 16. The multilayer structure for an integrated circuit according to claim 15, wherein said silicon is contained in an amount of about 1 weight percent. 17. The multilayer structure for an integrated circuit according to claim 14, further comprising a conductive pattern layer deposited to make electrical connection with the upper surface of the tungsten plug.