JPH01307272A - Manufacture of semiconductor non-volatile memory - Google Patents
Manufacture of semiconductor non-volatile memoryInfo
- Publication number
- JPH01307272A JPH01307272A JP63138728A JP13872888A JPH01307272A JP H01307272 A JPH01307272 A JP H01307272A JP 63138728 A JP63138728 A JP 63138728A JP 13872888 A JP13872888 A JP 13872888A JP H01307272 A JPH01307272 A JP H01307272A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- tunnel insulating
- insulating film
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ＩＣカードなどの記憶用デバイスとして用
いられている半導体不揮発性メモリの製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor nonvolatile memory used as a storage device such as an IC card.
この発明は、電気的消去可能な浮遊ゲート型半導体不揮
発性メモリにおいて、トンネル絶縁膜を酸化チッ化膜を
用いることにより、書換え回数の向上をはかったもので
ある。The present invention aims to improve the number of rewrites by using a nitride oxide film as a tunnel insulating film in an electrically erasable floating gate type semiconductor nonvolatile memory.
従来、第２図に示すように、プログラム端子であるトン
ネルドレイン領域２の上に約１００人のシリコン熱酸化
膜から成るトンネル酸化膜１６を設けた電気的書換え可
能な浮遊ゲート型半導体不揮発性メモリが知られていた
０例えば、Ｗ、 Ｓ。Conventionally, as shown in FIG. 2, an electrically rewritable floating gate type semiconductor nonvolatile memory has been provided with a tunnel oxide film 16 made of about 100 silicon thermal oxide films on a tunnel drain region 2 which is a program terminal. For example, W, S.
Ｊｏｈｎｓｏｎ ｅｔ ａｌ ”１６−にＥＥＰＩＩ
ＯＨｒｅｌｉｅｓ ｏｎ ｔｕｎｎｅｌｉｎ（ｌ ｆｏ
ｒ Ｍｔｅ−ｅｒａｓａｂｌｆ３１］ｒｏ（Ｊｒａｌ
５ｔＯｒａ（ｌｅ ’Ｅｌ１３ＣｔｒＯｎｉＣ３／Ｆｅ
ｂｒｔ＋ａｒＶ ２８（１９８０） ＋１１）１１３に
開示されている。Johnson et al.
OHrelies on tunnelin (l fo
r Mte-erasablf31]ro(Jral
5tOra(le 'El13CtrOniC3/Fe
brt+arV 28 (1980) +11) 113.
しかし、従来の半導体不揮発性メモリは、トンネル絶縁
膜として約１００人程度の熱酸化膜が用いられているた
めに、トンネルドレイン領域２と浮遊ゲート電［！７と
の間で、電荷のやりとり（即ち、プログラム動作）をす
ると、トンネル酸化膜１６が強電界ストレスにより偶発
的に破壊しやすいという欠点を有していた。However, in conventional semiconductor non-volatile memories, a thermal oxide film of about 100% is used as a tunnel insulating film, so the tunnel drain region 2 and the floating gate electrode [! 7, the tunnel oxide film 16 has the disadvantage that it is easily destroyed accidentally due to strong electric field stress.
そこで、この発明は、従来のこのような欠点を解決する
ために、プログラム動作により偶発破壊しない電気的書
換え可能な半導体不揮発性メモリを得ることを目的とし
ている。SUMMARY OF THE INVENTION In order to solve these conventional drawbacks, it is an object of the present invention to provide an electrically rewritable semiconductor nonvolatile memory that is not accidentally destroyed by programming operations.
上記課題を解決するために、この発明は、トンネル絶縁
膜を、高温熱チッ化により形成したチツ化シリコン膜を
＃、酸化した酸化チツ化膜を用いることにより、高電界
ストレスに強く、書換えによる偶発破壊を防止した。In order to solve the above problems, the present invention uses a silicon oxide film formed by oxidizing a silicon nitride film formed by high-temperature thermal nitridation as a tunnel insulating film, thereby making it resistant to high electric field stress and capable of resisting rewriting. Prevented accidental destruction.
〔実施例〕
以下に、この発明の実施例を図面にもとづいて説明する
。Ｎ型のメモリの場合について説明する。[Example] Below, an example of the present invention will be described based on the drawings. The case of N-type memory will be explained.
第１図（ｇ）が最終断面図であるが、Ｐ型シリコン基板
１の表面にお互いに間隔をおいてＮ１型のソース領域１
０とドレイン領域１１及びトンネル−ドレイン領域２が
形成されている。トンネルドレイン領域２の上には、部
分的にトンネル酸化チツ化膜６が設けられている。また
、ソース領域２とトンネルドレイン領域２との間の半導
体基板１の表面であるチャネル領域の上には、酸化膜３
が設けられ、さらに、その上にＣＶＤＶＤシリコンチツ
４が設けれらている。浮遊ゲート′ｒ＆極７は、トンネ
ル酸化チッ化膜５とＣＶＤＶＤシリコンチツ４の上に設
けられ、さらに、浮遊ゲート電極７の上には、制御ゲー
ト電極９が制御ゲート酸化膜８を介して設けられている
。FIG. 1(g) is the final cross-sectional view, and N1 type source regions 1 are spaced apart from each other on the surface of the P type silicon substrate 1.
0, a drain region 11 and a tunnel-drain region 2 are formed. A tunnel oxide film 6 is partially provided on the tunnel drain region 2 . Further, an oxide film 3 is formed on the channel region, which is the surface of the semiconductor substrate 1 between the source region 2 and the tunnel drain region 2.
is provided, and furthermore, a CVDVD silicon chip 4 is provided thereon. The floating gate 'r & electrode 7 is provided on the tunnel oxide nitride film 5 and the CVDVD silicon chip 4, and furthermore, a control gate electrode 9 is provided on the floating gate electrode 7 with a control gate oxide film 8 interposed therebetween. ing.
本発明のメモリの読み出し動作は、ソース領域１０とト
ンネルドレイン領域２との間のチャネル領域のコンダク
タンスが、浮遊ゲート電極７に含まれている電荷量によ
って変化することによって行なわれる。A read operation of the memory of the present invention is performed by changing the conductance of the channel region between the source region 10 and the tunnel drain region 2 depending on the amount of charge contained in the floating gate electrode 7.
また、情報のプログラムは、制御ゲート電＠９とドレイ
ン領域１１との間に高電圧を印加することにより、トン
ネル酸化チツ化膜６に高電界を集中させトンネル電流を
トンネルドレイン領域２と浮遊ゲート電極７との間に流
すことにより行うことかできる。In addition, the information is programmed by applying a high voltage between the control gate voltage @9 and the drain region 11, thereby concentrating a high electric field on the tunnel oxide film 6 and directing the tunnel current between the tunnel drain region 2 and the floating gate. This can be done by flowing the water between the electrode 7 and the electrode 7.
本発明のトンネル絶縁膜である酸化チツ化膜の製造方法
について説明する。A method for manufacturing a titanium oxide film, which is a tunnel insulating film of the present invention, will be explained.
まず、第１図（ａ）に示すように、基板１の全面に酸化
ＷＡ３及びＣＶＤシリコンチツ化Ｗ化種Ａ４成し、トン
ネル領域になる領域を、フォトリソ工程により第１図（
ｂ）のように、酸化膜３及びＣＶＤＶＤシリコンチツを
エツチングして基板１まで穴あけする０次に１００Ａ以
下の熱シリコンチッ化膜５を形成して、第１図（ｃ）の
ようにする。First, as shown in FIG. 1(a), oxidation WA3 and CVD silicon nitride W oxide seed A4 are formed on the entire surface of the substrate 1, and a region that will become a tunnel region is formed by a photolithography process as shown in FIG.
As shown in FIG. 1(c), the oxide film 3 and the CVDVD silicon chip are etched to form a thermal silicon nitride film 5 with a zero-dimensional temperature of less than 100 A by etching holes up to the substrate 1, as shown in FIG. 1(c).
次に、この熱シリコンチッ化膜５を９００℃以上の温度
で、Ｖ％酸化して、その上に、多結晶シリコン薄膜から
なる浮遊ゲート電極７を形成して、第１図（ｄ）のよう
にする０次に、１０００℃以上の高温で浮遊ゲート電極
７を酸化して制御ゲート酸化ＷＡ８を形成し第１図（ｅ
）のようにする、その上に、制御ゲート電ｆ！９を形成
し、第１図（ｆのように形成する。さらに、ソース領域
１０及びドレイン領域１１を浮遊ゲート電極７をマスク
にしてドーピングすることにより、第１図（ｇ）のメモ
リが完成する。Next, this thermal silicon nitride film 5 is oxidized by V% at a temperature of 900° C. or higher, and a floating gate electrode 7 made of a polycrystalline silicon thin film is formed thereon, as shown in FIG. 1(d). Next, the floating gate electrode 7 is oxidized at a high temperature of 1000° C. or higher to form the control gate oxide WA8.
), and on top of that, the control gate voltage f! 9 is formed as shown in FIG. 1(f).Furthermore, the source region 10 and drain region 11 are doped using the floating gate electrode 7 as a mask, thereby completing the memory shown in FIG. 1(g). .
本発明のトンネル絶縁膜である酸化チッ化膜６は、非常
に酸化速度の遅い、熱シリコンチッ化膜５を高温で長時
間で酸“化して形成するために、その品質は、従来のシ
リコン酸化膜に比べ優れている。その結果、書換えによ
るトンネル絶縁膜の破壊がきわめて少ないメモリが実現
できる。また、電気的書換え可能な半導体メモリの場合
、プログラム時に、ドレイン領域１１、あるいは、制御
ゲ、−ト電′Ｉ＃Ｉ８に約１０Ｖ以上の高電圧を印加す
る。The oxidized nitride film 6, which is the tunnel insulating film of the present invention, is formed by oxidizing the thermal silicon nitride film 5, which has a very slow oxidation rate, at high temperature for a long time, so its quality is comparable to that of conventional silicon. It is superior to oxide films.As a result, it is possible to realize a memory in which the tunnel insulating film is extremely less destroyed by rewriting.In addition, in the case of an electrically rewritable semiconductor memory, when programming, the drain region 11 or the control gate, - Apply a high voltage of about 10V or more to the electric current I#I8.
この電圧を制御する回路が、同一基板上に形成されてい
る０本発明のメモリにおいては、その高電圧制御用トラ
ンジスタのゲート絶縁膜として、チャネル領域上の酸化
膜３とＣＶＤＶＤシリコンチツ４との複合膜を用いるこ
とにより、ゲート耐圧の高いトランジスタを形成できる
。In the memory of the present invention in which a circuit for controlling this voltage is formed on the same substrate, a composite of an oxide film 3 on the channel region and a CVDVD silicon chip 4 is used as the gate insulating film of the high voltage control transistor. By using the film, a transistor with high gate breakdown voltage can be formed.
） また、制御ゲート酸化膜８は、１０００℃以上
の高温で、浮遊ゲート電極７の熱酸化により形成する、
この工程は、浮遊ゲート電極７か多結晶シリコンである
ため、その上の膜の品質を保つように高温熱酸化工程で
製造せざるをえない０本発明のメモリでは、トンネル絶
縁膜が酸化チッ化膜であるために、このような高温熱処
理工程があっても、トンネル絶縁膜の品質は劣化しない
、従来は、トンネル絶縁膜が、１００Ａ程度のシリコン
酸化膜で形成されていたために、この制御デー１ト酸化
工程により品質が低下するという問題があった。) The control gate oxide film 8 is formed by thermal oxidation of the floating gate electrode 7 at a high temperature of 1000° C. or higher.
In this process, since the floating gate electrode 7 is made of polycrystalline silicon, it must be manufactured using a high-temperature thermal oxidation process to maintain the quality of the film on it. Because it is a silicon oxide film, the quality of the tunnel insulating film does not deteriorate even with such a high-temperature heat treatment process. Conventionally, the tunnel insulating film was formed of a silicon oxide film of about 100A, so this control There was a problem in that the quality deteriorated due to the date oxidation process.
本発明のメモリは、制御ゲート電極９を浮遊ゲート電極
７の上に形成した例で説明したが、制御ゲート電′ｊＩ
ｉ！９は、基板１の表面に形成してもよい。Although the memory of the present invention has been described with an example in which the control gate electrode 9 is formed on the floating gate electrode 7, the control gate electrode ′jI
i! 9 may be formed on the surface of the substrate 1.
しかし、第１図のような構造のメモリに、特に適してい
る。即ち、酸化チッ化膜が高温工程に強いからである。However, it is particularly suitable for a memory having the structure shown in FIG. That is, this is because the nitride oxide film is resistant to high temperature processes.
この発明は、以上説明したように、トンネル絶縁膜とし
て、酸化チッ化膜を用いているために、後工程の制御ゲ
ート酸化の高温プロセスによる品質低下を防ぎ、書換え
回数の向上をする効果がある。As explained above, since this invention uses a nitride oxide film as a tunnel insulating film, it is effective in preventing quality deterioration due to the high-temperature process of control gate oxidation in the subsequent process and increasing the number of rewrites. .
第１図（ａ）〜（ｇ）は、この発明にかかる半導体不揮
発性メモリの製造方法の工程順断面図であり、第２図は
、従来の半導体不揮発性メモリの断面図である。
６・・・トンネル酸化チッ化膜
７・・・浮遊ゲート電極
１６・・・トンネル酸化膜
以上
出願人 セイコー電子工業株式会社FIGS. 1(a) to 1(g) are sectional views in the order of steps of a method for manufacturing a semiconductor nonvolatile memory according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor nonvolatile memory. 6...Tunnel oxide nitride film 7...Floating gate electrode 16...Tunnel oxide film and above Applicant: Seiko Electronics Industries, Ltd.
Claims (1)
前記酸化膜上にＣＶＤシリコンチッ化膜を形成する工程
と、トンネル領域となる領域に前記酸化膜及び前記ＣＶ
Ｄシリコンチッ化膜をエッチングする工程と、９００℃
以上の高温で熱チッ化する工程と、前記熱チッ化により
形成された熱チッ化膜を熱酸化する工程と、前記熱チッ
化膜を熱酸化した酸化チッ化膜上に浮遊ゲート電極を形
成する工程とから成り、前記トンネル領域上に形成され
た前記酸化チッ化膜をトンネル絶縁膜とする半導体不揮
発性メモリの製造方法。forming an oxide film on a first conductivity type semiconductor substrate;
forming a CVD silicon nitride film on the oxide film; and forming a CVD silicon nitride film on the oxide film and the CVD
D Etching process of silicon nitride film and 900℃
A process of thermally nitriding at the above-mentioned high temperature, a process of thermally oxidizing the thermal nitride film formed by the thermal nitride, and forming a floating gate electrode on the nitride oxide film obtained by thermally oxidizing the thermal nitride film. A method for manufacturing a semiconductor nonvolatile memory, comprising the step of: using the nitride oxide film formed on the tunnel region as a tunnel insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138728A JP2696103B2 (en) | 1988-06-06 | 1988-06-06 | Manufacturing method of semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138728A JP2696103B2 (en) | 1988-06-06 | 1988-06-06 | Manufacturing method of semiconductor nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01307272A true JPH01307272A (en) | 1989-12-12 |
| JP2696103B2 JP2696103B2 (en) | 1998-01-14 |
Family
ID=15228770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63138728A Expired - Lifetime JP2696103B2 (en) | 1988-06-06 | 1988-06-06 | Manufacturing method of semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2696103B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7619274B2 (en) | 2004-06-23 | 2009-11-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
| US7883967B2 (en) | 2005-07-25 | 2011-02-08 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device, semiconductor device and manufacturing method of nonvolatile semiconductor memory device |
-
1988
- 1988-06-06 JP JP63138728A patent/JP2696103B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7619274B2 (en) | 2004-06-23 | 2009-11-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
| US7985650B2 (en) | 2004-06-23 | 2011-07-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
| US7883967B2 (en) | 2005-07-25 | 2011-02-08 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device, semiconductor device and manufacturing method of nonvolatile semiconductor memory device |
| US8093126B2 (en) | 2005-07-25 | 2012-01-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device, semiconductor device and manufacturing method of nonvolatile semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2696103B2 (en) | 1998-01-14 |
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