JPH01295182A - Scan path circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a diagnostic circuit for LSI internal circuits, and in particular to a scan path circuit using a scan-in/out method, which allows LSSD shift I registers and latches to be configured with fewer transistors. The purpose of the present invention is to provide a scan path circuit, which is configured to connect a plurality of memory elements in the semiconductor integrated circuit in series to form a shift register and transfer serial test data during the diagnostic mode of the semiconductor integrated circuit. In the scan path circuit, a first tarlocked circuit writes test data inputted from a scan-in terminal to each of the memory elements in response to a scan clock signal, and a first tarocked circuit writes test data inputted from a scan-in terminal to each of the memory elements, and scans the dead data written to the memory elements. A second clocked circuit is attached thereto for reading data in accordance with a clock signal and outputting the read data to the scan-in terminal of the first tallied circuit attached to the subsequent memory element.

[Industrial application field]

The present invention relates to a diagnostic circuit for LSI internal circuits, and particularly to a scan path circuit using a scan-in/out method.

With the rapid development of semiconductor technology, the scale of integration of LSI or VLSI is increasing. The larger the scale of the agglomeration, the L
It becomes difficult to diagnose whether the internal circuit of the SI operates as designed. A scan path circuit is known as a method for diagnosing LSI internal circuits. A scan path circuit is a circuit in which a large number of flip-flops (storage elements) inside an LSI are connected in series by switching mode signals in order to operate them separately from the original operation of the LSI during the manufacturing stage of the LSI. These are series loops connected to form a shift register.

During diagnosis, test data (logic "1" or "O") is input from the scan-in terminal of the scan path circuit in synchronization with the tarok signal (hereinafter referred to as the scan clock signal) to form shift 1 to registers. Write to each flip frog sequentially. Since the internal state of an LSI is generally held in a flip-flop (register), the internal state of the LSI can be arbitrarily set from the outside by changing its contents through scan-in. On the other hand, when it is desired to check the internal state of an LSI, the internal state is generally scanned out by inputting a scan clock after stopping the system clock so that the internal state does not change.

By using the above two methods, it is possible to check for failures such as malfunctions, failures, and design errors in the internal circuits of LSIs.

[Conventional technology]

Example of conventional scan path circuit (DIGIT^1. LO
GICTESTING AND 5IH (ILAT
ION, P273 ~275Jiq7.17゜Harp
er & RoW, published by Publishers Inc. (by exander former cgo) is shown in FIG.

In FIG. 9, each register REG1 to REG constituting the LSI internal circuit is connected to a multiplexer MUX.
1 to MUXn are provided in parallel. The L
During normal operation of the SI, input data Di1 to Dio are processed in parallel and written to the respective registers REG1 to REG, and then output data D is generated. They are output in parallel as 1 to Do0. Select signal SEL in diagnostic mode
is input to each multiplexer MUX1 to MUXn.

The input terminals of multiplexers MUX1 to MUX are scan-in terminals SC,.

Switch to the side. By this switching, register REG
The output of REG2 is connected to the next register REG2, and then RE
The output of G is connected to REG3, and so on, forming a series circuit that connects each of the registers RE'G1 to REGn in a chain. This chain circuit will form a serial shift register. And scan-in terminal S
By inputting the test data Dtes to C, , and inputting the shift clock, the test data Dtes
t is written in each register REG1 to REGo. This is the scan-in operation.

Next, by applying a shift clock, the test data Dtest written in each register R, EG1 to REGo is serially read out from the scan access terminals SC, o. The above is the scan-out operation.

The above scan-in/out method uses LSI at the time of diagnosis.
However, there is a problem in that the circuit shown in FIG. 7 cannot necessarily convert a sequential circuit into a combinational circuit. For example, this is the case when the flip-flops (registers RE01-R, EGn) to be diagnosed are asynchronously set and reset, or when the input of the tarok signal depends on data. So, scan in/
In the out method, L S S D (1, evel
The concept of ``-8ensistive 5can l)sign'' is used as essential. LSSD is a level sensitive scan path.
This is a circuit in which the response is determined by the combination of input test data, regardless of the order in which the input test data changes.

FIG. 10 shows a conventional example of shift 1 register latch (S R1, ) using the LSSD concept (DIGITAL
l-OGICTESTING AND 5IHtl
LAT1ON, P276 ~280. Fig.

7.20. tlarper & Rom, Public
Published by shers Jnc, AIeXander Hi
cgo-1').

This shift register latch corresponds to one flip-flop, and consists of a latch L1 that acts as a storage element during normal operation of the LSI, and a latch L2 that operates during diagnosis. During normal operation, this circuit receives the clock signal CK3 from the terminal C and outputs the input data D from the output terminal. and■ Output. Tarock signal CK during scan-in operation
Test data Dtest input from the scan-in input terminal SC is written to the latch nJ-2. During the scan-out operation, the clock signal CK2 is applied to the terminal B and the data of l-1 or L
2, the data is read out, and outputted from the output terminal 5Cout.

When using CMO3+- transistors, this shift 1~ register latch has 10 NAND gates I~ and 40 transistors, and 2 inverters and 8 transistors, totaling 4
Requires 8 transistors.

[Problem to be solved by the invention]

Although the LSSD shift register latch is superior in that it can scan in/out accurately, it has the problem of requiring a large number of component transistors. In LSIs with limited space, this firstly leads to a decline in the functionality of the LSI, and secondly,
This leads to a decrease in wafer yield.

That is, the first point is as follows.

The integration density of an LSI is determined by the chip area, and on the same chip surface, the above-mentioned shift registers and latches are mounted together with ROM and RAM as internal circuits of the LSI, and a control circuit is also mounted. When many elements are mounted in such a limited space, using many transistors in the configuration of the shift register/latch inevitably limits the functions of other ROMs, RAMs, etc.

Regarding the second point, it is as follows. If a shift register latch is similarly implemented while maintaining the LSI function, the area of one chip must be increased. If the chip area is large, there is a high probability that dust and the like will fall during the pattern formation process on the wafer and the chip will be defective. As a result, the yield of wafers decreases rapidly.

An object of the present invention is to provide a scan path circuit in which an LSSD shift register/latch can be constructed using fewer transistors.

[Means to solve the problem]

A diagram of the principle of the present invention is shown in FIG. According to the present invention, when the semiconductor integrated circuit LSI is in the diagnostic mode, the semiconductor integrated circuit 1? '
Multiple storage elements (inverter latches) M1 in gLsI
~M0 are connected in series to form a shift register, and serial test data Dtest is transmitted through this shift register.
In the scan path circuit configured to transfer the data, the scan in terminals SC, .
a first clocked circuit ioo, ~1 for writing the test data Dtest inputted to the memory cells M1~M;
00 and the test data Dtest to be written into the memory elements M1-M are read out by the clock signal CK2 to the scan array 1, and the first clocked circuit 1ioo attached to the memory elements M2-Mo connected to the subsequent stage is read out.
,~1. The second signal transferred to the scan-in terminal of OO-0
It is constructed by combining the clocked circuits B200-1 to B200-0.

[Effect]

In normal mode (original operation of the LSI), scan-in clock signal cK1 and scan-out clock signal CK2 are negated, and normal clock signal CK3 is applied to normal control line A3. This normal clock signal CK3 is applied to each memory element M1 to M.
Data Di1 to Dio are written in parallel in synchronization with . Note that this writing is performed by the third clocked circuit 300. ~
300-n. And each memory element M1
~Data D written to M. 1 to Doo are read out in parallel as necessary.

In the diagnostic mode, the normal clock signal CK3 is negated, and the scan-in clock signal CK1 and scan-out clock signal CK2 are connected to the scan-in control line A.
1, applied to scanout control line A2. The relevant LS
Test data Dtest is applied to the scan-in terminal SC1 of I.
When n is input, the test data Dtest is input to the first clocked circuit 100-1. First clocked circuit 100
writes the test data Dtest into the first storage element M1 at the timing of the scan in clock signal CK1. The written test data D is read out by the second tallied circuit 200-1 at the est timing of the scan-out clock signal CK2, and then read out by the first tallied circuit 100-2 at the next stage by the scan-in clock signal CK1. The test data Dtest written to M2 is sequentially transferred and finally outputted from the scan-out terminal 5Cout.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

An example in which the present invention is applied to a micro ROM 400 as an LSI and an output latch (invert clutch) Ml of the micro ROM as a storage element is shown below.

The shift register latch, which is a component of the scan path circuit, includes a storage element M, a third clocked circuit 300 paired with this, a first clocked circuit 100 added thereto, and a second clocked circuit 200. , consists of.

Figure 2 shows a micro ROM to which the present invention is applied.
400 output latch configuration is shown. In FIG. 2, the output data D of the micro ROM 400 is transmitted to the third clocked circuit 300. is written to the inverter latch M1 via the inverter latch M1 as output data D.
The output is 0.

Third tallied circuit 300. has a clocked inverter CINV, one clock terminal of which is connected to the normal control line A3 via the inverter INV1, and the other clock terminal of which is directly connected to the normal control line A3.

Inverter clutch M1 is connected to inverter Nv2 (Fig. 7 (
(c)) and the large R inverter Nv3 (see FIG. 7(b)) are connected in antiparallel to form a so-called flip-flop type latch circuit. This large R inverter Nv3 is constructed by complementary-connecting transistors with large mutual conductance gm.

Data is input to the inverter latch M1 at the timing of the normal clock signal CK3 applied to the normal control line A3.

Next, the first locked circuit 100-1 at the first stage will be explained as an example of the first clocked circuit, but each of the first clocked circuits at the subsequent stage in the scan path circuit also has the same configuration, so the explanation thereof will be omitted. do.

As shown in FIG. 3, the first clocked circuit 100-1 has a clocked inverter CI N connected between the scan-in terminal SC, . and the input terminal of the inverter latch M1.
It has Vl. The clocked inverter CIN1 is an inverter using C0M5) transistors, and has a total of four transistors (see FIG. 7(a)). One clock terminal of the clocked inverter CINV1 is connected to the scan-in control line A1 via the inverter Nv6, and the other clock terminal is directly connected to the scan-in control line A1.

In the first clocked circuit 100-1, when the scan in clock signal CK1 is applied, the clocked inverter CI is synchronized with the clock timing.
NVl is opened and one bit of test data Dtest is written to invert clutch M1.

Next, the second clocked circuit will be explained using the first stage as an example. Note that each of the second clocked circuits at the subsequent stage has a similar configuration, and the explanation thereof will be omitted.

As shown in FIG. 3, the second clocked circuit 200 connects the output terminal of the inverter latch M1 and the skin-out terminal SC.
clocked inverter CIN connected between o and 1
■It has 2. This clocked inverter CIN■
2 is similarly composed of CMOS transistor inverters, and the number of transistors is four in total (see FIG. 7(a)). One clock terminal of the clocked inverter CIN2 is connected to the scan-out control line A2 via the inverter IN4. The other clock terminal is directly connected to scanout control line A2.

In the second clocked circuit 200-1, when the scan out signal CK2 is applied, the clocked inverter CTNv2 opens in synchronization with the clock timing, and the test I/data Dtest previously written to the inverter latch M1 is opened. The data is read out and transferred to the clocked inverter of the first clocked circuit 100 connected to the next stage.

As described above, each of the inverter clutches M1 to M0 has two clocked circuits, namely, the first clocked circuit ioo, ~100-0 and the second clocked circuit 20.
0-1 to 200-, are added to each inverter latch M
The shift register latches configured as shown in FIG. 1 to Mn scan path circuit elements, ie, shift register latches, are of dynamic type.

These shift register latches are connected in series to form a shift register, thereby forming a scan path loop within the LSI. FIG. 4 shows an embodiment of the series scan path circuit formed in this manner.

This FIG. 4 is expressed in correspondence with the conventional scan path circuit (FIG. 9). The details of each element are as described above, so the explanation will be omitted.

Next, the operation will be briefly explained.

In the normal operation mode, scan-in clock signal CK1 and scan-out clock signal CK are negated, and only normal clock signal CK3 is provided. Each input data Di1 to D is synchronized with this normal clock signal.
1° or third clocked circuit 300. .about.300-n to inverter latches M1 to M, respectively, in parallel. The written data is read as necessary,
Output data D. 1-D. , will be output.

In scan mode (diagnosis mode), normally clock signal C
Switching occurs when K is negated. Scan-in clock signal CK1 and scan-out clock signal CK2
and are non-overlapping in time and are given at different timings (see Figure 8).

When the scan-in clock signal CK1 is applied, the test data D applied to the scan-in input terminals SC, .
is written to the inverter latch M1 via the first clocked circuit 100-1est, and a scan-in operation is performed.

Next, when the scan-out clock signal CK2 is applied, the test data Dtest written in the inverter latch M1 is read out, and the second clocked circuit 200-
1 to the next stage first clocked circuit 100-2.

Next, when the scan in clock signal CK1 is applied, the test data D transferred from the previous stage is transferred to the first clocked circuit 100. is written to the inverter latch M2 via the est inverter latch M2. At this time, another test data Dtest newly inputted to the scan-in terminals SC, , is written to the inverter latch M1 via the first tallied circuit 100 at the first stage.

Next, when the scan-out clock signal CK2 is applied, the test data Dtest written in the inverter latch M2 is transferred to the first clocked circuit 100-3 of the next stage.
will be forwarded to. At this time, at the same time, inverter latch M1
The new test data Dtest written in is transferred to the next first clocked circuit 100-2.

Thereafter, in the same manner, the test data Dtes is sequentially applied to each inverter latch M1 to M in synchronization with the scan-in clock signal CK1 and the scan-out clock signal CK2.
o is serially shifted.

According to the first embodiment described above, the shift register latch is constructed by simply adding two clocked circuits, the first clocked circuit ioo, ~100, and the second clocked circuit 200-i~n 200. can do. Each clocked circuit consists of one clocked inverter (four transistors) and one inverter (two transistors), so the number of additional transistors per shift register may be 12.

As a result, the conventional shift register latch (Figure 10)
In contrast to the case in which a total of 48 transistors were required, in the case of this embodiment (FIG. 2), a total of 22 transistors can be used. In this way, a scan path circuit can be constructed with a very small number of transistors.

is the first clocked circuit i in the first embodiment (Fig. 2)
oo, inverter INV6, second clocked circuit 20
The inverter INV4 of 01 is omitted and the number of control lines is increased in its place.

That is, the clocked inverter CINV1°CINv
The scan in clock signal CK1 and the scan in clock signal CK2 applied to the inverted clock terminals of INV6. INV4, but each control line A1 . This is given by A2.

With this configuration, two inverters are omitted in each shift register latch, and a total of four transistors are not required in terms of the number of transistors. Therefore, one shift register latch can be made up of 18 transistors. It is possible. However, since the number of control lines increases by two, in terms of layout design, it is better to consider the advantages and disadvantages of the first embodiment and implement the one that reduces the chip area.

A third embodiment of the present invention is shown in FIG. 6. Each of the shift registers and latches shown in the first and second embodiments (Figures 2 to 5) is of a so-called dynamic type, and if the clock signal stops for a predetermined period of time or more, data will be destroyed. requires a clock signal. In contrast, this embodiment discloses a static type shift register that does not cause data destruction even if the tarock signal is stopped in the middle of a scan.

As shown in FIG. 6, the output stage of the clocked inverter CINV2 of the third clocked circuit 300 includes an inverter INV7. An inverter latch L by INV8 is interposed. This inverter latch holds and stabilizes the logic at the output end of the clocked inverter CIN3, and holds that value until the next signal change.

In this way, by configuring the static type, the test data Dtest can be scanned in to the shift register latch at any position, and can also be scanned out from the shift register latch at any position. This will lead to easier diagnosis of specific areas.

The rest of the configuration is the same as that in FIG. 2, so a description thereof will be omitted.

According to the first to third embodiments described above, the number of transistors constituting the LSSD shift register/latch can be significantly reduced. This means that when many functional elements must be implemented in a limited space such as in one LSI chip, the transistors required for the scan path circuit can be used for other functions such as increased ROM capacity, increased RAM capacity, etc. ), which substantially increases the functionality per LSI chip. Alternatively, when looking at the same functions, the chip size can be reduced by that much, and the yield can be improved. As described above, the present invention is suitable not only for manufacturing LSIs but also particularly for VLSIs.

[Effects of the Invention] As described above, according to the present invention, an LSSD shift register/latch can be constructed with a very small number of transistors, and an LSI.

Contributes to improving VLSI integration density.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram of an output latch of a micro ROM, Fig. 3 is a circuit diagram showing a first embodiment of the present invention, and Fig. 4 is a first embodiment of the present invention. Connection diagram of a scan path circuit according to an example; FIG. 5 is a circuit diagram showing a second embodiment of the present invention; FIG. 6 is a circuit diagram showing a third embodiment of the present invention; FIG. 7 is a symbol of each circuit element. Fig. 8 is an explanatory diagram of the scan clock signal, Fig. 9 is a circuit diagram of a conventional scan path circuit, and Fig. 10 is a conventional LSS circuit.
FIG. 3 is a circuit diagram of a D shift register/latch. 100, ~1oo-0...first tallied circuit, 20
0, ~200-0...second clocked circuit, 300-
i~300-n...Third clocked circuit, SC...
・Scan-in terminal, n 5Cout...Scan-out terminal, CK1...Scan clock signal, CK2...Scan clock signal, CK3...Normal clock signal, A1...Scan-in control line, A2...・Scanout control line, A3... Normal control line, M1~M,... Memory element (inverter latch), Di
1~Din...Input data, D. 1~Doo...Output data, CINV~CINv3...Clocked inverter. (a) (b) (C) Transistor

Claims (1)

[Claims] During the diagnosis mode of a semiconductor integrated circuit (LSI), a plurality of memory elements (M_1 to M_n) in the semiconductor integrated circuit are connected in series to form a shift register, and serial test data (D_t_e_s_t) is generated. In the scan path circuit configured to transfer a scan clock signal (CK_1) to each of the storage elements, a scan in terminal (SC
Test data (D_t_e_) input from _i_n)
A first clocked circuit (100_-_1 to 100_-_n) writes the test data written in the memory element to the scan clock signal (
A second clocked circuit (200_-_1 to 200_-_n) that reads the data by CK_2) and outputs it to the scan-in terminal of the first clocked circuit attached to the subsequent storage element.
A scan path circuit characterized by being attached with and.