CN115078956A - Test circuit - Google Patents

Abstract

A test circuit includes a plurality of normal flip-flops and an improved flip-flop. Each of the plurality of normal flip-flops includes a first input pin, a second input pin and a first output pin, and is used for selectively temporarily storing the first input pin according to a scan enable signal The input value or the input value of the second input pin. The improved flip-flop includes a third input pin, a fourth input pin and a second output pin respectively coupled to a black box circuit, the plurality of normal flip-flops and a plurality of combinational logic circuits , and is used to selectively temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Description

test circuit

technical field

The present disclosure relates to a test circuit for an integrated circuit, and more particularly, to a test circuit for testing an integrated circuit including a memory.

Background technique

With the development of semiconductor process technology, an integrated circuit (IC, Integrated Circuit) includes digital logic circuits and many embedded memories (eg, TCAM/TCM, RAM, SRAM). Generally speaking, the integrated circuit also includes a memory built-in self-test (MBIST, Memory Build-in Self-test) circuit for testing embedded memory and a scan chain test (scan chain test) for testing digital logic circuits. circuit.

However, the conventional scan chain test circuit includes a by-pass circuit for bypassing the memory and a multiplexer for selectively outputting the output signal of the memory or the output signal of the bypass circuit, the bypass circuit This often leads to problems of increased circuit area and routing congestion in integrated circuits, while multitasking circuits are prone to delay the output signal of the memory, thereby causing timing violations.

SUMMARY OF THE INVENTION

One aspect of the present disclosure is a test circuit. The test circuit is used for testing an integrated circuit, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits, and the test circuit includes a plurality of normal flip-flops and an improved flip-flop. Each of the plurality of normal flip-flops includes a first input pin, a second input pin and a first output pin, and is used for selectively temporarily storing the first input pin according to a scan enable signal The input value or the input value of the second input pin. The improved flip-flop includes a third input pin, a fourth input pin and a second output pin respectively coupled to the black box circuit, the plurality of normal flip-flops and the plurality of combinational logic circuits bit, and is used to selectively temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

In conclusion, by coupling the improved flip-flop that receives the scan test mode signal to the output end of the memory, the test circuit of the present disclosure can omit the conventional bypass circuit and the multiplexer coupled to the output end of the memory. As a result, the circuit area can be reduced, the problem of routing congestion is less likely to occur, and the delay of the output signal of the memory can be reduced (avoiding the problem of timing violation). In addition, since the test circuit can still complete the scan test when the number of components is reduced, the test yield of the integrated circuit can be improved, and the cost of the scan test can be reduced.

Description of drawings

1 is a schematic diagram illustrating an integrated circuit tested via automatic test equipment in accordance with some embodiments of the present disclosure.

2 is a schematic diagram illustrating an integrated circuit including a test circuit according to some embodiments of the present disclosure.

FIG. 3 is a schematic diagram illustrating a built-in self-test circuit of a memory according to some embodiments of the present disclosure.

4 is a schematic diagram illustrating another integrated circuit including a test circuit according to some other embodiments of the present disclosure.

5 is a schematic diagram illustrating another integrated circuit including a test circuit according to some other embodiments of the present disclosure.

Detailed ways

The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the specific embodiments described are only used to explain the present case, and are not used to limit the present case, and the description of the structural operations is not used to limit the order of its execution. The recombined structures, resulting in devices with equal efficacy, are within the scope of the present disclosure.

Terms used throughout the specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the content of this disclosure and in the specific content.

As used herein, "coupling" or "connection" may refer to two or more components in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also refer to two or more components Components interact or act on each other.

In addition, the "combinational logic circuit" used herein refers to a circuit composed of various logic gates, and the "normal flip-flop" and "modified flip-flop" used herein refer to a circuit different from the combinational logic The "sequential logic circuit" of the circuit.

Please refer to FIG. 1, which depicts that an integrated circuit 1 on a chip (not shown) can be tested by automatic test equipment ATE located outside the chip. As shown in FIG. 1 , the integrated circuit 1 includes a memory 10 , a plurality of combinational logic circuits (to simplify the description, only one combinational logic circuit CL is shown in FIG. 1 ) and a test circuit according to some embodiments of the present disclosure 50, wherein the memory 10, the combinational logic circuit CL and the test circuit 50 are coupled to each other. When testing the integrated circuit 1, the automatic test equipment ATE generates a known test vector TV, inputs the test vector TV to the integrated circuit 1 through the scan input terminal SI on the chip, and receives the test circuit 50 through the scan output terminal SO on the chip The scan output value SOV is used to judge whether the combinational logic circuit CL is normal. In addition, the test circuit 50 can also test whether the memory 10 is normal.

Referring to FIG. 2 , in some embodiments, the test circuit 50 includes a plurality of normal flip-flops (to simplify the description, only five normal flip-flops FF1 - FF5 are shown in FIG. 2 ), at least one modified flip-flop MFF, a built-in self-test circuit 20 in memory, a multiplexer MUX, and a feedback circuit FB. The test circuit 50 can selectively operate in a scan test mode (to test the combinational logic circuits on the integrated circuit 1 ) or a memory built-in self test mode ( to test the memory 10 on the integrated circuit 1).

As shown in FIG. 2 , the normal flip-flops FF1 ˜ FF5 each include a first input pin D1 , a second input pin SI1 , a first enable pin SE1 and a first output pin Q1 , and are respectively used for according to a The scan enable signal Sen (connected to the first enable pin SE1 ) selectively temporarily stores the input value of the first input pin D1 or the input value of the second input pin SI1 . The improved flip-flop MFF includes a third input pin D2, a fourth input pin SI2, a second enable pin SE2 and a second output pin Q2, and is used for the scan test mode signal Ms (consistent with the second can be connected to pin SE2) to selectively temporarily store the input value of the third input pin D2 or the input value of the fourth input pin SI2. When the test circuit 50 operates in the scan test mode, the scan test mode signal Ms will always be kept at the first level (eg, a high level). However, the scan enable signal Sen is set to a first level or a second level (eg, a low level) according to whether the test circuit 50 is currently in a shift or capture stage.

Structurally, the first input pin D1 of the normal flip-flop FF1 is coupled to the combinational logic circuit CL2, and the second input pin SI1 of the normal flip-flop FF1 is coupled to the first output pin Q1 of the normal flip-flop FF3 (To simplify the description, the normal flip-flop FF3 in FIG. 2 only shows the first output pin Q1 ), the first enable pin SE1 of the normal flip-flop FF1 is used to receive the scan enable signal Sen, and the normal flip-flop FF1 is used to receive the scan enable signal Sen. The first output pin Q1 of the device FF1 is coupled to the fourth input pin SI2 of the improved flip-flop MFF.

The first input pin D1 of the normal flip-flop FF2 is coupled to the combinational logic circuit CL3, and the second input pin SI1 of the normal flip-flop FF2 is coupled to the second output pin Q2 of the improved flip-flop MFF. The first enable pin SE1 of the flip-flop FF2 is used for receiving the scan enable signal Sen, and the first output pin Q1 of the normal flip-flop FF2 is coupled to other combinational logic circuits (not shown).

In other embodiments, the first output pin Q1 of the normal flip-flop FF2 can be coupled to other combinational logic circuits (not shown in the figure) and the normal flip-flop (not shown in the figure) at the same time.

The third input pin D2 of the modified flip-flop MFF is coupled to the output end of the memory 10 , and the fourth input pin SI2 of the modified flip-flop MFF is coupled to the first output pin Q1 of the normal flip-flop FF1 , the second enable pin SE2 of the modified flip-flop MFF is used to receive the scan test mode signal Ms, and the second output pin Q2 of the modified flip-flop MFF is coupled to the second input of the normal flip-flop FF2 Pin SI1 and combinational logic circuit CL1.

In the embodiment shown in FIG. 2 , the built-in self-test circuit 20 is coupled to the second output pin Q2 of the improved flip-flop MFF and the multiplexer MUX. Referring to FIG. 3 , the built-in self-test circuit 20 includes a comparison logic circuit 210 , a processing circuit 220 and a test vector generator 230 . Specifically, the comparison logic circuit 210 is coupled to the second output pin Q2 of the improved flip-flop MFF, the processing circuit 220 is coupled to the comparison logic circuit 210, and the test vector generator 230 is coupled to the processing circuit 220 and multiple Tasker MUX.

As shown in FIG. 2, the first input terminal of the multiplexer MUX is coupled to the built-in self-test circuit 20, the second input terminal of the multiplexer MUX is coupled to the combinational logic circuit CL4, and the The output terminal is coupled to the input terminal of the memory 10 and the feedback circuit FB.

The first input pin D1 of the normal flip-flop FF4 is coupled to the feedback circuit FB, and the second input pin SI1 of the normal flip-flop FF4 is coupled to the first output pin Q1 of the normal flip-flop FF5 (for simplicity of description) 2, the normal state flip-flop FF5 only indicates the first output pin Q1), the first enable pin SE1 of the normal state flip-flop FF4 is used to receive the scan enable signal Sen, and the first enable pin of the normal state flip-flop FF4 An output pin Q1 is coupled to the combinational logic circuit CL4.

In another embodiment, the combinational logic circuit CL4 in FIG. 2 may not exist. At this time, the first output pin Q1 of the normal flip-flop FF4 is directly coupled to an input terminal of the multiplexer MUX (for example, the second input terminal of the multiplexer MUX), which does not affect the operation of the present invention. .

Since the memory bypass (by-pass) circuit has been removed, in order to test the combinational logic circuit CL4 and the multiplexer MUX, the output of the multiplexer MUX is fed back to any normal flip-flop by adding a feedback circuit FB (eg : The first input pin of the normal flip-flop FF4). The feedback circuit FB is coupled to the output end of the multiplexer MUX, the first input pin D1 of the normal state flip-flop FF4 and a logic circuit (not shown in the figure), wherein the logic circuit can be a combinational logic circuit or a normal state flip-flop. Specifically, the feedback circuit FB includes a first logic gate L1 and a second logic gate L2. The first input terminal of the first logic gate L1 is used for receiving the scan test mode signal Ms, and the second input terminal of the first logic gate L1 is coupled between the output terminal of the multiplexer MUX and the input terminal of the memory 10 . The first input end of the second logic gate L2 is coupled to the output end of the first logic gate L1, the second input end of the second logic gate L2 is coupled to the logic circuit, and the output end of the second logic gate L2 is coupled to On the first input pin D1 of the normal flip-flop FF4.

Regarding the "normal flip-flop" used in the embodiment, its first input pin (eg, the first input pin D1) is usually coupled to the combinational logic circuit of the previous stage, and its second input pin (For example: the second input pin SI1) is usually coupled to the output pin of the flip-flop of the previous stage, and its enable pin (for example: the first enable pin SE1) is usually used to receive the scan enable signal Sen, and its output pin (for example: the first output pin Q1) is usually coupled to the input pin of the combinational logic circuit or/and the flip-flop of the next stage to form a scan chain ).

Regarding the "improved flip-flop" used in the embodiment, the first input pin (eg, the third input pin D2) is usually coupled to the output end of the memory 10, and the second input pin ( For example, the fourth input pin SI2) is usually coupled to the output pin of the flip-flop of the previous stage, and its enable pin (for example, the second enable pin SE2) is usually used to receive the scan test mode signal Ms , and its output pin (eg: the second output pin Q2 ) is usually coupled to the combinational logic circuit of the next stage, the input pin of the flip-flop of the latter stage or/and the built-in self-test circuit 20 of the memory.

In the initial stage of the test, the test circuit 50 operates in the scan test mode to test all the combinational logic circuits in the integrated circuit 1 . When the test circuit 50 operates in the scan test mode, the scan test mode signal Ms has a first level (eg, a high level). Since the built-in self-test circuit 20 also has combinatorial logic circuits that can be tested, the level of the built-in self-test mode signal Mb does not need to be particularly limited.

During the scan test performed by the scan chain technology, the detection process includes a shift and a capture phase. The test vector TV generated by the automatic test equipment ATE is input to a first-stage normal flip-flop (not shown) in the test circuit 50 during the displacement phase. In some embodiments, the test vector TV consists of a preset number of "0 (logical zero)" and "1 (logical one)" arrangements, and the automatic test equipment ATE will be set according to each flip-flop in the test circuit 50. The value of determines the arrangement of "0" and "1".

First, the test circuit 50 operates in the displacement phase in the scan test mode. At this time, the scan test mode signal Ms has a first level, and the scan enable signal Sen has a first level. In this way, the normal flip-flops FF1-FF5 on the integrated circuit 1 each read the input value of the second input pin SI1 according to the scan enable signal Sen of the first level (that is, the output of the previous stage of flip-flops). value). The improved flip-flop MFF reads the input value of the fourth output pin SI2 (ie, the output value of the previous-stage flip-flop) according to the scan test mode signal Ms of the first level. Also as shown in FIG. 2 , the normal flip-flops FF1 to FF5 and the improved flip-flop MFF both receive the frequency signal CLK. With the triggering of each periodic pulse in the frequency signal CLK, the normal flip-flops FF1 to FF5 and the improved flip-flop MFF will each continuously read the output value of the previous stage of flip-flops, and at the same time store the previously stored values. Output to the next-stage flip-flop. At the end of the displacement phase, the values in the test vector TV for each flip-flop in the test circuit 50 will be set to each flip-flop in the test circuit 50 . The action at this stage is to initialize the values of all flip-flops.

For example, the values for the modified flip-flop MFF and the normal flip-flop FF2 in the test vector TV generated by the automatic test equipment ATE may be [0, 1]. It is assumed that in one cycle of the clock signal CLK, the values stored in the normal flip-flop FF3 and the normal flip-flop FF1 are "0" and "1", respectively. In the next cycle, the normal flip-flop FF1 will store the previously temporarily stored value "0" of the normal flip-flop FF3, and the modified flip-flop MFF will store the previously temporarily stored value of the normal flip-flop FF1 "1" ". In addition, the normal flip-flop FF2 will store the previously temporarily stored value (eg "0") of the modified flip-flop MFF. In the next cycle, that is, at the end of the displacement phase, the modified flip-flop MFF will store the previously temporarily stored value "0" of the normal flip-flop FF1, and the normal flip-flop FF2 will store the modified flip-flop MFF. The previously buffered value "1".

Next, the test circuit 50 operates in the acquisition phase in the scan test mode. At the beginning of the acquisition stage, each combinational logic circuit in the integrated circuit 1 will perform operations according to the values set by the flip-flop of the previous stage in the displacement stage, and generate output values. When the test circuit 50 operates in the acquisition stage in the scan test mode, the scan test mode signal Ms still has the first level, and the scan enable signal Sen has the second level (eg, low level). Different from the displacement stage, the normal flip-flops FF1-FF5 on the integrated circuit 1 each read the input value of the first input pin D1 according to the scan enable signal Sen of the second level (that is, the combinational logic of the previous stage). output value of the circuit). With the triggering of the pulse in the frequency signal CLK, the normal flip-flops FF1 to FF5 will each obtain and record the output value of the previous stage combinational logic circuit, while the improved flip-flop MFF is still based on the scan test mode signal Ms of the first level. Read the output value of the normal flip-flop FF1. At this time, if the improved flip-flop MFF reads the output value of the memory 10 through the third input pin D2 as in the prior art, unpredictable memory data will be obtained, which reduces the test fault coverage. Therefore, in the present invention, the enable pin of the improved flip-flop MFF is changed to be coupled to the scan test mode signal Ms to improve the test error coverage.

Since the memory bypass circuit has been removed, the output of the combinational logic circuit (eg, the combinational logic circuit CL4 shown in FIG. 2 or the combinational logic circuit in the memory built-in self-test circuit 20 ) coupled to the input terminal of the memory 10 The value cannot be transmitted to the next-stage flip-flop (ie, the modified flip-flop MFF) through the bypass circuit, so that the automatic test equipment ATE cannot test all the combinational logic circuits. It is worth noting that the test circuit 50 can feed back the output value of the combinational logic circuit coupled to the input end of the memory 10 to the normal flip-flop FF4 through the feedback circuit FB, so that the automatic test equipment ATE can test the coupling through the normal flip-flop FF4. A combinational logic circuit connected to the input end of the memory 10 .

Specifically, when the test circuit 50 operates in the acquisition stage, the multiplexer MUX selectively outputs the combination in the memory built-in self-test circuit 20 according to the built-in self-test mode signal Mb of the first level or the second level. The output value of the logic circuit or the output value of the combinational logic circuit CL4. In some embodiments, the first logic gate L1 is an AND gate, and the second logic gate L2 is an OR gate. The first logic gate L1 outputs the output value of the multiplexer MUX according to the scan test mode signal Ms of the first level, and the second logic gate L2 performs operation according to the output value of the first logic gate L1 and the output value of the logic circuit , to output a feedback value (not shown in the figure) to the first input pin D1 of the normal flip-flop FF4.

After the acquisition phase is completed, the test circuit 50 operates in the displacement phase again. In this way, the output values of each combinational logic circuit in the integrated circuit 1 can be sequentially transmitted to each flip-flop in the test circuit 50, and finally output through the scan output SO, and received by the automatic test equipment ATE to judge the integration. Whether each combinational logic circuit in circuit 1 can operate normally. In addition, the feedback value can be sequentially transmitted from the normal flip-flop FF4 to the following stages of flip-flops, so that the automatic test equipment ATE can determine the combinational logic coupled to the input end of the memory 10 by receiving the feedback value Is the circuit normal.

In some embodiments, while the output values of each combinational logic circuit in the integrated circuit 1 are output, another set of values in another test vector TV generated by the automatic test equipment ATE can also be obtained from the scan input terminal SI according to The sequence is stored to each flip-flop in the integrated circuit 1 for another test. In other words, the test circuit 50 can alternately operate in the displacement phase and the acquisition phase until all the combinational logic circuits in the integrated circuit 1 are tested.

After testing all combinational logic circuits in the integrated circuit 1 , the test circuit 50 then operates in a memory built-in self-test mode to test the memory 10 . When the test circuit 50 operates in the memory built-in self-test mode, the scan test mode signal Ms has a second level, and the built-in self-test mode signal Mb has a first level. As shown in FIG. 3 , the processing circuit 220 controls the test vector generator 230 to generate a memory test pattern TP. The multiplexer MUX receives and outputs the memory test pattern TP according to the built-in self-test mode signal Mb of the first level. The memory 10 receives the memory test pattern TP to output a memory output value MOV. The improved flip-flop MFF reads the input value of the third input pin D2 (ie, the output value of the memory 10 ) according to the scan test mode signal Ms of the second level, to output the memory output value MOV to the built-in self-test of the memory circuit 20.

Also as shown in FIG. 3 , the comparison logic circuit 210 receives the memory output value MOV, and compares the memory output value MOV with an expected value (not shown in the figure) to generate a comparison result. The processing circuit 220 selectively controls the test vector generator 230 to generate another memory test pattern TP or directly outputs an error signal Err according to the comparison result. Specifically, when the comparison result indicates that the memory output value MOV is equal to the expected value, the processing circuit 220 controls the test vector generator 230 to generate another memory test pattern TP to further test the memory 10 . When the comparison result indicates that the memory output value MOV is different from the expected value, the processing circuit 220 directly outputs the error signal Err to the internal register of the chip (not shown in the figure), and the automatic test equipment ATE can use the I/O bus (Not shown in the figure) Read the content of the internal register of the chip to obtain the wrong test result, so as to judge that the memory 10 has an abnormal condition.

Please refer to FIG. 4 , which depicts a schematic diagram of another integrated circuit 2 . The integrated circuit 2 has a similar structure to the integrated circuit 1 and can likewise be tested by automatic test equipment ATE located outside the chip. Different from the integrated circuit 1, the test circuit 50 on the integrated circuit 2 does not include the feedback circuit FB, but also includes a normal-state flip-flop FF6. In order to solve the problem that the combinational logic circuit coupled to the input end of the memory 10 cannot be tested, the normal flip-flop FF6 is coupled between the output end of the multiplexer MUX and the input end of the memory 10 . Structurally, the first enable pin SE1 of the normal flip-flop FF6 is coupled to the scan enable signal Sen, the first input pin D1 of the normal flip-flop FF6 is coupled to the output end of the multiplexer MUX, and the normal state The second input pin SI1 of the flip-flop FF6 is coupled to the first output pin Q1 of another normal-state flip-flop (not shown). In this way, the output value of the combinational logic circuit coupled to the input end of the memory 10 can be temporarily stored in the normal flip-flop FF6 (through the first input pin D1) during the acquisition stage, and sequentially transmitted to the shift stage during the shift stage. The flip-flops connected in series are finally transmitted to the scan output terminal SO so that the automatic test equipment ATE can receive the output value of the combinational logic circuit coupled to the input terminal of the memory 10 . The automatic test equipment ATE can determine whether the combinational logic circuit CL4 and the multiplexer MUX operate normally according to the output value. The remaining structures and operations of the embodiment shown in FIG. 4 are the same as or similar to the foregoing embodiments, and are not repeated here.

In another embodiment, the memory built-in self-test circuit 20 does not need to exist, and the multiplexer MUX coupled to the input end of the memory 10 does not need to exist or can be regarded as being incorporated into the combinational logic circuit CL4. . The above two modified applications do not affect the operations of the improved flip-flop MFF, the feedback circuit FB and the normal-state flip-flop FF6 in FIG. 4 in the present invention. Those skilled in the art can understand the implementation details of the related art, so they are not repeated here.

In another embodiment, the memory 10 in the foregoing embodiments may be any circuit (ie, black box circuit) that cannot apply scanchain tests, for example, the memory 10 may be an analog circuit or a scanchain that cannot be chained ( scan chain) digital circuits.

Please refer to FIG. 5 , which depicts a schematic diagram of yet another integrated circuit 3 . The integrated circuit 3 has a similar structure to the integrated circuit 1 and can likewise be tested by automatic test equipment ATE located outside the chip. Different from the integrated circuit 1, the test circuit 50 on the integrated circuit 3 includes another modified flip-flop besides the modified flip-flop MFF1 (equivalent to the modified flip-flop MFF shown in FIG. 2 ). MFF2 and normal flip-flop FF7. Structurally, the third input pin D2 of the modified flip-flop MFF2 is coupled to the output end of the memory 10, and the fourth input pin SI2 of the modified flip-flop MFF2 is coupled to the first output of the normal flip-flop FF7 The pin Q1, the second enable pin SE2 of the improved flip-flop MFF2 is used to receive the scan test mode signal Ms. In addition, the memory built-in self-test circuit 20 is changed to be coupled to the second output pin Q2 of the modified flip-flop MFF2 instead of being coupled to the second output pin Q2 of the modified flip-flop MFF1. The remaining structures and operations of the embodiment shown in FIG. 5 are the same as or similar to those of the foregoing embodiments, and are not repeated here.

To sum up, by coupling the improved flip-flop MFF that receives the scan test mode signal Ms to the output end of the memory 10, the test circuit 50 of the present disclosure can omit the conventional bypass circuit and many more coupled to the output end of the memory. task circuit. In this way, the circuit area of the integrated circuits 1 to 3 is reduced, the problem of routing congestion is less likely to occur, and the delay of the output signal of the memory 10 is reduced (a timing violation problem is avoided). In addition, since the test circuit 50 can still complete the scan test when the number of components is reduced, the test yield of the integrated circuit can be improved, and the cost of the scan test can be reduced.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope of the appended patent application.

【Symbol Description】

1, 2, 3: integrated circuits

10: memory

20: Memory built-in self-test circuit

50: Test circuit

210: Compare Logic Circuits

220: Processing Circuits

230: Test Vector Generator

ATE: Automatic Test Equipment

CL, CL1, CL2, CL3, CL4, CL5: Combinational logic circuits

CLK: frequency signal

D1: the first input pin

D2: The third input pin

Err: Error signal

FF1, FF2, FF3, FF4, FF5, FF6, FF7: normal flip-flops

FB: Feedback Circuit

L1: first logic gate

L2: second logic gate

MFF, MFF1, MFF2: Improved flip-flops

Ms: scan test mode signal

Mb: Built-in self-test mode signal

MOV: memory output value

MUX: Multitasker

SE1: The first enable pin

SE2: The second enable pin

Sen: scan enable signal

SI: scan input

SI1: The second input pin

SI2: the fourth input pin

SO: scan output

SOV: Scan Out Value

TV: test vector

TP: Memory Test Pattern

Q1: The first output pin

Q2: The second output pin.

Claims (10)

1. A test circuit for testing an integrated circuit, wherein the integrated circuit comprises a black box circuit and a plurality of combinational logic circuits, and the test circuit comprises: A plurality of normal flip-flops, wherein the plurality of normal flip-flops respectively include a first input pin, a second input pin and a first output pin, and are used for selectively temporarily temporarily according to a scan enable signal storing the input value of the first input pin or the input value of the second input pin; and An improved flip-flop includes a third input pin, a fourth input pin and a second output respectively coupled to the black box circuit, the plurality of normal flip-flops and the plurality of combinational logic circuits The pin is used for selectively temporarily storing the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal. 2. The test circuit of claim 1, wherein the third input pin is coupled to an output end of the black box circuit, and the fourth input pin is coupled to a first one of the plurality of normal flip-flops The first output pin of a normal state flip-flop, the second output pin is coupled to a first combinational logic circuit of the plurality of combinational logic circuits and a second normal state of the plurality of normal state flip-flops the second input pin of the flip-flop. 3. The test circuit of claim 2, wherein when the test circuit operates in a displacement stage in a scan test mode, the scan enable signal has a first level, and the scan test mode signal has a first level Three-level, the first normal flip-flop temporarily stores and outputs the output value of a third normal flip-flop among the plurality of normal flip-flops according to the scan enable signal of the first level. The improved formula The flip-flop temporarily stores and outputs the output value of the first normal-state flip-flop according to the scan test mode signal of the third level, and the second normal-state flip-flop is based on the scan enable signal of the first level The output value of the improved flip-flop is temporarily stored and output. 4. The test circuit of claim 3, wherein when the test circuit operates in an acquisition stage in the scan test mode, the scan enable signal has a second level different from the first level, The scan test mode signal has the third level, and the first normal flip-flop temporarily stores an output value of a second combinational logic circuit among the plurality of combinational logic circuits according to the scan enable signal of the second level , the improved flip-flop temporarily stores the output value of the first normal state flip-flop according to the scan test mode signal of the third level, and the second normal state flip-flop according to the scan test mode signal of the second level The enable signal temporarily stores an output value of a third combinational logic circuit among the plurality of combinational logic circuits. 5. The test circuit of claim 2, wherein a fourth combinational logic circuit in the plurality of combinational logic circuits is coupled to the input end of the black box circuit and a fourth combinational logic circuit in the plurality of normal flip-flops Between normal flip-flops; The fourth combinational logic circuit includes a multiplexer. 6. The test circuit according to claim 5, further comprising a feedback circuit, wherein the feedback circuit is coupled to the output end of the fourth combinational logic circuit and the first input pin of the fourth normal-state flip-flop and a logic circuit; When the test circuit operates in a scan test mode, the feedback circuit calculates a feedback value according to the output value of the fourth combinational logic circuit and the output value of the logic circuit, and outputs the feedback value to the fourth normal positive state the first input pin of the inverter; When the test circuit is not operating in the scan test mode, the feedback circuit outputs the output value of the logic circuit to the first input pin of the fourth normal-state flip-flop. 7. The test circuit of claim 6, wherein the feedback circuit comprises a first logic gate and a second logic gate, a first input terminal of the first logic gate receives the scan test mode signal, the first logic gate The second input end of the gate is coupled between the output end of the fourth combinational logic circuit and the input end of the black box circuit, and the first input end of the second logic gate is coupled to the output end of the first logic gate , the second input end of the second logic gate is coupled to the logic circuit, and the output end of the second logic gate is coupled to the first input pin of the fourth normal state flip-flop. 8. The test circuit of claim 5, wherein the first output pin of the fourth normal-state flip-flop in the plurality of normal-state flip-flops is coupled to the fourth combinational logic circuit, the plurality of normal-state flip-flops A fifth normal-state flip-flop in the flip-flops is coupled between the output end of the fourth combinational logic circuit and the input end of the black box circuit; When the test circuit operates in an acquisition stage of a scan test mode, the scan enable signal has a second level, and the fifth normal-state flip-flop temporarily stores the scan enable signal according to the scan enable signal of the second level the output value of the fourth combinational logic circuit; When the test circuit operates in a displacement stage of a scan test mode, the scan enable signal has a first level different from the second level, and a sixth normal state of the plurality of normal state flip-flops The inverter is coupled to the second input pin of the fifth normal state flip-flop, and the fifth normal state flip-flop temporarily stores and outputs the sixth normal state flip-flop according to the scan enable signal of the first level. output value. 9. The test circuit according to claim 2, wherein the black box circuit is a memory; Wherein the test circuit further includes a built-in self-test circuit for the memory, which is used for outputting a test pattern for testing the memory, and is coupled to the improved flip-flop; Wherein the test circuit further includes another improved flip-flop including a fifth input pin, a sixth input pin and a third output pin, and is used for selectively temporarily storing the test signal according to the scan test mode signal The input value of the fifth input pin or the input value of the sixth input pin. 10. The test circuit of claim 9, wherein the fifth input pin is coupled between the output end of the memory and the third input pin of the improved flip-flop, and the sixth input pin coupled to the first output pin of a seventh normal flip-flop among the plurality of normal flip-flops, the third output pin is coupled to the memory built-in self-test circuit; The test circuit further includes a multiplexer, wherein a first input terminal of the multiplexer is coupled to the memory built-in self-test circuit to receive the test pattern, and a second input terminal of the multiplexer is coupled to a fourth combinational logic circuit among the plurality of combinational logic circuits.

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