JPH01293661A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01293661A JPH01293661A JP63126572A JP12657288A JPH01293661A JP H01293661 A JPH01293661 A JP H01293661A JP 63126572 A JP63126572 A JP 63126572A JP 12657288 A JP12657288 A JP 12657288A JP H01293661 A JPH01293661 A JP H01293661A
- Authority
- JP
- Japan
- Prior art keywords
- base
- groove
- layer
- collector
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000012212 insulator Substances 0.000 claims abstract description 6
- 238000000926 separation method Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000005192 partition Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/40—Vertical BJTs
- H10D10/421—Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に間する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor devices.
従来、多数の高耐圧バイポーラトランジスタを同一半導
体基板上に構成するには、比較的厚い（１０〜２５μｍ
）Ｎ型エピタキシャル層をＰ型半導体基板上に設けてい
た。その高耐圧トランジスタの他素子との電気的絶縁は
、Ｐ＋型埋込層３と半導体表面より拡散し形成したＰ＋
型拡散層５をぶつけて、絶縁を確保していた。Conventionally, in order to configure a large number of high-voltage bipolar transistors on the same semiconductor substrate, a relatively thick (10 to 25 μm)
) An N-type epitaxial layer was provided on a P-type semiconductor substrate. The high voltage transistor is electrically insulated from other elements by a P+ type buried layer 3 and a P+ layer formed by diffusion from the semiconductor surface.
Insulation was ensured by bumping the mold diffusion layer 5.
第５図は従来のバイポーラトランジスタの一例の断面図
である。FIG. 5 is a cross-sectional view of an example of a conventional bipolar transistor.
Ｐ型半導体基板１にＮ＋型埋込層２、Ｐ＋型埋込層３を
設けた後、Ｎ型エピタキシャル層４を堆積する ｐ ′
″型絶縁拡散層５で絶縁分離してＮ型の島領域を形成し
た後、酸化膜６を形成する。通常の方法によりＰ型ベー
ス７、Ｎ＋型のエミッタ８、コレクタコンタクト９、チ
ャネルストッパー１０を形成し電極配線１１を形成する
。After providing an N+ type buried layer 2 and a P+ type buried layer 3 on a P type semiconductor substrate 1, an N type epitaxial layer 4 is deposited p'
After forming an N-type island region by insulating and separating it with a "" type insulating diffusion layer 5, an oxide film 6 is formed.A P-type base 7, an N+ type emitter 8, a collector contact 9, and a channel stopper 10 are formed by a conventional method. are formed to form the electrode wiring 11.
前述のチャネルストッパーの役割について考案する。 Let us consider the role of the channel stopper mentioned above.
第６図は第５図のＣ部拡大図である。FIG. 6 is an enlarged view of section C in FIG.
通常、Ｐ型半導体基板１は最低電位に接続されている。Normally, the P-type semiconductor substrate 1 is connected to the lowest potential.
そして、今、高耐圧パイボーラトランジスタのワースト
バイアス状態として、コレクタ領域４を最高電位に、又
、ベース領域７を最低電位にした時のことを考える。こ
の時、ベース７−絶縁拡散層５間で電気的につながって
いるのを防止できれば問題がな０゜
上記の様に電圧が印加されたとすると、空乏層が形成さ
れる。第６図で番号２１はベースコレクタ間に形成され
な空乏層の端を、番号２２は半導体基板を含む絶縁拡散
層−コレクタ間に形成された空乏層の端を、番号２３は
Ｎ型エピタキシャル層表面にできた反転層を示す、この
反転層２３は高耐圧トランジスタを得るためエピタキシ
ャル層４の濃度を比較的低く （１０”ａｍ’程度）し
であるためできやすいが、これを抑えるためＮ“型のチ
ャネルストッパー１０を設けてあり、この中では不純物
濃度が高濃度であるなめチャネルが急に止まっている。Now, let us consider a case where the collector region 4 is set to the highest potential and the base region 7 is set to the lowest potential as the worst bias state of the high-voltage piborar transistor. At this time, there is no problem as long as electrical connection between the base 7 and the insulating diffusion layer 5 can be prevented.If a voltage is applied as described above, a depletion layer is formed. In FIG. 6, number 21 indicates the end of the depletion layer formed between the base and collector, number 22 indicates the end of the depletion layer formed between the insulating diffusion layer including the semiconductor substrate and the collector, and number 23 indicates the end of the depletion layer formed between the collector and the insulating diffusion layer including the semiconductor substrate. This inversion layer 23, which represents an inversion layer formed on the surface, is easy to form because the concentration of the epitaxial layer 4 is relatively low (about 10 am') in order to obtain a high voltage transistor. A type channel stopper 10 is provided in which a diagonal channel with a high impurity concentration is abruptly stopped.
以上が高耐圧バイポーラトラジスタのチャネルストッパ
ーの働きであるが、この構造の欠点は、ベース７と絶縁
拡散層５との間の距離が非常に長くなる点にある０例え
ば、６０Ｖ程度の電位を印加した時、エピタキシャル層
４の比抵抗が数Ω・Ｃ程度であれば、拡散の拡がりも考
慮すると、約５０μｍ程度と大きくなる。The above is the function of the channel stopper of a high voltage bipolar transistor, but the drawback of this structure is that the distance between the base 7 and the insulating diffusion layer 5 is very long. If the resistivity of the epitaxial layer 4 is about several Ω·C when a voltage is applied, the resistivity will be as large as about 50 μm, taking into account the spread of diffusion.
本発明は、−導電型半導体基板に一導電型絶縁分離層で
分離された逆導電型素子領域が形成され、該素子領域内
にバイポーラトランジスタが形成されている半導体装置
において、前記トランジスタのベースと前記絶縁分離層
との間に溝が形成され、該溝が絶縁物で埋められれこと
により構成される。The present invention provides - a semiconductor device in which an element region of opposite conductivity type separated by an insulating separation layer of one conductivity type is formed on a conductivity type semiconductor substrate, and a bipolar transistor is formed in the element region; A groove is formed between the insulation layer and the insulation separation layer, and the groove is filled with an insulator.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of a first embodiment of the present invention.
第５図に示した従来例と同様に、半導体基板１に高耐圧
バイポーラトランジスタを設ける。ただし、本実施例で
は、高耐圧バイポーラトランジスタを電気的に絶縁分離
するための絶縁拡散層５とトランジスタのベース７との
間のコレクタ領域（エピタキシャル層４）に表面から２
本の渭１２を掘り、絶縁物でその溝１２を埋め、その溝
２の間にＮ＋型のチャネルストッパーを設ける。この溝
１２は、ベース７及びコレクタコンタクト９を２本の溝
で取囲んである。Similar to the conventional example shown in FIG. 5, a high breakdown voltage bipolar transistor is provided on the semiconductor substrate 1. However, in this embodiment, the collector region (epitaxial layer 4) between the insulating diffusion layer 5 for electrically isolating the high voltage bipolar transistor and the base 7 of the transistor is
The edges 12 of the book are dug, the grooves 12 are filled with an insulator, and an N+ type channel stopper is provided between the grooves 2. This groove 12 surrounds the base 7 and the collector contact 9 with two grooves.
第２図は第１図（ｂ）のＢ部拡大図である。FIG. 2 is an enlarged view of part B in FIG. 1(b).
第２図を参照して再び高耐圧バイポーラトランジスタの
ワーストバイアス状態を考えると、ベース−コレクタ間
の空乏層２１は絶縁物で埋っな溝１２ａで止められ、又
、半導体基板１から絶縁拡散層に到る絶縁領域−コレク
タ間の空乏層２２は溝１２ｂで止められる。従って、ベ
ースと絶縁領域が導通してしまうことはない。Considering again the worst bias condition of the high voltage bipolar transistor with reference to FIG. The depletion layer 22 between all the insulating regions and the collector is stopped by the groove 12b. Therefore, electrical conduction between the base and the insulating region will not occur.
ここで、Ｎ＋チャネルストッパー１０は、どちらかの空
乏層が万一、ノイズなどで溝を乗り越えた時、表面にあ
る高濃度の拡散層で空乏層を吸収するものである。Here, in the N+ channel stopper 10, when one of the depletion layers crosses the groove due to noise or the like, the high concentration diffusion layer on the surface absorbs the depletion layer.
この様にして、チャネルストッパー１０の両端に渭を形
成すると、コレクタにできる空乏層の途中から区切れる
ことができるので、絶縁拡散Ｊｉ１５とベース７の間の
距離を大幅に小さくすることができ、高集積化に適する
構造となる（６０■印加時で約２０〜３０μｍ）。By forming the edges at both ends of the channel stopper 10 in this way, the depletion layer formed at the collector can be separated from the middle, so the distance between the insulating diffusion Ji 15 and the base 7 can be significantly reduced. The structure is suitable for high integration (approximately 20 to 30 μm when applying 60 μm).
第３図は本発明の第２の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the invention.
第２の実施例は、Ｎ＋チャネルストッパー１０の片側に
だけ溝１２を埋めた例であり、その他は第１の実施例と
同じである。第２の実施例は第１の実施例と比べ低い電
圧が印加される様な時、または片側しか高電圧が印加さ
れない様な時に有効である。The second embodiment is an example in which a groove 12 is filled only on one side of the N+ channel stopper 10, and the other aspects are the same as the first embodiment. The second embodiment is effective when a lower voltage is applied than in the first embodiment, or when a high voltage is applied only on one side.
第４図は本発明の第３の実施例の断面図である。FIG. 4 is a sectional view of a third embodiment of the invention.
第３の実施例は、溝１２を設けることは第２の実施例と
同じであるが、Ｎ＋チャネルストッパー１０を省略して
いる。The third embodiment is the same as the second embodiment in providing the groove 12, but the N+ channel stopper 10 is omitted.
この場合も比較的低い電圧が印加された場合、または、
比較的半導体基板表面濃度の高い場合に有効である。Again, if a relatively low voltage is applied, or
This is effective when the semiconductor substrate surface concentration is relatively high.
また、これらのチャネルストッパー及び溝はベース領域
の周囲を完全に囲む必要はなく、チャネルができる心配
のある所にのみ入れても効果がある。又、本発明は高耐
圧バイポーラで示したが他の素子に対しても有効で、拡
散抵抗ｌＭＯＳトランジスタ等の半導体素子のチャンネ
ルル防止にも適用できる。Furthermore, these channel stoppers and grooves do not need to completely surround the base region, and can be effective even if they are placed only in areas where there is a risk of channel formation. Furthermore, although the present invention has been described with respect to a high-voltage bipolar device, it is also effective for other devices, and can also be applied to channel prevention in semiconductor devices such as diffused resistance IMOS transistors.
以上説明したように、本発明は、バイポーラトランジス
タを含む集積回路において、素子領域を区画する絶縁拡
散層とベース領域との間に溝を設け、この溝を絶縁物で
埋めてチャネルが形成されるのを抑制する構造にしたの
で、古有面積を小さくし、集積度を向上させる効果があ
る。As explained above, in an integrated circuit including a bipolar transistor, the present invention provides a groove between an insulating diffusion layer that partitions an element region and a base region, and fills this groove with an insulator to form a channel. Since the structure suppresses this, it has the effect of reducing the old area and improving the degree of accumulation.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ’線断面図、第２図は第１図（ｂ）のＢ部拡
大図、第３図は本発明の第２の実施例の断面図、第４図
は本発明の第３の実施例の断面図、第５図は従来のバイ
ポーラトラジスタの一例の断面図、第６図は第５図のＣ
部拡大図である。
１・・・Ｐ型半導体基板、２・・・Ｎ＋型埋込層、３・
・・Ｐ＋型埋込層、４・・・Ｎ型エピタキシャル層、５
・・・Ｐ＋型絶縁拡散層、６・・・酸化膜、７・・・ベ
ース、８・・・エミッタ、９・・・コレクタコンタクト
、１０・・・Ｎ＋チャネルストッパー、１１・・・電極
配線、１２゜１２ａ、１２ｂ−溝、２１．２２・・・空
乏層、２３・・・反転層。FIGS. 1(a) and (b) are a plan view and a sectional view taken along the line A-A' of the first embodiment of the present invention, FIG. 2 is an enlarged view of section B in FIG. 1(b), and FIG. 4 is a sectional view of a third embodiment of the invention, FIG. 5 is a sectional view of an example of a conventional bipolar transistor, and FIG. 6 is a sectional view of an example of a conventional bipolar transistor. C in the diagram
It is an enlarged view of the part. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N+ type buried layer, 3...
...P+ type buried layer, 4...N type epitaxial layer, 5
... P+ type insulating diffusion layer, 6... Oxide film, 7... Base, 8... Emitter, 9... Collector contact, 10... N+ channel stopper, 11... Electrode wiring, 12° 12a, 12b-grooves, 21.22...depletion layer, 23...inversion layer.
Claims (1)
た逆導電型素子領域が形成され、該素子領域内にバイポ
ーラトランジスタが形成されている半導体装置において
、前記トランジスタのベースと前記絶縁分離層との間に
溝が形成され、該溝が絶縁物で埋められていることを特
徴とする半導体装置。In a semiconductor device in which an element region of opposite conductivity type separated by an insulating separation layer of one conductivity type is formed in a semiconductor substrate of one conductivity type, and a bipolar transistor is formed in the element region, a base of the transistor and the insulating separation layer are formed. 1. A semiconductor device, wherein a groove is formed between the semiconductor device and the groove, and the groove is filled with an insulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63126572A JPH01293661A (en) | 1988-05-23 | 1988-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63126572A JPH01293661A (en) | 1988-05-23 | 1988-05-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01293661A true JPH01293661A (en) | 1989-11-27 |
Family
ID=14938485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63126572A Pending JPH01293661A (en) | 1988-05-23 | 1988-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01293661A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2785090A1 (en) * | 1998-10-23 | 2000-04-28 | St Microelectronics Sa | POWER COMPONENT WITH INTERCONNECTIONS |
| JP2003086826A (en) * | 2001-09-12 | 2003-03-20 | Hamamatsu Photonics Kk | Photodiode array, solid image pickup unit and radiation detector |
| US6831338B1 (en) | 1998-10-19 | 2004-12-14 | Stmicroelectronics S.A. | Power component bearing interconnections |
| CN112768504A (en) * | 2019-11-05 | 2021-05-07 | 珠海格力电器股份有限公司 | Terminal structure of power semiconductor device and power semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559761A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device |
-
1988
- 1988-05-23 JP JP63126572A patent/JPH01293661A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559761A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6831338B1 (en) | 1998-10-19 | 2004-12-14 | Stmicroelectronics S.A. | Power component bearing interconnections |
| FR2785090A1 (en) * | 1998-10-23 | 2000-04-28 | St Microelectronics Sa | POWER COMPONENT WITH INTERCONNECTIONS |
| WO2000025363A1 (en) * | 1998-10-23 | 2000-05-04 | Stmicroelectronics S.A. | Power component bearing interconnections |
| US6583487B1 (en) | 1998-10-23 | 2003-06-24 | Stmicroelectronics S.A. | Power component bearing interconnections |
| JP2003086826A (en) * | 2001-09-12 | 2003-03-20 | Hamamatsu Photonics Kk | Photodiode array, solid image pickup unit and radiation detector |
| JP4482253B2 (en) * | 2001-09-12 | 2010-06-16 | 浜松ホトニクス株式会社 | Photodiode array, solid-state imaging device, and radiation detector |
| CN112768504A (en) * | 2019-11-05 | 2021-05-07 | 珠海格力电器股份有限公司 | Terminal structure of power semiconductor device and power semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0357614B2 (en) | ||
| JPH04146674A (en) | Semiconductor device and manufacture thereof | |
| JPH0336311B2 (en) | ||
| KR940022887A (en) | Insulated Gate Bipolar Transistor | |
| JP3582890B2 (en) | Semiconductor device | |
| US4000507A (en) | Semiconductor device having two annular electrodes | |
| JPH01293661A (en) | Semiconductor device | |
| JPH0556667B2 (en) | ||
| JPS63194367A (en) | semiconductor equipment | |
| JP3217552B2 (en) | Horizontal high voltage semiconductor device | |
| JP3106844B2 (en) | Lateral insulated gate bipolar transistor | |
| JP3033372B2 (en) | Semiconductor device | |
| JP2883779B2 (en) | Semiconductor device | |
| JPS6230704B2 (en) | ||
| JP2518929B2 (en) | Bipolar semiconductor integrated circuit | |
| JPS6310578B2 (en) | ||
| JPH0136711B2 (en) | ||
| JPH0669510A (en) | High-breakdown-strength semiconductor device | |
| JP3233002B2 (en) | Field effect transistor | |
| JPH05110075A (en) | Insulated gate type field effect transistor | |
| JPS5863177A (en) | semiconductor equipment | |
| JPH03231471A (en) | Insulated-gate field-effect transistor | |
| JPH07114280B2 (en) | Semiconductor device | |
| JPH01143253A (en) | Semiconductor device and manufacture thereof | |
| JPS63244684A (en) | Semiconductor device |