JP3033372B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a bipolar transistor.

[0002]

2. Description of the Related Art In an ECL circuit shown in FIG.
Signal propagation time for a signal exiting the output is transmitted to the next stage of the input is determined by the time for charging and discharging the capacitance C _L of the wiring connecting the circuit, and the amount of current charging time flowing through the output transistor Q ₄ of the ECL circuit Involved. If this reason the wiring is long capacitance C _L is large, in order to shorten the charging time, it is necessary to increase the current flowing through the output transistor Q _4, the output transistor Q ₄ are needs to increase the emitter area. However, when the wiring is short and the capacitance C _L is small, the use of a transistor having a large emitter area results in a longer signal propagation time than the case of using a transistor having a small emitter area due to the influence of parasitic capacitance in the transistor.

As a means for solving this problem, a plurality of transistors having a small emitter area are prepared, and one transistor is used when the load is small, and as shown in FIG. Although there is a method of connecting in parallel, a high integration is difficult because a plurality of transistors are required in this method.

Therefore, in the conventional method, a plurality of emitter regions are arranged in one collector region, a common base electrode is used, and when the load is small, one emitter is used.
When the load is large, a plurality of emitters are used to adjust the amount of current, thereby reducing the element area and achieving high integration.

FIG. 5 is a plan view showing an example of a conventional semiconductor device, and FIG. 6 is an enlarged sectional view of FIG.

As shown in FIGS. 5 and 6, a collector is formed by separating an N ⁺ -type buried layer 12 and an N-type epitaxial layer 13 provided on a P-type silicon substrate 11 by an insulating film 14 buried in a trench 1. A plurality of base regions 3 of the collector extraction region 2 are provided in the region, a base extraction electrode 4 connected to each of the base regions 3 is provided in common, the base regions 3 are connected to each other, and a surface including the base extraction electrode 4 is provided. The emitter region 5 provided in the base region 3 and the emitter electrode 16 connected to the emitter region 5 are formed insulated from the base region 3 by the insulating film 15 provided in the base region 3.

[0007]

A conventional semiconductor device is:
As a method of adjusting the delay time due to the wiring, the current flowing through the output transistor is changed. As a method of changing the current, a plurality of output transistors are prepared, and the number of transistors used is changed. However, this method requires a large number of elements and requires a large area, so that high integration is difficult.

This conventional semiconductor device has a plurality of bipolar transistors sharing a collector region and commonly connecting a base extraction electrode. The current capacity of an output transistor is changed by changing the number of emitter electrodes connected. . However, in this method, a plurality of base regions are connected by the base extraction electrode connected to the base region 3 regardless of whether only one emitter is used with a small current or a plurality of emitters are used with a large current. The diffusion capacitance C _jc between the base and the collector is always more than the number of the emitters compared to the transistor having one emitter.

Therefore, even when only one emitter is used in order to use the output transistor with a small current, the capacitance between the base and the collector is more than twice as large as that of the transistor with one emitter, and the switching speed of the transistor is increased. There is a problem that the temperature decreases.

In a transistor in which the elements are separated by trenches as shown in the conventional example, the thickness of the first insulating film 14 is small, and the base polycrystalline silicon film 4 connecting the two base regions and the first polycrystalline silicon film 4 are formed. The base polycrystalline silicon film 4 and the epitaxial layer 13 are formed on the insulating film.
However, there is a problem that the capacitance between the two increases in addition to the capacitance between the base and the collector.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
An insulating isolation region in which a groove is filled with a first insulating film;
Surrounded by the edge separation region, the region of another conductivity type
Transistor formation region of one conductivity type insulated from the region
And one conductive layer provided on the surface of the transistor formation region.
-Type collector extraction region and multiple base regions of opposite conductivity type
And an emitter of one conductivity type formed in the base region.
Connected to the insulation region and the isolation region.
Partitioning a plurality of base areas and a plurality of base areas, and
A first insulating film for partitioning the plurality of base regions from each other
From the surface of the base region other than the emitter region
On the first insulating film which is derived and located above the groove
A base extraction electrode extending to the base extraction electrode, and the base extraction electrode
A second insulating film covering the base and the base extraction electrode
The portion of the second insulating film located above the groove is open
And a base contact hole provided
And the first specific form is as described above.
The base region opposes the collector extraction region.
And as a second specific form,
Source regions are opposed to each other with the long sides close to each other,
The drawer region is close to the short side of the pair of base regions.
It is provided.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a first embodiment of the present invention, and FIG. 2 is an enlarged sectional view of FIG.

As shown in FIGS. 1 and 2, an N-type epitaxial layer 13 is formed on a surface including an N ⁺ -type buried layer 12 selectively provided on the upper surface of a P-type silicon substrate 11. next,
The groove 1 on the upper surface of the epitaxial layer 13 reach the P-type silicon substrate 11 is provided, the insulating film 14 on the upper surface of the groove 1 in filled with and epitaxial layer 13 is selectively formed to N ⁺ -type buried layer 12 and N The collector region composed of the type epitaxial layer 13 is separated.

Next, an N-type impurity is doped into the N-type epitaxial layer 13 through an opening at the center of the insulating film 14 to form a collector extraction region 2 reaching the N ⁺ -type buried layer 12. A base region 3, a base lead electrode 4 connected to the base region 3, an emitter region 5 provided in the base region 3, and a base lead electrode 4 are provided on the left and right element forming regions opposed to each other with the region 2 interposed therebetween. Insulating film 1
5, an emitter electrode 16 connected to the emitter region 5 is formed. Next, the insulating film 15 is selectively etched to form the base contact hole 6 and the collector contact hole 7. In addition, the current capacity of the bipolar transistor can be sequentially increased by extending the collector lead-out region 2 in the major diameter direction as necessary and sequentially arranging the base regions 3 having the emitter regions 5 on both sides thereof in opposition.

FIG. 3 is a plan view showing a second embodiment of the present invention.

As shown in FIG. 3, a base extraction electrode 4 of a bi-polar transistor, in which the long sides of two base regions 3 sharing a collector region are arranged close to each other and symmetrically opposed to each other, is used for device isolation. Extending over the groove 1 of
The structure is the same as that of the first embodiment except that the collector extraction region 2 is arranged close to the short side of the base region 3 opposed to the base region 3, and has an emitter region 5 with the collector extraction region 2 interposed therebetween. A set of base regions 3 can be sequentially added.

[0018]

As described above, according to the present invention, when a plurality of base regions and emitter regions are arranged in a collector region surrounded and separated by a groove, a base extraction electrode connected to each base region is formed. By independently forming and arranging them so as to extend over the element isolation grooves, and connecting the number of base extraction electrodes and the number of emitter electrodes corresponding to the necessary current capacity of the bipolar transistor,
This has the effect of minimizing the capacitance between the collectors.

Therefore, according to the present invention, it is possible to arrange a plurality of emitters in the same collector region without a large increase in capacitance, and there is an effect that high integration and high performance can be easily achieved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view of FIG.

FIG. 3 is a plan view showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an example of an ECL circuit.

FIG. 5 is a plan view illustrating an example of a conventional semiconductor device.

FIG. 6 is an enlarged sectional view of FIG. 5;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Groove 2 Collector extraction region 3 Base region 4 Base extraction electrode 5 Emitter region 6 Base contact hole 7 Collector contact hole 11 P-type silicon substrate 12 N ⁺ type buried layer 13 N-type epitaxial layer 14, 15 Insulating film 16 Emitter electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 21/8222 H01L 27/082 H01L 29/73

Claims (3)

(57) [Claims] 1. An insulating separation in which a trench is filled with a first insulating film.
Region, and other regions surrounded by the insulating isolation region.
One-conductivity-type transformer isolated from one-conductivity-type region
A transistor forming region and a transistor forming region.
The collector extraction region of one conductivity type and the
A number of base regions and one formed in said base region.
Connected to a conductive type emitter region and the insulating isolation region
Together with the collector extraction region and the plurality of base regions.
Partitioning and partitioning the plurality of base regions from each other
A first insulating film and the base region other than the emitter region;
The first channel, which is derived from the surface of the area and is located above the groove
A base extraction electrode extending over the insulating film of
A second insulating film covering the source extraction electrode;
Extremely high and located above the groove of the second insulating film.
Base contact hole provided with an opening
And a semiconductor device comprising: Wherein said base region is a semiconductor device according to claim 1, wherein it is positioned so as to face each other across the collector lead-out region. Wherein the base region are opposed to each other to close the long side, the collector lead-out region is the pair of base territory
2. The semiconductor device according to claim 1, wherein the semiconductor device is provided close to a short side of the region .