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JPH01293642A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01293642A
JPH01293642A JP12613788A JP12613788A JPH01293642A JP H01293642 A JPH01293642 A JP H01293642A JP 12613788 A JP12613788 A JP 12613788A JP 12613788 A JP12613788 A JP 12613788A JP H01293642 A JPH01293642 A JP H01293642A
Authority
JP
Japan
Prior art keywords
die pad
stress
semiconductor chip
thermal expansion
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12613788A
Other languages
Japanese (ja)
Inventor
Masanori Obata
正則 小畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12613788A priority Critical patent/JPH01293642A/en
Publication of JPH01293642A publication Critical patent/JPH01293642A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate a stress between a molding resin and a semiconductor chip and to relax a stress to be exerted on a die pad by a method wherein a thermal expansion coefficient of the molding resin is made nearly equal to a thermal expansion coefficient of the semiconductor chip and a hole used to relax the stress is made in the die pad. CONSTITUTION:Roles 6 used to relax a stress are made at regular intervals in a die pad 5. A semiconductor chip 2, the die pad 5, wires 3 and one part of connection pins 4 are resin-sealed with a molding resin 1. A thermal expansion coefficient of the resin 1 is selected so as to be nearly equal to a thermal expansion coefficient of the chip 2. Then, when this assembly is cooled after the resin sealing operation, a stress to be exerted on the pad 5 from the resin 1 is scattered because the holes 6 exist. Also a stress from the chip 2 is scattered and relaxed through the holes 6. By this setup, the stress to be exerted on the pad 5 is relaxed.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は半導体装置に関するものであり、特にモール
ド樹脂で半導体チップおよびダイパッドを覆い樹脂封止
した半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip and a die pad are covered with a molding resin and sealed with a resin.

［従来の技術］ 第２図は、従来の半導体装置を示す断面図である。第２
図において、半導体チップ２はダイパッド５上に接着さ
れており、半導体チップ２はワイヤ３により接続ピン４
と接続されている。半導体チップ２、ダイパッド５、ワ
イヤ３および接続ピン４の一部は、モールド樹脂１によ
り覆われ樹脂封止されている。[Prior Art] FIG. 2 is a sectional view showing a conventional semiconductor device. Second
In the figure, the semiconductor chip 2 is bonded on the die pad 5, and the semiconductor chip 2 is connected to the connecting pin 4 by the wire 3.
is connected to. Parts of the semiconductor chip 2, die pad 5, wires 3, and connection pins 4 are covered with a mold resin 1 and sealed with the resin.

従来の半導体装置において、モールド樹脂１としては、
半導体チップ２の熱膨張率とダイパッド５の熱膨張率の
中間にあたる熱膨張率の樹脂が用いられている。In a conventional semiconductor device, the mold resin 1 is as follows:
A resin having a coefficient of thermal expansion that is between the coefficient of thermal expansion of the semiconductor chip 2 and the coefficient of thermal expansion of the die pad 5 is used.

［発明が解決しようとする課題］ このようにモールド樹脂１の熱膨張率として、半導体チ
ップ２とダイパッド５の中間の熱膨張率のものを用いる
と、半導体チップ２の熱膨張率とモールド樹脂１の熱膨
張率が異なるため、モールド樹脂により樹脂封止した後
常温に冷却された際、半導体チップ２がモールド樹脂１
から応力を受けるという問題があった。このような問題
を解決する方法として、半導体チップ２の熱膨張率と同
じ熱膨張率を有する樹脂をモールド樹脂１として用いる
ことが考えられるが、このようなモールド樹脂を用いる
と、ダイパッド５との熱膨張率の差が大きくなりすぎ、
ダイパッド５への応力が問題となる。[Problems to be Solved by the Invention] As described above, when the thermal expansion coefficient of the molding resin 1 is intermediate between that of the semiconductor chip 2 and the die pad 5, the thermal expansion coefficient of the semiconductor chip 2 and the molding resin 1 are Since the thermal expansion coefficients of the semiconductor chips 2 and 1 are different, when the semiconductor chip 2 is cooled to room temperature after being sealed with a mold resin, the semiconductor chip 2 is different from that of the mold resin 1.
There was a problem in that it was subjected to stress. One possible way to solve this problem is to use a resin having the same coefficient of thermal expansion as that of the semiconductor chip 2 as the mold resin 1. However, if such a mold resin is used, the relationship between the die pad 5 and the The difference in thermal expansion coefficient becomes too large,
Stress on the die pad 5 becomes a problem.

この発明は、このような従来の問題を解消するためにな
されたもので、モールド樹脂と半導体チップとの間での
応力をほぼなくすとともに、ダイパッドへのモールド樹
脂からの応力も緩和され得る半導体装置を提供すること
を目的としている。This invention was made to solve these conventional problems, and provides a semiconductor device in which stress between the mold resin and the semiconductor chip can be almost eliminated, and stress from the mold resin on the die pad can also be alleviated. is intended to provide.

［課題を解決するための手段］ この発明の半導体装置では、ダイパッド上に半導体チッ
プを設け、モールド樹脂で半導体チップおよびダイパッ
ドを覆い樹脂封止しており、モールド樹脂の熱膨張率は
半導体チップの熱膨張率とほぼ同じであり、かつダイパ
ッドには応力を緩和するための穴が形成されていること
を特徴としている。[Means for Solving the Problems] In the semiconductor device of the present invention, a semiconductor chip is provided on a die pad, and the semiconductor chip and die pad are covered and sealed with a mold resin, and the thermal expansion coefficient of the mold resin is equal to that of the semiconductor chip. The coefficient of thermal expansion is almost the same as that of the die pad, and the die pad is characterized by having holes formed to relieve stress.

［作用］ この発明の半導体装置では、モールド樹脂の熱膨張率が
半導体チップの熱膨張率とほぼ同じである。したがって
、モールド樹脂により樹脂封止した後常温に冷却しても
、半導体チップとモールド樹脂との間にはほとんど応力
が生じない。[Function] In the semiconductor device of the present invention, the coefficient of thermal expansion of the molding resin is approximately the same as that of the semiconductor chip. Therefore, even if the semiconductor chip is sealed with a mold resin and then cooled to room temperature, almost no stress is generated between the semiconductor chip and the mold resin.

また、この発明の半導体装置では、ダイパッドに応力を
緩和するための穴が形成されている。この穴は、好まし
くはダイパッドに分散した状態で周期的に形成される。Further, in the semiconductor device of the present invention, holes are formed in the die pad to relieve stress. The holes are preferably formed periodically and distributed over the die pad.

モールド樹脂の熱膨張率として、半導体チップの熱膨張
率とほぼ同じものを用いることにより、モールド樹脂の
熱膨張率と、ダイパッドの熱膨張率との差は従来の半導
体装置よりも大きくなるが、ダイパッドには応力を緩和
するための穴が形成されているため、ダイパッドへのモ
ールド樹脂の応力がこの穴により緩和される。また、ダ
イパッドへの半導体チップからの応力も同じくこの穴に
より緩和される。By using a coefficient of thermal expansion of the mold resin that is almost the same as that of the semiconductor chip, the difference between the coefficient of thermal expansion of the mold resin and the coefficient of thermal expansion of the die pad is larger than that of conventional semiconductor devices. Since holes are formed in the die pad to relieve stress, the stress of the molding resin on the die pad is relieved by the holes. Further, the stress applied to the die pad from the semiconductor chip is also alleviated by this hole.

［実施例］ 第１図は、この発明の一実施例である半導体装置を示す
断面図である。第１図において、ダイパッド５には、応
力を緩和するため周期的に穴６が形成されている。この
ダイパッド５の上に半導体チップ２が接着されている。[Embodiment] FIG. 1 is a sectional view showing a semiconductor device which is an embodiment of the present invention. In FIG. 1, holes 6 are periodically formed in the die pad 5 to relieve stress. A semiconductor chip 2 is bonded onto this die pad 5.

半導体チップ２はワイヤ３により接続ピン４に接続され
ている。半導体チップ２、ダイパッド５、ワイヤ３およ
び接続ピン４の一部は、モールド樹脂１により樹脂封止
されている。モールド樹脂１の熱膨張率は、半導体チッ
プ２の熱膨張率とほぼ同一のものとなるよう選択されて
いる。The semiconductor chip 2 is connected to connecting pins 4 by wires 3. A portion of the semiconductor chip 2, die pad 5, wires 3, and connection pins 4 are resin-sealed with a mold resin 1. The coefficient of thermal expansion of the molding resin 1 is selected to be approximately the same as that of the semiconductor chip 2.

ダイパッド５には周期的な穴６が形成されているため、
樹脂封止した後常温に冷却した際、ダイパッド５に加わ
るモールド樹脂１からの応力を穴６の存在により分散さ
せることができる。また、半導体チップ２からの応力も
、この穴６により分散させ緩和させることができる。Since periodic holes 6 are formed in the die pad 5,
When the die pad 5 is cooled to room temperature after resin sealing, the stress from the mold resin 1 applied to the die pad 5 can be dispersed by the presence of the holes 6. Further, the stress from the semiconductor chip 2 can also be dispersed and relaxed by the holes 6.

なお、この発明においてダイパッドに形成する穴の大き
さや密度は、使用するモールド樹脂、ダイパッドおよび
半導体チップなどの熱膨張率の差等を考慮して適宜調整
することができる。In the present invention, the size and density of the holes formed in the die pad can be adjusted as appropriate, taking into account differences in thermal expansion coefficients of the molding resin used, the die pad, the semiconductor chip, and the like.

［発明の効果］ 以上説明したように、この発明によれば、モールド樹脂
および半導体チップの熱膨張率をほぼ同一にしているの
で、モールド樹脂と半導体チップとの間で発生する応力
をほぼなくすことができる。[Effects of the Invention] As explained above, according to the present invention, since the coefficient of thermal expansion of the mold resin and the semiconductor chip are made almost the same, stress generated between the mold resin and the semiconductor chip can be almost eliminated. I can do it.

また、ダイパッドには応力を緩和するための穴が形成さ
れているので、モールド樹脂とダイパッドとの熱膨張率
の差が従来よりも大きくなっても、モールド樹脂からの
ダイパッドへの応力は緩和され得る。さらに、半導体チ
ップからのダイパッドへの応力もこの穴により緩和され
得る。In addition, the die pad has holes formed to relieve stress, so even if the difference in thermal expansion coefficient between the mold resin and the die pad becomes larger than before, the stress from the mold resin to the die pad will be alleviated. obtain. Furthermore, the stress on the die pad from the semiconductor chip can also be alleviated by the hole.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、この発明の一実施例である半導体装置を示す
断面図である。第２図は、従来の半導体装置の一例を示
す断面図である。 図において、１はモールド樹脂、２は半導体チップ、３
はワイヤ、４は接続ピン、５はダイパッド、６はダイパ
ッドに形成される穴を示す。 なお、図中、同一符号は同一または相当部分を示す。FIG. 1 is a sectional view showing a semiconductor device which is an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of a conventional semiconductor device. In the figure, 1 is a mold resin, 2 is a semiconductor chip, and 3 is a mold resin.
4 is a wire, 4 is a connection pin, 5 is a die pad, and 6 is a hole formed in the die pad. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] （１）ダイパッド上に半導体チップを設け、モールド樹
脂で前記半導体チップおよびダイパッドを覆い樹脂封止
した半導体装置において、前記モールド樹脂の熱膨張率
は、前記半導体チップの熱膨張率とほぼ同じであり、か
つ前記ダイパッドには応力を緩和するための穴が形成さ
れていることを特徴とする半導体装置。(1) In a semiconductor device in which a semiconductor chip is provided on a die pad, the semiconductor chip and the die pad are covered and sealed with a mold resin, the coefficient of thermal expansion of the mold resin is approximately the same as the coefficient of thermal expansion of the semiconductor chip. and a hole for relaxing stress is formed in the die pad.
JP12613788A 1988-05-23 1988-05-23 Semiconductor device Pending JPH01293642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12613788A JPH01293642A (en) 1988-05-23 1988-05-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12613788A JPH01293642A (en) 1988-05-23 1988-05-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01293642A true JPH01293642A (en) 1989-11-27

Family

ID=14927589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12613788A Pending JPH01293642A (en) 1988-05-23 1988-05-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01293642A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684328A (en) * 1992-07-29 1997-11-04 Samsung Electronics Co., Ltd. Semiconductor chip package using improved tape mounting
KR100302559B1 (en) * 1998-12-31 2001-11-30 마이클 디. 오브라이언 Semiconductor Package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684328A (en) * 1992-07-29 1997-11-04 Samsung Electronics Co., Ltd. Semiconductor chip package using improved tape mounting
KR100302559B1 (en) * 1998-12-31 2001-11-30 마이클 디. 오브라이언 Semiconductor Package

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