JPH01280911A - Operational amplifier circuit - Google Patents

Abstract

PURPOSE:To improve the drive capability with respect to a capacitive load by providing two sets of folded cascode stages connecting to a differential input stage, driving one drive transistor(TR) of an inverse amplifier being the final stage by one out put and driving the other TR of the inverse amplifier through current mirror by the other output. CONSTITUTION:Since the maximum voltage of a contact 6 rises up to the voltage of a 1st power supply 1, an MP8 is turned off in this case and the output voltage is lowered up to a voltage equal to the voltage of a 2nd power supply 2. On the other hand, since the voltage of a contact 5 rises up to the voltage of the 1st power supply 1, an MP7 is turned off in this case and since no current flows to an MN5, no current flows to the MN 6. That is, in this case, the output voltage rises up to a voltage equal to the voltage of the 1st voltage source 1. Moreover, the output stage is of push-pull configuration where N- channel MOS TRs MN1-12 and P-channel MOS TRs MP1-11 are controlled both by an input signal. Thus, the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an operational amplifier circuit configured on an integrated circuit, and particularly to an operational amplifier circuit configured on an integrated circuit. This invention relates to a large operational amplifier that is symmetrical in both negative directions.

[Conventional technology]

Conventionally, operational amplifiers with a large gain and a wide output voltage range have mainly used a two-stage amplifier configuration. This conventional technique will be explained using FIG. 2. Figure 2 is from 1984
IEEE Journal of Solid State Circuits.
5th C of 5olid-5tate C1rcurts)
This is a circuit published in Volume 19, page 1, 920 pages.

In FIG. 3, a p-channel MO8) transistor MP for a constant current source is formed by applying a constant voltage 111 to the gate electrode.
MPIOI and MP 102, which are a differential transistor pair whose source electrodes are commonly connected to the constant current source, are connected to 109 (hereinafter referred to as MP 109). The drain electrodes of the differential transistor pair have gate electrodes commonly connected to a reference voltage input terminal 106, and drain electrodes connected to a current mirror constituted by MP 105 and MP 106 with the first power supply line 101 as a reference. N-channel MOS transistors MN103 and M used in the folded cascode stage made of
The source electrode of N104 (hereinafter referred to as MN103 and MN104) is connected to a constant current source with the second voltage source 102 as a reference.

The output 106 of the folded cascode stage is MP
The signal is further amplified by an inverting amplifier in which 108 is a drive transistor and MN 106, whose gate terminal 109 is supplied with a constant voltage, is a constant current load, and is output from an output terminal 107. C6 in FIG. 2 is a phase compensation capacitor. This circuit has the advantage that the input voltage range can be widened and the output voltage range can output up to a voltage approximately equal to the negative power supply 102 for the lowest voltage. Note that terminal 10
A constant voltage is also applied to 5.

[Problem to be solved by the invention]

However, when a large capacitive load is connected to the circuit and a signal with a large amplitude is output, the speed at which the voltage decreases is limited by the current flowing through the MN 106, especially when the voltage decreases.

Therefore, in order to speed up this process, it is necessary to increase the current flowing through the MN 106. This means that the current consumed by the circuit increases. If the current is further increased, the upper limit of the output voltage is determined by this current and the on-resistance of MP 10 g, so it becomes impossible to increase the output voltage to below the power supply voltage. These drawbacks are unacceptable for operational amplifiers implemented on integrated circuits.

[Means to solve the problem]

In order to solve the above problems, the present invention provides an operational amplifier circuit in which a common source is connected to a first constant current source whose one end is connected to a first voltage source, and each gate electrode is connected to an input terminal. a differential transistor pair having a first polarity, the drain electrode being connected to a first current mirror configured by the first transistor pair having a first polarity and having the first voltage source as a reference; , a first pair of transistors having a second polarity, whose gate electrodes are commonly connected to a first reference voltage source and whose source electrodes are respectively connected to the drain electrodes of each of the differential transistor pairs; a current source pair consisting of a folded cascode stage with a drain electrode connected to the source electrode of said second transistor pair, a source electrode connected to a second voltage source, and a transistor pair having a second polarity; and a third transistor pair whose drain electrode has a first polarity and is connected to a second current mirror having a symmetrical relationship with respect to the first current mirror with respect to the first voltage source. a fourth pair of transistors having a second polarity, whose gate electrodes are commonly connected to the first reference voltage source and whose source electrodes are respectively connected to the drain electrodes of each of the differential transistor pairs; a second folded cascode stage and a third current mirror constituted by a transistor pair having a second polarity, the drain electrode of which is the reference electrode as the second voltage source, and the gate electrode of which is connected to the second folded cascode stage; and a pair of transistors having a first polarity connected to a dead cascode stage.

[Effect]

By using the circuit of the present invention, there are two sets of folded cascode stages connected to the differential input stage, and one drive transistor is driven by the - terminal of the inverting amplifier which is the final stage of output Z, and the other drive transistor is By configuring a push-pull type output stage by driving another transistor of the inverting amplifier with an output current mirror, the drive capability for capacitive loads is dramatically improved, and the output voltage range is reduced to - It can be expanded to a cup.

〔Example〕

Hereinafter, the present invention will be explained in more detail with reference to an example realized on an MO3 type integrated circuit. FIG. 1 is a circuit diagram showing the configuration of this embodiment. The embodiment of FIG. 1 includes P-channel MO8) transistors MPIO, MPII and N-
1F-+”/Nel Mos transistor MN9.MNI
O, MNI 1. A simple reference bias voltage generation circuit configured by MNI2 is also included in the description.

First, P-channel MOS transistors MPI and MP2 whose sources are commonly connected to a constant current source constituted by a P-channel transistor MP9 whose source electrode is connected to the first voltage source 1 and whose gate electrode is constant biased constitute a differential transistor pair. P-channel MO8) The gate electrodes of transistors MPI and MP2 form input terminals 3 and 4, respectively. N-channel MO 8) transistor pairs MNI and M whose gate electrodes are biased to another constant voltage 6 and whose source electrodes are connected to the drain electrodes of said differential pairs MPI and MP2, respectively;
The input signal is passed through the first folded cascode stage consisting of a current mirror formed by N2 and transistors MP3 and MP4, in which the drain electrodes of MHI and MN2 are connected to the current input and output terminals, respectively. The signal is amplified and an amplified output is obtained at the output contact 5. This circuit has another folded cascode stage. It consists of a first folded cascode stage and a pair of N-channel MO8) transistors MN3 and M, whose gate and source electrodes are respectively connected in common.
The drain electrodes of N4, MN3, and MN4 are connected to the current input/output terminals, respectively, and the direction of the reversed current is opposite to that of the first current mirror. A second folded cascode stage constituted by a current mirror, this second folded cascode stage is symmetrical to the first folded cascode stage, and the output 6 of this stage is the output of 5. An output with the opposite phase is obtained. These two folded cascode stages are
It operates by being current biased by N-channel MO8) transistors MN7 and MN8, which constitute a pair of constant current sources whose gate electrodes are biased to a common constant voltage. The output 5 of the first folded casshood stage is converted into a current by a P-channel MO8) transistor MP7,
5 and MN6 to output terminal 7 through a third current mirror constituted by MN6. The output 6 of the second folded casshood stage is connected to the output 8 through a P-channel transistor MP8. Here, MN
6 and MP8 constitute a push-pull output circuit. CCI and CC2 are phase compensation capacitors.

In the embodiment described above, the first compensation capacitor CCI is connected between the output terminal 7 and the drain terminal of the transistor MP2 to which the normal input terminal 4 is connected, and the first compensation capacitor CCI is connected between the output terminal and the gate of the output drive N-channel transistor MN8. C6 between the electrodes
The reason why two 6-phase compensation capacitors are required is that there are two paths for driving the output, one for driving MP8 and the other for driving MN6. CCI is MP
8, and CO2 is M
This is phase compensation for the path that drives N6. A phase compensation capacitor may be added between contact 5 and ground for the path for driving MN6. FIG. 2 shows an embodiment in which a second phase compensation capacitor C82 is added between the contact 5 and the second power source. The ground side terminal of the second phase compensation capacitor C82 may be the first power supply or another reference voltage.

To explain the operation of this circuit again, a signal inputted from the input terminal 3.4 is amplified and outputted to the output contacts 5 and 6 of the folded cascode stage. One side of this output is M
Drive P8. The other output is MP7. It is inverted by MN5 and drives MN6. Then, it is further amplified by MP8 and MN8 and output to the output cuff.

In addition, in the present invention, the N-channel MO8) transistor and the P-channel MO transistor in each embodiment of FIG. 1 and FIG.
It is also possible to use a circuit in which the S transistors are replaced.

〔Effect of the invention〕

In this circuit, the maximum value of the voltage at contact 6 increases to the voltage of the first power supply, so in this case, MP8 is turned off and the output voltage can drop to a voltage equal to the voltage of the second power supply. On the other hand, since the voltage at contact 5 also rises to the voltage of the first power supply, in this case MP7 is turned off, and since no current flows through MN5, it is possible to create a case in which no current flows to MN6 as well. That is, in this case the output voltage rises to a voltage equal to the voltage of the first voltage source.

Also, in the output stage, unlike conventional circuits, both the N-channel MO3) transistor and the P-channel MO8) transistor are controlled by the input signal, or the speed of the falling signal is limited by the bias current of the circuit. The problem of a significant increase in current consumption when trying to improve the speed of rise or fall does not occur, and it becomes possible to design the current flowing through the output stage to be small. Therefore, by using the circuit according to the present invention, it is possible to create an operational amplifier with low power consumption, high driving capability, and wide output voltage range.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing another embodiment of the invention, and Fig. 3 is a circuit diagram showing a conventionally generally known CMO8 operational amplifier circuit. It is a diagram. MN1~12...N channel MO3) transistor, MP 1~11...P channel MO3
) transistor, 1,101...first voltage source,
2゜102...Second voltage source, 3.4.103
．． 104...Input terminal, 5,6...Output node, 7,107...Output terminal, 106...
...Cascode stage output, 109...Gate input terminal. Agent Patent Attorney Uchihara Otogiku 3 MN/1) 3-n4・〃v～πke・/2-～Channel 6 St-Lanolin (RiΔ〃lρ/・nnn・dan-n V, Tan,
Rhinoceros, m3/ρ4: Input Sadanako Z, force λ coat 7 Nagato /ρ7-output Kikai child Zukta: ri'''-?, U) Za
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Claims (1)

[Claims] A pair of differential transistors having a first polarity, each having a common source connected to a first constant current source whose one end is connected to a first voltage source, and each gate electrode serving as an input terminal. , a drain electrode connected to a first current mirror formed by a first transistor pair having a first polarity and referenced to the first voltage source, and a gate electrode commonly connected to a first reference voltage line. a first folded cascode stage constituted by a second pair of transistors having a second polarity, each having a source electrode connected to a drain electrode of each of said differential transistor pair; a current source pair consisting of a pair of transistors connected to the source electrodes of the pair of transistors, the source electrodes of which are connected to a second voltage source and have a second polarity; and a third pair of transistors whose drain electrodes have a first polarity. a second current mirror having a symmetrical relationship with respect to the first current mirror, and having a gate electrode connected to the first reference voltage source; a second folded cascode stage constituted by a fourth pair of transistors of a second polarity connected in common and whose source electrodes are respectively connected to the drain electrodes of each of said differential transistor pairs; connected to a third current mirror constituted by a pair of transistors having a second polarity with electrodes as the second voltage source, and gate electrodes each having a first polarity connected to the folded cascode stage; An operational amplifier circuit comprising: a pair of transistors, wherein a connection point between the pair of transistors having the first polarity and the third current mirror is an output terminal.