JP3119221B2 - Operational amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier,
In particular, it relates to an operational amplifier having a current mirror circuit before an output stage.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing an example of a conventional operational amplifier. This conventional operational amplifier is a CMOS operational amplifier having a push-pull output, and has a power supply terminal VDD and a power supply terminal VGN to which a power supply voltage lower than the power supply terminal VDD is applied.
During D, the configuration includes a bias circuit 1, an input stage 2, a phase inversion output stage 3, and an output stage 4.

The bias circuit 1 includes an N-channel transistor MN1 controlled by applying a bias voltage from a bias voltage input terminal VB to a gate, and a P-channel transistor MP1 having a drain and a gate connected to the drain of the MN1. . The input stage 2 is connected to the P
A current mirror circuit composed of channel transistors MP1 and MP2, and a P-channel transistor M forming a current switch with respect to P-channel transistor MP2.
P3 and MP4, and N-channel transistors MN2 and MN3 forming a current mirror circuit. The input terminals VII and VIN are connected to the gates of the P-channel transistors MP3 and MP4.

The phase inversion output stage 3 comprises a transistor MP5 of a constant current source whose source and back gate are connected to the power supply terminal VDD, and N-channel transistors MN4 and MN5 controlled by the voltage of the node N1 of the input stage 2. . Further, the output stage 4 includes a current mirror circuit including the N-channel transistors MN5 and MN6 of the phase inversion output stage 3, a current mirror circuit including the P-channel transistors MP6 and MP7 connected to the drain side of the transistor MN6, The circuit comprises a resistor R1 and a capacitor C1, which constitute a circuit, and an N-channel transistor MN7 which is controlled by applying a voltage of a node N1 to a gate. P-channel transistors MP7 and N
Both drains of the channel transistor MN7 are connected to the output terminal O
Commonly connected to UT.

In this conventional operational amplifier, a constant bias voltage is applied to a transistor M from a bias voltage input terminal VB.
By being applied to the gate of N1, a constant current flows through each of the transistors MP1 and MP2 and the transistor MP5, which constitute a current mirror circuit connected to the drain side of the transistor MN1, to operate as a constant current source. On the other hand, input signals are input to respective gates of the transistors MP3 and MP4, and the input signals are differentially amplified and taken out from the node N1, phase-inverted by the phase inversion output stage 3, and output through the output stage 4. Is done.

FIG. 3 is a circuit diagram showing another example of the conventional operational amplifier. 2, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. The conventional operational amplifier shown in FIG. 3 is a single-drive operational amplifier and includes a transistor M
The output voltage taken out from the connection point between the drain of P4 and the drain of transistor MN3 is phase-compensated and output.

Here, the conventional operational amplifier shown in FIG. 2 has a bias current of 2 with respect to the load transistor MP7.
The output can be driven up to twice. Further, the output conductance can be doubled as compared with the single-drive operational amplifier as shown in FIG. 3, which is effective for reducing the transistor channel width and the bias current.

Further, the conventional operational amplifier shown in FIG.
The output current of the phase inversion output stage 3 is converted into a drive voltage of a load transistor by a two-stage current mirror. Here, the channel lengths of the transistors from the phase inversion output stage 3 to the output terminal OUT are made uniform, and the relationship between the channel amplification of the phase inversion input transistor and the current amplification ratio determined by the ratio of the channel width of the output transistor is determined by the load-side current path MN5. , MN6,
It must be designed so that MP6 and MP7 hold.

[0009]

However, in the above-mentioned conventional operational amplifier, the common-mode input range of the input stage 2 is changed to GN without changing the range of the output voltage according to the user's request.
When the voltage is lowered to the D side, the output voltage at the node N1 of the input stage 2 decreases, so that the potential becomes substantially equal to the threshold voltage of the transistor MN4. For this reason, most of the bias current supplied from the transistor MP5 flows to the transistor MN5, and the balance between the phase inversion input transistor MN4 and the phase inversion output transistor MN5 cannot be maintained.

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide an operational amplifier capable of maintaining a balance between a phase inversion input transistor and a phase inversion output transistor.

[0011]

According to the present invention, there is provided an input stage for differentially amplifying an input signal, a bias circuit for supplying a bias signal to the input stage, and an output signal of the input stage. And an output stage for phase-compensating and outputting the output signal of the phase-inversion output stage, wherein the phase-inversion output stage includes a transistor for a constant current source, an input A phase inversion input transistor to which the output signal of the stage is input, and a phase inversion output transistor in which a current flowing through the phase inversion input transistor and the constant current source transistor is determined, wherein the constant current source transistor is of a first conductivity type. And the phase inverting input transistor and the phase inverting output transistor are each a second conductivity type non-doped M transistor.
It is composed of OS transistors.

According to the present invention, since the phase inversion input transistor and the phase inversion output transistor of the phase inversion output stage to which the signal amplified by the input stage is inputted are each constituted by a non-doped MOS transistor, the phase inversion input transistor and the phase inversion The output transistor can be operated at a threshold voltage sufficiently lower than the signal voltage output from the input stage.

Here, the present invention provides a first conductive type first MOS transistor and a first conductive type second MOS transistor which forms a current mirror circuit with the first MOS transistor.
An S transistor, a first non-doped MOS transistor of a second conductivity type having a drain connected to the drain of the first MOS transistor and a gate connected to the bias voltage input terminal, and a gate connected to the first input terminal And a third MOS transistor of the first conductivity type, the source of which is connected to the drain of the second MOS transistor, the gate of which is connected to the second input terminal, and the second MOS transistor A fourth MOS transistor of the first conductivity type having a source connected to the drain of the first MOS transistor and a first MOS transistor having a gate connected to the gate of the first MOS transistor
5th MOS transistor of the first conductivity type and sixth and 7th conductivity type of the first
, A second non-doped MOS transistor of the second conductivity type having a drain connected to the drain of the third MOS transistor, a drain connected to the drain of the fourth MOS transistor, and A gate is connected to a common connection point between both drains of a third non-doped MOS transistor of a second conductivity type forming a current mirror circuit with the non-doped MOS transistor, a fourth MOS transistor and a second non-doped MOS transistor, and A fourth non-doped MOS transistor of the second conductivity type for phase inversion input having a drain connected to the drain of the fifth MOS transistor, and a phase inversion having a gate and drain connected to the drain of the fourth non-doped MOS transistor The fifth of the second conductivity type for output
And a second conductive type in which the gate is connected to the gate of the fifth non-doped MOS transistor and the gate and drain of the sixth MOS transistor and the drain are connected to the gate of the seventh MOS transistor. Sixth non-doped MOS transistor, a fourth MOS transistor and a second non-doped M transistor.
A seventh non-doped MOS transistor of a second conductivity type having a gate connected to a common connection point between both drains of the OS transistor, and a drain connected to the drain and the output terminal of the seventh MOS transistor; In this configuration, a capacitor and a resistor are connected in series between a common connection point of both drains of the transistor and the second non-doped MOS transistor and both drains of the sixth and seventh non-doped MOS transistors.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an operational amplifier according to an embodiment of the present invention. 2, the same components as those in FIG. 2 are denoted by the same reference numerals.

In FIG. 1, the operational amplifier includes a first power supply terminal VDD, a second power supply terminal VGND to which a power supply voltage lower than the first power supply terminal VDD is applied, a bias power supply terminal VB, and a first power supply terminal VB. , The second input terminals VII, VIN
And first to seventh P-channel MOS transistors MP1 to MP7, and first to seventh N-channel non-doped MOS transistors MND1.
To MND7.

In the first P-channel MOS transistor MP1, the source and the back gate are connected to the first power supply terminal VDD, and the gate and the drain are the first N.
It is connected to the drain of the channel non-doped MOS transistor MND1. First N-channel non-doped M
The OS transistor MND1 has a gate connected to the bias power supply terminal VB, and a source and a back gate connected to the second power supply terminal VGND. In addition, the first P
The gate of the channel MOS transistor MP1 is connected to the gate of the second P-channel MOS transistor MP2 and the fifth
Of the P-channel MOS transistor MP5.

The transistor MP2 has a source and a back gate connected to the first power supply terminal VDD, and a drain connected to the third power supply terminal VDD.
And the fourth P-channel MOS transistor MP3 connected to the source and back gate of the
It is connected to the source and the back gate of the transistor MP4. Thereby, the transistors MP1 and MP2
Constitutes a current mirror circuit. The drain of the third P-channel MOS transistor MP3 is connected to the second N-channel non-doped MOS transistor M3.
Connected to the gate and drain of ND2.

The second N-channel non-doped MOS transistor MND2 has a source and a back gate connected to the second power supply terminal VGND, a gate connected to the drain, and a third N-channel non-doped MOS transistor MND3 connected to the gate. It is connected. The drain of the third N-channel non-doped MOS transistor MND3 is connected to the drain of the fourth P-channel MOS transistor MP4, the gates of the fourth N-channel non-doped MOS transistor MND4 and the seventh N-channel non-doped MOS transistor MND7, and the capacitor C1. Is connected to Fourth P-channel MOS transistor MP4
Has a source and a back gate connected to the drain of the second P-channel MOS transistor MP2, and a gate connected to the second
Is connected to the input terminal VIN. The transistors MP2, MP3, MP4, MND2 and MND3 constitute an input stage, and the transistors MND1 and MP1
Constitutes an input stage bias circuit.

Fifth P-channel MOS transistor MP
The source and back gate of each of the fifth and sixth P-channel MOS transistors MP6 and MP7 are connected to the first power supply terminal VDD.
It is connected to the. The fifth P-channel MOS transistor MP5 forms a constant current source. The gates of the sixth P-channel MOS transistor MP6 and the seventh P-channel MOS transistor MP7 are connected to each other to form a current mirror circuit.

Fourth N-channel non-doped MOS transistor MND4, fifth N-channel non-doped MOS transistor MND5, sixth N-channel non-doped MO transistor
The source and back gate of the S transistor MND6 and the seventh N-channel non-doped MOS transistor MND7 are both connected to the second power supply terminal VGND. The drain of the fourth N-channel non-doped MOS transistor MND4 is connected to the fifth P-channel M
The drain of the OS transistor MP5, the drain and gate of the fifth N-channel non-doped MOS transistor MND5, and the gate of the sixth N-channel non-doped MOS transistor MND6 are connected to each other. N
Channel non-doped MOS transistors MND5 and MND
The gates of ND6 are commonly connected.

Further, a sixth N-channel non-doped MOS
The drain of the transistor MND6 is connected to the drain and the gate of the sixth P-channel MOS transistor MP6. The seventh N-channel non-doped MOS transistor MND7 has a drain commonly connected to the output terminal OUT together with a drain of the seventh P-channel MOS transistor MP7, and a gate connected to the capacitor C1 and the resistor R1.
P-channel MOS transistor M
Connected to the drain of P7 and the transistor MP4
And MND3 are also connected to a common drain connection point (node N1). The capacitor C1 and the resistor R1 constitute a phase compensation circuit.

The N-channel non-doped MOS transistors MND4 and MND5 and the P-channel MOS transistor MP5 constitute a phase inversion circuit (phase inversion output stage). The P-channel MOS transistor MP5 is a bias current source of the phase inversion circuit.

In the operational amplifier of this embodiment, a constant bias voltage is applied to the gate of the transistor MN1 from the bias voltage input terminal VB, so that the transistor constituting the current mirror circuit connected to the drain of the transistor MN1 is formed. The point that a constant current flows through each of the transistors MP1 and MP2 and the transistor MP5 to operate as a constant current source is the same as the conventional operational amplifier of FIG.

On the other hand, an input signal is inputted from the input terminals VII and VIN to the respective gates of the transistors MP3 and MP4.
, And is differentially amplified by MP4 and input from the node N1 to the gate of the N-channel non-doped MOS transistor MND4.

Here, since the transistor MP5 operating as a constant current source is connected to the drains of the N-channel non-doped MOS transistors MND4 and MND5, the N-channel non-doped MOS transistor MND4
N-channel non-doped MOS transistor MND5 according to the output voltage from node N1 input to the gate of
Is determined. The current flowing through the N-channel non-doped MOS transistor MND5 is the difference between the current flowing from the transistor MP5 and the current flowing through the transistor MND4.

Since transistor MND5 forms a current mirror circuit with N-channel non-doped MOS transistor MND6, a current equal to the current flowing through transistor MND5 flows through transistor MND6, and a current corresponding to this current forms a current mirror circuit. To the transistors MP6 and MP7. Node N
The voltage from 1 is applied to and controls the gate of the N-channel non-doped MOS transistor MND7.

When the operational amplifier of this embodiment performing the above operation is compared with the conventional operational amplifier of FIG. 2, the threshold voltage of N-channel non-doped MOS transistor MND4 is equal to the output voltage of the input stage (the voltage at node N1). )
, The common mode input range of the differential circuit is G
Even when the bias current is lowered to the ND side, the bias current supplied from the transistor MP5 flows through the transistors MND4 and MND5 in substantially equal amounts, respectively, and the phase inversion input transistor MND4
And the phase inversion output transistor MND5 can be balanced.

The present invention is not limited to the above-described embodiment, and various other modifications are possible without departing from the gist of the present invention.

[0029]

As described above, according to the present invention,
The phase inverting input transistor and the phase inverting output transistor of the phase inverting output stage are constituted by non-doped MOS transistors, so that the phase inverting input transistor and the phase inverting output transistor have a sufficiently lower threshold value than the output signal voltage of the input stage. Can be operated with the conventional MO
Compared to the S transistor, even if the common mode input range of the differential circuit in the input stage is lowered to the GND side, the balance between the phase inversion input transistor and the phase inversion output transistor can be maintained, and therefore, the degree of freedom in the application of the operational amplifier can be improved. Can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

FIG. 3 is a circuit diagram of another example of the related art.

[Explanation of symbols]

MP1 to MP7 P-channel MOS transistors MND1 to MND7 N-channel non-doped MOS transistors C1 Capacitor for phase compensation R1 Resistance for phase compensation

Claims (6)

(57) [Claims] An input stage for differentially amplifying an input signal; a bias circuit for supplying a bias signal to the input stage; a phase inversion output stage for inverting the output signal of the input stage and outputting the inverted signal; An output stage for compensating and outputting the output signal of the phase inversion output stage.
The phase inversion output stage includes a constant current source transistor, a phase inversion input transistor to which an output signal of the input stage is input, and a phase inversion in which a current flowing by the phase inversion input transistor and the constant current source transistor is determined. An output transistor, wherein the constant current source transistor comprises a first conductivity type MOS transistor, and the phase inversion input transistor and the phase inversion output transistor each comprise a second conductivity type non-doped MOS transistor. An operational amplifier characterized in that: 2. The input stage, comprising: a first transistor having the same conductivity type as the first conductivity type having a gate connected to a first input terminal;
An OS transistor, a second MOS transistor having a gate connected to a second input terminal, and having the same conductivity type as the first conductivity type, differentially connected to the first MOS transistor; And a first current mirror circuit forming a constant current source connected to the source side of the second MOS transistor, and a second current for a load connected to the drain side of the first and second MOS transistors. The two transistors constituting the second current mirror circuit are non-doped MOS transistors of the same conductivity type as the second conductivity type, and an output signal is taken out from the drain of the second MOS transistor. The operational amplifier according to claim 1, wherein: 3. The first conductivity type is a P-channel,
3. The operational amplifier according to claim 1, wherein the second conductivity type is an N-channel. 4. A first MOS transistor of a first conductivity type, a second MOS transistor of a first conductivity type forming a current mirror circuit with the first MOS transistor, and the first MOS transistor A first non-doped MOS transistor of a second conductivity type having a drain connected to the drain thereof and a gate connected to the bias voltage input terminal, a gate connected to the first input terminal, and
A third MOS transistor of a first conductivity type having a source connected to the drain of the second MOS transistor;
A fourth MOS transistor of a first conductivity type having a gate connected to the second input terminal and a source connected to the drain of the second MOS transistor; and a gate connected to the gate of the first MOS transistor. Connected to the first
5th MOS transistor of the first conductivity type and sixth and 7th conductivity type of the first
MOS transistor, a second non-doped MOS transistor of a second conductivity type having a drain connected to the drain of the third MOS transistor, and the fourth MO transistor.
A third non-doped MOS transistor of a second conductivity type having a drain connected to the drain of the S transistor and forming a current mirror circuit with the second non-doped MOS transistor; the fourth MOS transistor and the second MOS transistor; A fourth non-doped MO of the second conductivity type for a phase inversion input, having a gate connected to a common connection point of both drains of the non-doped MOS transistor and a drain connected to the drain of the fifth MOS transistor
An S transistor, a fifth non-doped MOS transistor of the second conductivity type for phase-inversion output having a gate and a drain connected to the drain of the fourth non-doped MOS transistor, and a gate connected to the fifth non-doped MOS transistor. A sixth non-doped MOS transistor of a second conductivity type having a gate connected, a gate and a drain of the sixth MOS transistor, and a drain connected to a gate of the seventh MOS transistor;
The seventh MOS transistor of the second conductivity type has a gate connected to a common connection point of both drains of the third MOS transistor and the third non-doped MOS transistor, and a drain connected to the drain and the output terminal of the seventh MOS transistor. And a capacitor connected in series between a common connection point of both drains of the fourth MOS transistor and the third non-doped MOS transistor and both drains of the sixth and seventh non-doped MOS transistors. And an operational amplifier comprising: a resistor; 5. The first to seventh MOS transistors are P-channel MOS transistors, and the first to seventh non-doped MOS transistors are N-channel non-doped MOS transistors.
Each source of the fifth, sixth, and seventh MOS transistors is connected to a high-potential-side power supply terminal, and each source of the first to seventh non-doped MOS transistors is connected to a low-potential-side power supply terminal. The operational amplifier according to claim 4, wherein: 6. The transistor according to claim 4, wherein the first to seventh MOS transistors and the first to seventh non-doped MOS transistors are transistors each having a back gate and a source connected to each other. Operational amplifier.