JPH01280858A - Lock control system for main storage device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a main storage device due to a lock access by storing a lock instruction to its address in a buffer tag array when the lock instruction is unsuccessful and referring to the lock unsuccessful bit of the buffer tag array for the access of the lock instruction to the main storage device. CONSTITUTION:When the lock instruction is made access to the main storage device and it is unsuccessful, it is stored in the lock unsuccessful bit 72 of the address provided in the buffer tag array 7. Then, when the lock instruction is unsuccessful, even if the lock instruction is repeatedly outputted, the access of the lock instruction thereafter is not carried out by referring to the buffer tag array 7 to the main storage device. Thereby, an excessive lock access to the main storage device is reduced and the processing efficiency of the main storage device can be improved for that.

Description

[Detailed Description of the Invention] [Summary] Regarding a lock control method for a main memory device that refers to an unsuccessful lock focus of a buffer tag array of a buffer, focusing on a device with a built-in buffer, the main memory device using lock access is The purpose of the present invention is to provide a method for preventing performance deterioration of a main storage device, and when the processor accesses one address of a main storage device shared by a plurality of processors, the address of the main storage device is locked by a lock instruction prior to the access. This is a method that occupies access to the main storage device, and provides a lock failure bit at each address of a buffer tag array that stores the real address of the data in the main memory stored in the buffer, and refers to the lock failure bit. a lock failure processing unit for processing a lock instruction to access the main storage device, and if the lock instruction is unsuccessful, storing it in the corresponding address of the buffer tag array;
The lock instruction access to the main storage device is performed by referring to the lock failure bit of the buffer tag array.

[Industrial application field]

The present invention relates to a lock control method for a main memory device that refers to a lock failure bit in a buffer tag array of a buffer.

In a system where multiple processors share the main memory, when accessing the main memory using a lock instruction, the exclusive right to that address is taken and then the data at that address is accessed. It protects the data being accessed by eliminating access from the processor.

When the lock access is unsuccessful, the processor immediately repeats the same lock access and waits for the lock to succeed, or processes another job (see FIG. 5).

However, the main memory needs to process lock accesses that each processor continues to manipulate and return after each processor sees a lock failure, and this processing reduces the effective efficiency of the main memory.

Therefore, it is required to increase the processing efficiency of the main storage device by controlling this lock access.

[Conventional technology]

FIG. 3 is a diagram explaining the lock control logic configuration of a conventional example. FIG. 4 is a flowchart diagram of FIG. 3.

Conventionally, common lock access is performed as follows.

Normally, when the instruction input to the instruction register is recognized as a lock instruction, a lock fetch access is unconditionally issued to the main memory regardless of whether there is data in the buffer.

That is, in FIG. 3, when the lock instruction stored in the instruction register 1 is recognized as a lock instruction by the decoder 3, a lock access signal is stored in the lock access register 4, and a main storage unit (MSU) request signal is generated. is issued to MSU request register 5, and the address of the lock instruction stored in operand register 2 is
The signals and data of these registers are stored in the U address register 6 and output to the main memory.

On the other hand, as described above, the buffer tag array 7 stores addresses on the main storage device of data stored in buffers (not shown), that is, real addresses.

Then, store accesses from other devices are disabled by the buffer invalidation signal, and the address of the data transferred from the main memory device to the buffer is written into the buffer tag array 7 by the move-in signal.

That is, the tag validity bit 7 is set by the buffer invalidation signal.
1 becomes "0" and becomes rlJ by the move-in signal.

In a normal main memory access instruction, the main memory is accessed when there is no match between the address stored in the operand register 2 and the address stored in the buffer tag array 7.

If they match, the buffer is accessed without accessing the main memory.

Hereinafter, in the flowchart of FIG. 4, the main storage device checks whether there is an issued lock address, and if so, compares the lock access address with the input lock access address. If they are equal, wait until the previous access is released.

Once released, the next lock address is set, and subsequent use of the same lock address by other devices is prohibited.

When it is determined that the input data can be locked, the newly input data is replaced with the lock data, that is, the newly input data is stored in the main memory, and the main memory ends the lock at that point.

Then, the condition code CC indicating that the lock access was successful is set to "0".

When the entered data was impossible to lock,
The device that issued the lock access instructs the main storage device to terminate the lock access.

Then, the condition code CC is set to "1".

[Problem to be solved by the invention]

As described above, in the conventional method, lock access is always performed on the main storage device, but because the lock access is performed without knowing whether or not it has been released, the throughput of the system deteriorates.

The present invention was created in view of these points, and an object of the present invention is to provide a method for preventing performance deterioration of a main memory device due to lock access, focusing on a device with a built-in buffer.

[Means to solve the problem]

In order to achieve the above-mentioned purpose, a lock failure bit is provided at each address of the buffer tag array that stores the real address of the data in the main memory stored in the buffer, and a lock failure processing section is provided. If the instruction is unsuccessful, store it at that address in the buffer tag array, and access the lock instruction to main memory by
Perform this by referring to the lock failure bit in the buffer tag array.

[For production]

When a lock instruction is unsuccessfully accessed to the main memory, it is stored in a lock failure bit of the address provided in the buffer tag array.

Even if the configuration is such that the lock command is repeatedly output when the lock command is unsuccessful, subsequent lock command accesses refer to the buffer tag array to store the lock command in the main memory. There is no access.

Therefore, unnecessary lock accesses to the main memory are reduced, and the processing efficiency of the main memory can be improved accordingly.

(Embodiment) FIG. 1 is a diagram illustrating a control logic configuration of a lock control method for a main storage device of the present invention, and FIG. 2 is a flowchart diagram of FIG. 1.

In FIG. 1, 72 is a lock failure bit provided at the real address of the main memory stored in the buffer tag array 7, and 8 is a lock failure processing unit.

Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the present invention will be mainly explained with reference to the flowchart of FIG. 2 and the parts added to the control method described in the section of the prior art described above.

(2) When the lock command is unsuccessful, rlJ is written to the lock failure bit 72 of the address in the buffer tag array 7.

■When accessing a lock, the buffer tag array 7 is always accessed, and even if validity is confirmed by the tag validity bit 71 (tag validity bit 71 is rlJ), the lock is unsuccessful (lock failure bit 72 is ``l''), no access is issued to the main memory.

In other words, since the lock was unsuccessful, the device waits for unlock from another device.

(2) When an instruction to release the lock is received from another device, the tag validity bit 71 of the buffer tag array 7 is set to "0".

- When accessing a tag address where the tag validity bit 71 is "1", an access is issued to the main memory.

■When data is transferred from the main memory, the tag validity bit 71 is set to "1" and the lock failure bit 7 is set to "1".
Set 2 to "0".

When a lock failure is stored in the buffer tag array 7 and the operand address of the lock instruction and the real address of the buffer tag fail, the lock failure processing unit 8 sends an MSU request signal and a lock access signal to the main storage device. do not send.

That is, steps A and B in FIG. 4 are added, and when the lock is unsuccessful, the next lock instruction will not access the main memory, and the processing of the 1a device will be reduced.

Note that the above main memory may also be a data processing resource,
It goes without saying that the control method of the present invention can also be applied to devices that use processor resources.

〔Effect of the invention〕

As is clear from the above description, the present invention reduces the access load on the main memory, improves access efficiency, and speeds up the processing of the entire system, making it extremely useful industrially. .

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the control logic configuration of an embodiment of the main memory lock control method of the present invention, FIG. 2 is a flowchart diagram of FIG. 1, and FIG. 3 is a diagram explaining the control logic configuration of a conventional example. FIG. 4 is a flowchart of FIG. 3, and FIG. 5 is a diagram explaining lock control. In the figure, 7 is a buffer tag array, 72 is a lock failure bit, and 8 is a lock failure processing unit. O 37 ＾ Flow 1↑ - Toro 4th figure

Claims (1)

[Scope of Claims] When the processor accesses one address of a main memory shared by a plurality of processors, the access to the address of the main memory is occupied by a lock instruction prior to the access. A lock failure bit (72) is provided at each address of the buffer tag array (7) storing the real address of the data in the main memory stored in the buffer, and the lock failure bit (72) is referred to. a lock failure processing unit (
8), and if the lock instruction is unsuccessful, it is stored in the corresponding address of the buffer tag array (7), and when the lock instruction accesses the main memory, the buffer tag array (7) A lock control method for a main memory device characterized by: