JPH01276343A - Tracing device - Google Patents

Abstract

PURPOSE:To trace a hardware signal by providing a means which compares the address value set externally and the address value of a memory storing an instruction under execution in an information processor. CONSTITUTION:An address which is used as a trigger is set at an address register 5 via a keyboard, etc., of a service processor 1 and through a diagnosing bus 2. A diagnosing bus control part 10 compares the set address value with the address value 18 of a microinstruction under execution. When the coincidence is obtained between both address values, the address coincidence signals 3 and 7 are transmitted to the processor 1 and a write control part 8 respectively. Then a memory part 15 stores the interface signals successively in the addresses shown by the address signal 11 sent from the part 8. At the same time, the changing state of the interface signal set after transmission of the coincidence signal is traced within the part 15. Thus the processor 1 can read the trace data 19 out of the part 15 and then investigate a fault.

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a toss device, and more particularly, to a system that tracks output signals from predetermined observation points within an information processing device.
Concerning lace equipment. Prior Art Conventionally, in an information processing device 6 such as a computer, a hardware signal (for example, an output signal of an interface) is
~ Didn't have the ability to race. Therefore, if a failure occurs within the □ti'i information processing device,
There was a drawback in that a measuring instrument with a tracing function was required to investigate the cause of such problems. OBJECTS OF THE INVENTION It is an object of the invention to provide a 1-to-race device capable of tracing hardware signals. Structure of the Invention The tracing device of the present invention is a tracing device that traces output signals of predetermined observation points in an information processing device from 1 to 1, and is configured to trace output signals of predetermined observation points in an information processing device. - Comparing means for comparing the address value of the storage device in which the instruction being executed is stored; and storage means for sequentially storing the output signal after the comparison result of the comparing means indicates a match. It is characterized by EXAMPLE Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a system diagram showing the configuration of an embodiment of a first to second base apparatus according to the present invention. In this country, the race device 1 to 20 according to an embodiment of the present invention includes a Zapis processor (SVI) 1, a write control section 8, a diagnostic bus control section 10, and a storage section 15.
, and a reading control section 17, and is installed in the information processing device; η. Note that 2 is a diagnostic bus, and 9 is an internal processor of the information processing device. Also 1
4 is a ratpin boss)~, which is lappin connected in advance to an important intertacosheath Shinzuki (not shown), which is necessary for the investigation of the fault W. Zahis Processor] is an A-board (not shown), CR'T
” and a processing device. The write control section 8 controls writing/reading of the storage section 15. Reference numeral 11 indicates an address signal, and 12 indicates an output 1 bit enable. No. 8 (OE) and No. 13 are Rai 1 Hey Enable 偕'+'; (w1= ). It compares the near address C1η set to t with the address value 18 of the microphone command being executed once, and if the comparison result shows a match, write the address ``match signals 3 and 7 as service processor 1''. This is to send people to the control unit 8. Note that 6 is a read signal. The storage section 15 sequentially stores the output signals of the interface circuits and the spacer circuits connected to the wrapping bosses I-1 and I-4 under the control of the write control section 8. The continuation control section 17 has a continuation register 16, and this continuation register 16 temporarily stores the outputs of the readout record/hoof section 15, 1 to 19, under the control of the write control section 8. . When J'5 has such a configuration and races from 1 to 1, the stopping worker or the like must address it via the diagnostic bus 2 using the board, etc. of Zerpisp attack 1, and do not use it as a trigger for register 5. (In other words, I want to do llj,!a!II) Set the address to cella 1. ,〉 address register 5 is set to Sera 1 to At 1.・Is the value of Mike X'? Instructions (Tour unevenness. 4A) are recorded/admonished internal program 1-7-sen''memory'! A1 in A position

[Response. Note that the address value held in the address register 5 is constantly compared with the attos value 18 during execution. If the comparison result does not indicate a match, match signals 3 and 7 are sent out. When the write control unit 8G receives the core address match signal 7 (J), it sets the memory address signal 11 to "UO" (minimum address) and sends a write pulse to the write control unit 8 (No. 4 13). As the address value of the address signal 11 increases, the address value of the address signal 11 is increased in response to the write pulse.
When the maximum address of 5 is reached, the sending of write pulses is stopped. In response to this operation, the storage section 15 sequentially stores the interfaces J and -S in the addresses indicated by the addresses 11 and 11 from the write control section 8. Through the above operations, the state of change of the interface signal after sending out the address match signal is raced from 1 to 1 in the storage section 15. On the other hand, the address number 3 is also input manually to the service processor 1. The Zahis processor 1 performs the following processing operation after a predetermined period of ++i1 from the input of the address match signal 3 (after completion of tracing). First, the diagnostic controller 1 sends a read command to the diagnostic controller 10 . Then, the diagnostic bus control section], O
l-J, sends the read previous issue 6 to the write control unit 8. When the write control unit 8 i, :J receives this read 154 No. 6), it sequentially increases the address value indicated by the address signal 1, and the address signal 11 of 1 and -, and the address signal 11 of 1 to 1. l-enable signal 13 and is sent to the record/b section 15. The read control unit 17 stores the 1 race data 19 sent from the storage unit 15 in the successive output register 16 . Then, by scanning the diagnostic bus 2, the Zahisp explorer 1 sells 3 sales registers 16 and
Displayed on R"f" etc. By repeating the above 4 readout processing operations, it is possible to read out all the l-race data stored in the storage unit 15.
+1 ability, [樟τ1fl17)] can be investigated. In other words, by installing this device in an information processing device and connecting the points expected to cause a failure or the points to be observed with the points 1 to 14 in advance, the hardware signals can be easily transmitted. 1~ You can race. As described in detail, by providing the 1-to-race device according to the present invention in an information processing device, it is possible to easily depack hardware signals and investigate faults without using a measuring device having a 1-to-lace function. There is an effect that it can be done. 11. Explanation of Sections of the Drawings FIG. 1 is a system diagram showing the configuration of a lace device according to an embodiment of the present invention. Explanation of symbols of main parts■...Server sp+7Setsuza8...Writing control section 10...High cutting lotus control section 17'l...Wrapping boss 1~

Claims (1)

[Claims] (1) A tracing device that traces output signals from predetermined observation points within an information processing device, and a storage device that stores address values set from the outside and instructions being executed in the information processing device. 1. A tracing device comprising: a comparison means for comparing the address value of the output signal; and a storage means for sequentially storing the output signal after the comparison result of the comparison means indicates a match.