JPH01272121A - Through-hole structure and manufacture thereof - Google Patents
Through-hole structure and manufacture thereofInfo
- Publication number
- JPH01272121A JPH01272121A JP10039388A JP10039388A JPH01272121A JP H01272121 A JPH01272121 A JP H01272121A JP 10039388 A JP10039388 A JP 10039388A JP 10039388 A JP10039388 A JP 10039388A JP H01272121 A JPH01272121 A JP H01272121A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- etching
- layer
- hole
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims abstract description 70
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 61
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 230000002950 deficient Effects 0.000 abstract 1
- 239000000203 mixture Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229920000620 organic polymer Polymers 0.000 description 3
- 239000002861 polymer material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路におけるスルーホール構造とその製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a through-hole structure in an integrated circuit and a method for manufacturing the same.
第3図(a) 、 (b)は、従来のスルーホールの形
成方法を示したものである。第3図(al 、 (bJ
中、1は半導体デバイスを集積してなる基板、2は層間
絶縁膜、3は絶縁膜の表面、4,5.6はスルーホール
、7,8.9は電極、1θ、11.12は電極の露出部
分、13はホトレジストである。層間絶縁膜2の表面3
の平坦化は配線の伝達特性の均質化を向上させ、配線の
断線および線間の漏れ電流防止に有効なことから、配線
の微細化に伴い必須となっている。一般に多層配線にお
ける平坦化は凹凸のある下地上になされるため、表面3
の平坦度が向上する程、ホトレジスト13の開口部にエ
ツチングによって形成されるスルーホール4.5と6の
深さの差は下地の凹凸の持っている段差の高さに近スく
ことになる。このためスルーホール4.5とスルーホー
ル6を形成する際のエツチングに必要な時間が異なシ、
浅い方のスルーホール6の下地である電極9の露出部分
12は、スルーホール6のエツチングが完了した後も、
深め方のスルーホール4,5の形成が完了するまでエツ
チング雰囲気にさらされることKなる。この場合、層間
絶縁膜2のエツチングレートをa、下地である電極9の
エツチングレートをbとし、スルーホール4.5および
6の深さをそれぞれH4、H5およびH6とする。エツ
チング完了時に下地である電極9がエツチングされる深
さH9はH4=H5として少なくとも
h9=b(H4−H6)/a
となる。こうした下地のエツチングは不必要なばかりで
なく、配線不良の原因にもなる。また、エツチングによ
るバタン変換差はエツチング完了後にエツチング雰囲気
にされることによシ増加しやすいので、・ぐタンの微細
化の観点からもエツチング時間の均一化が必要である。FIGS. 3(a) and 3(b) show a conventional method for forming through holes. Figure 3 (al, (bJ
Inside, 1 is a substrate formed by integrating semiconductor devices, 2 is an interlayer insulating film, 3 is the surface of the insulating film, 4, 5.6 are through holes, 7, 8.9 are electrodes, 1θ, 11.12 are electrodes The exposed portion 13 is photoresist. Surface 3 of interlayer insulating film 2
Planarization improves the homogeneity of the transmission characteristics of the wiring, and is effective in preventing disconnection of the wiring and leakage current between the lines, so it has become essential as the wiring becomes finer. Generally, planarization in multilayer wiring is done on an uneven base, so the surface 3
As the flatness of the photoresist 13 improves, the difference in depth between the through holes 4.5 and 6 formed by etching in the opening of the photoresist 13 becomes closer to the height of the step of the underlying unevenness. . For this reason, the etching times required to form through holes 4.5 and 6 are different.
The exposed portion 12 of the electrode 9, which is the base of the shallower through hole 6, remains unchanged even after the etching of the through hole 6 is completed.
The through holes 4 and 5 are exposed to the etching atmosphere until the formation of the deeper through holes 4 and 5 is completed. In this case, the etching rate of the interlayer insulating film 2 is a, the etching rate of the underlying electrode 9 is b, and the depths of the through holes 4.5 and 6 are H4, H5, and H6, respectively. When etching is completed, the depth H9 to which the underlying electrode 9 is etched is at least h9=b(H4-H6)/a, assuming H4=H5. This underlying etching is not only unnecessary, but also causes wiring defects. Further, since the difference in batten conversion due to etching tends to increase by being placed in an etching atmosphere after etching is completed, it is necessary to make the etching time uniform from the viewpoint of finer etching.
さらに、エツチングレートaとH4、H5のばらつきを
許容するべくエツチング時間u H4/ a以上の時間
なされる。Further, in order to allow variations in the etching rate a and H4 and H5, the etching time is longer than uH4/a.
その時、場合によってはすでに下地面が露出した後もオ
ーバーエツチングがなされるので、あるばらつき値のも
とでは下地のエツチング−i H層間絶縁膜2の厚さに
比例する。At this time, in some cases, over-etching is performed even after the underlying surface has been exposed, so that under a certain variation value, the etching of the underlying surface is proportional to the thickness of the interlayer insulating film 2.
本発明は上記の事情に鑑みてなされたもので、スルーホ
ールの形成において、異なる深さのスルーホールのエツ
チング時間を等しくシ、スルーホールの接続歩留シの向
上と・母タン変換差のばらつきを防止し定スルーホ〜ル
構造およびその製造方法を提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances.The present invention has been made in view of the above-mentioned circumstances.In forming through-holes, it is possible to equalize the etching time of through-holes of different depths, improve the connection yield of through-holes, and ・dispersion of mother tongue conversion difference. It is an object of the present invention to provide a fixed through-hole structure and a method for manufacturing the same.
本発明は上記目的を達成するために、基板表面には導電
性層または不純物拡散領域が形成されてなり、該表面上
に第1の絶縁性層と第1の絶縁性層上に第1の絶縁性層
とは異なる材料からなる第2の絶縁性層と第2の絶縁性
層上に第2の絶縁性層とは異なる材料からなる第3の絶
縁性層が積層して絶縁膜層をなし、該絶縁膜層にスルー
ホールが形成されてなることを!特とするもの、又、上
記スルーホールの製造方法において、ホトレジストをマ
スクにして第、3の絶縁性層をエツチングする第1の工
程と第2の絶縁性層をエツチングする第2の工程と第1
の絶縁性層をエツチングする第3の工程とよりなシ、第
1の工程と第2の工程の少なくとも一方において当該絶
縁性層のエツチングレートが下地絶縁性層のエツチング
レートより大きいことを特徴とするものである。In order to achieve the above object, the present invention includes a conductive layer or an impurity diffusion region formed on the surface of a substrate, a first insulating layer on the surface, and a first insulating layer on the first insulating layer. A second insulating layer made of a material different from that of the insulating layer and a third insulating layer made of a material different from the second insulating layer are laminated on the second insulating layer to form an insulating film layer. No, a through hole is formed in the insulating film layer! Particularly, in the above method for manufacturing a through hole, the first step of etching the third insulating layer using a photoresist as a mask, the second step of etching the second insulating layer, and the third step of etching the third insulating layer using a photoresist as a mask. 1
The third step of etching the insulating layer is characterized in that in at least one of the first step and the second step, the etching rate of the insulating layer is higher than the etching rate of the underlying insulating layer. It is something to do.
本発明は、スルーホールを形成する層間絶縁膜の膜構成
を最上層の絶縁性層と最上層絶縁性層とは異なる組成の
中間絶縁性層と中間絶縁性層とは異なる組成の最下層絶
縁性層の31膜構成とし、異なる深さのスルーホールの
エツチング時間を最上層絶縁性層のエツチング時間と中
間絶縁性層のエツチング時間と最下層絶縁性層のエツチ
ング時間とに区分し、最上層のエツチングにおいて中間
層絶縁性膜のエツチングレートを極めて小さくすること
によ)最上層絶縁性膜の膜厚の異なる場合も中間絶縁性
層のエツチング量を少なくする。最上1−P3縁柱層部
のエツチング完了後、残った中間絶縁性層と最下層絶縁
性層をエツチングしてスルーホールを形成する訳である
が、異なる深さのスルーホールにおいても中間絶縁性層
と最下I−絶縁性層の膜厚を等しくしておくことによシ
スルーホールのエツチング時間を同一にすることができ
る。The present invention provides a film structure of an interlayer insulating film forming a through hole, including an uppermost insulating layer, an intermediate insulating layer having a composition different from the uppermost insulating layer, and a lowermost insulating layer having a composition different from the intermediate insulating layer. The etching time for through holes of different depths is divided into the etching time for the uppermost insulating layer, the etching time for the middle insulating layer, and the etching time for the lowermost insulating layer. By making the etching rate of the intermediate insulating film extremely small during etching, the amount of etching of the intermediate insulating layer can be reduced even when the thickness of the uppermost insulating film is different. After the etching of the uppermost 1-P3 edge column layer is completed, the remaining intermediate insulating layer and the lowermost insulating layer are etched to form through holes, but the intermediate insulating properties can be maintained even in through holes of different depths. By making the film thicknesses of the layer and the bottom I-insulating layer the same, the etching time for the through holes can be made the same.
この時、エツチングレートや膜厚のばらつきに対するマ
ージンとしてのスルーホール下地のオーバーエツチング
fは最下層絶縁性層にのみ依存するので、同じ深さのス
ルーホールを形成する場合、従来技術よシもオーバーエ
ツチング時間を短縮でき、かつオーバーエツチング時間
を等しくできるのでスールホール形成にともなう特性ば
らつきを無くすことができる。At this time, the over-etching f of the through-hole base, which serves as a margin for variations in etching rate and film thickness, depends only on the bottom insulating layer. Since the etching time can be shortened and the over-etching time can be made equal, variations in characteristics due to the formation of through holes can be eliminated.
以下図面を参照して本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第1図は、本発明によるスルーホール構造の一実施例を
示す断面図である。図において1#′i表面に導電性層
または不純物拡散領域が形成された半導体デ・ぐイスを
集積してなる基板、2011”!絶縁膜、30は20と
材質の異なる緑絶膜、40は30と材質のことなる絶縁
膜、4,5および6はスルーホール、7,8および9は
電極、13はホトレジストである。FIG. 1 is a sectional view showing an embodiment of a through-hole structure according to the present invention. In the figure, 1#'i is a substrate formed by integrating semiconductor devices with a conductive layer or an impurity diffusion region formed on its surface, 2011''! insulation film, 30 is a green insulation film made of a different material from 20, 40 is 30 is an insulating film made of a different material, 4, 5 and 6 are through holes, 7, 8 and 9 are electrodes, and 13 is a photoresist.
以下、第1図に示したスルーホールの製造方法を第2図
を用いて説明する。Hereinafter, a method for manufacturing the through hole shown in FIG. 1 will be explained using FIG. 2.
即ち、第2図(sJに示すように、半導体デ・ぐイス、
たとえばMO8電界効果トランジスタを集積してなる基
板1の主面にはダート電極9による段差が存在する。該
主面上に、たとえばSlO□を材料とした絶縁膜20を
被着する。5IO2の被着は気相反応によってモ、スノ
母ツタリンクマタハバイアススノ苧ツタリングによって
も可能である。5102の膜厚は上記電極を被覆できる
膜厚であればよく、いま、グー)[極9の高さを500
nmとすると、この高さにたいして100 nm程度
でよい。絶縁1!!!20としては5t3N4でもよい
。続いて、ノンドーグのアモルファスS1を材料とし気
絶縁膜30を100 nrn程度の膜厚で被着する。ア
モルファスStの被着は熱分解反応によってもプラズマ
反応によってもス・9ツタリングによってもよく、段差
部分の被覆性の良否はどうでもよい。続いて、再びS1
0□をダート11L極9の段差以上の膜厚で堆積しエッ
チパック法等の表面平坦化法により平坦化された絶縁膜
40の表m13を得る。そのため、たとえばこの上に有
機高分子材層を塗布し、これを熱処理して平坦な表面を
有する配線構造体を形成する。次に、このように構成さ
れた配線構造体の表面を例えばリアクティブ イオン
エツチング(RIE )によって絶縁膜40と有機高分
子材層のエツチングレートが同一となる条件でエツチン
グし、絶縁M40の凸部を有機高分子材層のエツチング
と同時に除去して平坦面3を得る。That is, as shown in FIG. 2 (sJ), a semiconductor device,
For example, a step formed by a dirt electrode 9 exists on the main surface of a substrate 1 on which MO8 field effect transistors are integrated. An insulating film 20 made of, for example, SlO□ is deposited on the main surface. Deposition of 5IO2 is also possible by vapor phase reaction, or by sino-motsutaring. The film thickness of 5102 may be as long as it can cover the above electrode.
If the height is 100 nm, then the height may be about 100 nm. Insulation 1! ! ! 20 may be 5t3N4. Subsequently, a vapor insulating film 30 made of non-dawg amorphous S1 is deposited to a thickness of about 100 nrn. The amorphous St may be deposited by a thermal decomposition reaction, a plasma reaction, or a sputtering method, and it does not matter whether the step portion is coated well or not. Then, S1 again
A surface m13 of the insulating film 40 is obtained by depositing 0□ to a thickness equal to or greater than the step difference of the dirt 11L pole 9 and flattening it by a surface flattening method such as an etch pack method. Therefore, for example, an organic polymer material layer is applied thereon and heat treated to form a wiring structure having a flat surface. Next, the surface of the wiring structure configured in this way is treated with reactive ions, for example.
Etching (RIE) is performed under conditions such that the etching rate of the insulating film 40 and the organic polymer material layer are the same, and the convex portion of the insulating film M40 is removed simultaneously with the etching of the organic polymer material layer to obtain a flat surface 3.
次に、ホトリングラフィ工程によシホトレジスト13を
パタンニングしスルーホールの開口位置を露出して表面
3上をホトレジストで被覆°する。Next, the photoresist 13 is patterned by a photolithography process to expose the opening positions of the through holes, and the surface 3 is covered with the photoresist.
次に、第2図(b)に示すように、スルーホールのエツ
チングは、通常のRIE装置を用い、エツチングy ス
K CHF3102混合カスを流量比9 / 75 S
CCM。Next, as shown in FIG. 2(b), the through-holes were etched using an ordinary RIE device, and the etching ys-K CHF3102 mixture was heated at a flow rate ratio of 9/75S.
C.C.M.
圧力50 mTorr、 RF を力1000W印加し
た場合には、S量0□のエッチレートは36nm/分、
アモルファスS1のエツチングレートは4層m/分であ
る。When a pressure of 50 mTorr and an RF force of 1000 W are applied, the etch rate for an S amount of 0□ is 36 nm/min.
The etching rate of amorphous S1 is 4 layers m/min.
今、例として、スルーホール4.5の深さを11000
n、スルーホール6の深さを500 nmとする。この
場合、スルーホール4.5の最上層5102の膜厚は8
00nm、スルーホール6の最上層SlO□の膜厚は3
00 nmとなる。エッチレートと膜厚のばらつきに対
するマージンとして2096のオーバーエツチングを想
定するとスルーホール6のアモルファスS1層は最上層
S10□のエツチング完了までに約74 nmのオーバ
ーエツチングをうける0これは全アモルファスSi層の
厚さの74%をエツチングしたことになる。次に、第2
図(e)に示すように、中間層たるアモルファスS1の
エツチングは、円筒型または平行平板型のプラズマエツ
チング装置を用い、エツチングガスにCF4102混合
ガスを流量比9515SCCM、圧力500 mTgr
r、RF tc力150W印加した場合には、Siのエ
ッチレートは150nm 7分、SiO□のエッチレー
トは10 nm 7分となシはぼアモルファスSiのみ
を等方的にエツチングする。Now, as an example, the depth of through hole 4.5 is 11000.
n, and the depth of the through hole 6 is 500 nm. In this case, the thickness of the top layer 5102 of the through hole 4.5 is 8.
00 nm, and the thickness of the top layer SlO□ of through hole 6 is 3
00 nm. Assuming over-etching of 2096 nm as a margin for variations in etch rate and film thickness, the amorphous S1 layer of through hole 6 will be over-etched by approximately 74 nm by the time the top layer S10□ is etched. This means that 74% of the thickness was etched. Next, the second
As shown in Figure (e), the amorphous S1 that is the intermediate layer is etched using a cylindrical or parallel plate type plasma etching device, using a CF4102 mixed gas as the etching gas at a flow rate of 9515 SCCM and a pressure of 500 mTgr.
When an RF tc force of 150 W is applied, the etch rate for Si is 150 nm for 7 minutes, and the etch rate for SiO□ is 10 nm for 7 minutes, so that only amorphous Si is isotropically etched.
また、通常のRIE装置においても同様のエツチングガ
スによシSlと5IO2のエッチレート比を5対1程度
にでき、仁の場合は、Slエツチング完了後にスルーホ
ール6では最下層S102g(の上部ニ20nmのエツ
チングが生じるが、はとんど問題とならない。次に、第
2図(d)に示すように、最下層5IO2のエツチング
は最上層と同じエツチング条件で行う。上記のごとく2
0係のオーバーエツチングを想定すると下地IIf極に
対するオーバーエツチング時間はあらゆるスルーホール
において等[、< 0.6分となυ、実用上まったく問
題とならない。Also, in a normal RIE device, the etch rate ratio of Sl and 5IO2 can be set to about 5:1 using the same etching gas. Etching of 20 nm occurs, but this is rarely a problem.Next, as shown in FIG. 2(d), the bottom layer 5IO2 is etched under the same etching conditions as the top layer.
Assuming zero factor overetching, the overetching time for the underlying IIf electrode is equal to <0.6 minutes for all through holes, which poses no practical problem at all.
このように、層間絶縁膜を3層構造とし、中間層のエツ
チングレートを最上層のエツチングレートよりも小さく
することによシ、主面に段差を持ち表面3の平坦な配線
構造体では、深さの異なるスルーホールのエツチング完
了時間を等しくすることができる。その結果、オーバー
エツチング時間の短縮が大幅にできるので、オーバーエ
ツチングに伴うスルーホールの接続不良やノナタン変換
差の増加を防止できる。尚、最下層のエツチングレート
を中間層のエツチングレートよりも小さくしてもよく、
この場合にも上記と同様の効果を得ることができる。In this way, by forming the interlayer insulating film into a three-layer structure and making the etching rate of the middle layer smaller than the etching rate of the top layer, a wiring structure with a step on the main surface and a flat surface 3 can be etched deep. The etching completion time for through holes of different sizes can be made equal. As a result, the over-etching time can be significantly shortened, thereby preventing through-hole connection failures and increases in nonatane conversion differences due to over-etching. Note that the etching rate of the bottom layer may be lower than the etching rate of the middle layer.
In this case as well, effects similar to those described above can be obtained.
以上説明し九様に、本発明ではスルーホールのオーツク
ーエツチング時間の短縮がはかられる。その効果として
はオーバーエツチングに伴5スルーホール下地のエツチ
ング量が減少するので配線接続歩留りが向上する。さら
に効果としてオーバーエツチング洗体うサイドエツチン
グによるスルーホールの拡大が減少するのでスルーホー
ルエツチング時の・2タンf換差の制御性が向上する。As explained above, the present invention can reduce the auto-quenching time of through-holes. The effect is that the amount of etching on the base of the five through holes is reduced due to over-etching, so that the wiring connection yield is improved. Further, as an effect, the enlargement of the through hole due to over-etching and side etching is reduced, so that the controllability of the 2-tanf conversion difference during through-hole etching is improved.
これは配線ピッチの微細化に有利である。This is advantageous for miniaturizing the wiring pitch.
M1図は、本発明のスルーホール構造の一実施例を示す
断面図、第2図(−)〜(d)は、第1図に示したスル
ーホールの製造方法の一実施例を工程順に示す断面図、
第3図(a)〜(b)は従来のスルーホールの製造方法
の一例を工程順に示す断面図である。
1・・・半導体デバイスを集積してなる基板、2・・・
絶縁k、3・・・最上部絶縁膜の表面、4,5.6・・
・スルーホール、7,8.9・・・電極、10,11゜
12・・・電極の露出部分、13・・・ホトレジスト、
20・・・絶縁膜、3θ・・・絶縁Pa20とは組成の
異なる絶縁膜、40・・・絶縁膜30とは組成の異なる
絶縁膜。
出願人代理人 弁理士 鈴 江 武 彦第2 図Figure M1 is a cross-sectional view showing an embodiment of the through-hole structure of the present invention, and Figures 2 (-) to (d) show an example of the method for manufacturing the through-hole shown in Figure 1 in order of steps. cross section,
FIGS. 3(a) and 3(b) are cross-sectional views showing an example of a conventional through-hole manufacturing method in the order of steps. 1...Substrate formed by integrating semiconductor devices, 2...
Insulation k, 3...Surface of top insulating film, 4,5.6...
・Through hole, 7, 8.9... Electrode, 10, 11° 12... Exposed part of electrode, 13... Photoresist,
20... Insulating film, 3θ... Insulating film having a different composition from the insulating film 20, 40... Insulating film having a different composition from the insulating film 30. Applicant's agent Patent attorney Takehiko Suzue Figure 2
Claims (2)
成されてなり、該表面上に第1の絶縁性層と第1の絶縁
性層上に第1の絶縁性層とは異なる材料からなる第2の
絶縁性層と第2の絶縁性層上に第2の絶縁性層とは異な
る材料からなる第3の絶縁性層が積層して絶縁膜層をな
し、該絶縁膜層にスルーホールが形成されてなることを
特徴とするスルーホール構造。(1) A conductive layer or an impurity diffusion region is formed on the surface of the substrate, and a first insulating layer is formed on the surface and a material different from the first insulating layer is formed on the first insulating layer. A third insulating layer made of a material different from that of the second insulating layer is laminated on the second insulating layer to form an insulating film layer, and a through-hole is formed in the insulating film layer. A through-hole structure characterized by holes.
成されてなり、該表面上に第1の絶縁性層と第1の絶縁
性層上に第1の絶縁性層とは異なる材料からなる第2の
絶縁性層と第2の絶縁性層上に第2の絶縁性層とは異な
る材料からなる第3の絶縁性層が積層して絶縁膜層をな
し、該絶縁膜層にスルーホールが形成されてなるスルー
ホールの製造方法において、ホトレジストをマスクにし
て第3の絶縁性層をエッチングする第1の工程と第2の
絶縁性層をエッチングする第2の工程と第1の絶縁性層
をエッチングする第3の工程とよりなり、第1の工程と
第2の工程の少なくとも一方において当該絶縁性層のエ
ッチングレートが下地絶縁性層のエッチングレートより
大きいことを特徴とするスルーホールの製造方法。(2) A conductive layer or an impurity diffusion region is formed on the surface of the substrate, and a first insulating layer is formed on the surface and a material different from the first insulating layer is formed on the first insulating layer. A third insulating layer made of a material different from that of the second insulating layer is laminated on the second insulating layer to form an insulating film layer, and a through-hole is formed in the insulating film layer. In the method for manufacturing a through hole in which a hole is formed, the first step of etching the third insulating layer using a photoresist as a mask, the second step of etching the second insulating layer, and the first insulating layer are etched. a third step of etching the insulating layer, and the etching rate of the insulating layer is higher than the etching rate of the base insulating layer in at least one of the first step and the second step. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10039388A JPH01272121A (en) | 1988-04-25 | 1988-04-25 | Through-hole structure and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10039388A JPH01272121A (en) | 1988-04-25 | 1988-04-25 | Through-hole structure and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01272121A true JPH01272121A (en) | 1989-10-31 |
Family
ID=14272746
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10039388A Pending JPH01272121A (en) | 1988-04-25 | 1988-04-25 | Through-hole structure and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01272121A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5661084A (en) * | 1996-10-04 | 1997-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for contact profile improvement |
US6071832A (en) * | 1996-03-25 | 2000-06-06 | Nec Corporation | Method for manufacturing a reliable semiconductor device using ECR-CVD and implanting hydrogen ions into an active region |
US6396078B1 (en) | 1995-06-20 | 2002-05-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with a tapered hole formed using multiple layers with different etching rates |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59168640A (en) * | 1983-03-15 | 1984-09-22 | Nec Corp | Manufacture of semiconductor device |
JPS607737A (en) * | 1983-06-27 | 1985-01-16 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-04-25 JP JP10039388A patent/JPH01272121A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59168640A (en) * | 1983-03-15 | 1984-09-22 | Nec Corp | Manufacture of semiconductor device |
JPS607737A (en) * | 1983-06-27 | 1985-01-16 | Nec Corp | Manufacture of semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6396078B1 (en) | 1995-06-20 | 2002-05-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with a tapered hole formed using multiple layers with different etching rates |
US6593235B2 (en) | 1995-06-20 | 2003-07-15 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device with a tapered hole formed using multiple layers with different etching rates |
US6071832A (en) * | 1996-03-25 | 2000-06-06 | Nec Corporation | Method for manufacturing a reliable semiconductor device using ECR-CVD and implanting hydrogen ions into an active region |
US5661084A (en) * | 1996-10-04 | 1997-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for contact profile improvement |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4824521A (en) | Planarization of metal pillars on uneven substrates | |
JPH01290236A (en) | Method of levelling wide trench | |
JPH11330245A (en) | Method for contact formation of semiconductor device | |
JPH0563940B2 (en) | ||
JPH01272121A (en) | Through-hole structure and manufacture thereof | |
JPH11121327A (en) | Semiconductor device and its manufacture | |
JP3191896B2 (en) | Method for manufacturing semiconductor device | |
JPH0313744B2 (en) | ||
JP2628339B2 (en) | Method for manufacturing semiconductor device | |
JP3097338B2 (en) | Method of forming contact hole | |
JPH09129730A (en) | Manufacture of semiconductor device | |
JPS63271958A (en) | Formation of multilayer interconnection | |
JPH098007A (en) | Method for flattening insulation film | |
KR0124646B1 (en) | Metal Film Manufacturing Method of Semiconductor Device | |
JPS61206242A (en) | Manufacture of semiconductor device | |
JP3070564B2 (en) | Method for manufacturing semiconductor device | |
JPH0321024A (en) | Multilayer interconnection structure and method for processing its interplayer film | |
JPH01209727A (en) | Manufacture of semiconductor device | |
JPH0254659B2 (en) | ||
JPS6347947A (en) | Manufacture of semiconductor device | |
JPS59175124A (en) | Manufacture of semiconductor device | |
KR20040022080A (en) | Method for manufacturing metal insulator metal capacitor | |
JPH0621043A (en) | Manufacture of semiconductor device | |
JPH07211714A (en) | Manufacture of semiconductor device | |
JPH1174355A (en) | Manufacture of semiconductor device |