JPH01269336A - Start-stop synchronization system data transmission system - Google Patents

Abstract

PURPOSE:To prevent the propagation of out of synchronism, and to normally monitor the alarm information of a trouble detecting station so as to restore transmission trouble surely and quickly by start-stop-synchronization-controlling every frame by attaching a synchronizing pattern to a transmission line frame format. CONSTITUTION:The synchronizing pattern of the head part of reception data is detected by a receiving timing circuit 6 by using the clock signal of integer times of transmission bit rate to be outputted from an oscillation circuit 5, and is frequency-divided down to the transmission bit rate so that sampling timing is settled nearly at the center of the first bit of a data part, and the reception data is inputted to a buffer memory circuit 7 according to this receiving timing clock signal. The data is transmitted from the buffer memory circuit 7 by a transmitting timing circuit 8 at its own original transmitting timing that a clock signal outputted from the oscillation circuit 5 is frequency-divided, and the frame is regenerated by adding the synchronizing pattern to output data by a frame regeneration circuit 9. Thus, the out of synchronism of a bit is not propagated to other station.

Description

[Detailed description of the invention] [Industrial application field] The present invention is utilized in a loop type data transmission system.

In particular, the present invention relates to an asynchronous data transmission method in which each data transmission device is independently synchronized.

[Already needed]

The present invention makes it possible to prevent the spread of bit synchronization by providing a clock generation source for each data transmission device inserted into the transmission path in a system in which data is transmitted on a loop-shaped transmission path with start-stop synchronization. This is how it was done.

[Conventional technology]

Conventionally, in this type of loop-type data transmission system, data transmission is performed by establishing bit synchronization, and each data transmission device has a memory capacity that is an integral multiple of the transmission frame format length, and has a memory capacity that is an integral multiple of the transmission frame format length, and has a memory capacity that is an integral multiple of the transmission frame format length. It had a built-in buffer memory circuit and a transmission frame regeneration circuit that were independent from each other, and established frame synchronization independence.

[Problem that the invention seeks to solve]

However, in this conventional method, bit synchronization is established by the data transmission device of the master station having a masked clock distributing clock signals to the data transmission devices of other slave stations, so bit synchronization may occur. There is a drawback that when this occurs in one station, the bit synchronization will spread to all data transmission devices serving as lower stations. Furthermore, when the data transmission device of the master station monitors alarm information from the data transmission device of the slave station, there is a drawback that if bit synchronization occurs, the alarm information cannot be properly monitored.

The present invention aims to eliminate such drawbacks, and aims to provide an asynchronous data transmission system in which bit synchronization does not affect other stations.

[Failure to solve the problem]

The present invention provides a loop-type transmission path through which a signal string including a data portion and a synchronization pattern added to the beginning of the data portion is transmitted at a predetermined bit rate, and a loop-type transmission path through which a signal string including a data portion and a synchronization pattern added to the beginning of the data portion is inserted into the loop-type transmission path. A buffer circuit having an area for storing a plurality of data parts, a clock signal that extracts the data part from an incoming signal sequence and stores it in this buffer circuit,
a first circuit that divides and generates a clock signal from a given clock signal, a second circuit that divides and generates a clock signal from a given clock signal for reading out contents stored in the buffer circuit, and the buffer. In an asynchronous data transmission method, each of the data transmission devices includes a plurality of data transmission devices each including a frame regeneration circuit that adds a synchronization pattern to the beginning of a data portion read from a circuit. The present invention is characterized in that it includes an oscillation circuit that provides the first and second circuits with a clock signal having a bit rate that is an integral multiple of the bit rate.

[Effect]

The oscillation circuit outputs a clock signal that is an integral multiple of the bit rate of the data transmission path. The synchronization pattern of the transmission frame is detected using a clock signal obtained by dividing the clock signal of this oscillation circuit, and the timing of the clock signal is corrected so that the sampling timing is determined approximately at the center of the first bit of the data section. manually into the buffer memory circuit. A clock signal is generated by simply frequency-dividing the output tarock signal to the bit rate of the transmission line, and the clock signal of the oscillation circuit is frequency-divided, and the data portion is read using this clock signal. A synchronization pattern is added to the beginning of this read data section. Terminal data is transmitted and received in a predetermined time slot of the data section to which this synchronization pattern is added.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a block configuration diagram showing the configuration of this embodiment.

In this embodiment, as shown in FIG. 1, a loop-type transmission line 5 is used, through which a signal string including a data section and a synchronization pattern added to the beginning of this data section is transmitted at a predetermined bit rate.
0, a buffer memory circuit 7, which is a buffer circuit inserted into the loop-type transmission line 50 and having an area for storing a plurality of data parts of the signal string, extracts the data part from the incoming signal string and stores it in this buffer. A reception timing circuit 6 which is a first circuit that divides and generates a clock signal that defines the timing of storing in the circuit from a given clock signal, and a clock that defines the timing of reading out the contents stored in the buffer circuit. a transmission timing circuit 8 which is a second circuit that divides and generates a signal from a given clock signal; a frame regeneration circuit 9 that adds a synchronization pattern to the beginning of the data portion read from the buffer circuit; and the predetermined frame regeneration circuit 9. data transmission devices 1.2.3 and 4 including an oscillation circuit 5 that provides a clock signal with a bit rate that is an integral multiple of the bit rate of .

Next, the operation of this embodiment will be explained. Using a clock signal that is an integral multiple of the transmission bit rate output from the oscillation circuit 5, the reception timing circuit 6 detects the synchronization pattern at the beginning of the received data, and generates a timing signal approximately at the center of the first bit of the data section. The reception timing clock signal is output by dividing the frequency to the transmission bit rate so that the
The received data is manually input to the buffer memory circuit 7 according to this reception timing clock signal. The buffer memory circuit 7 has a memory capacity capable of storing an integer number of data parts in the received data, and the transmission timing circuit 8 transfers the data from the buffer memory circuit 7 at a unique transmission timing obtained by dividing the clock signal output from the oscillation circuit 5. The frame regeneration circuit 9 adds a synchronization pattern (1) to the output data to form a frame.The branch/add circuit 10 branches the terminal data at a predetermined time slot in the output data in synchronization with the transmission timing. and sends the output data to the data transmission device of the next station.

FIG. 2 is a format diagram of a transmission path frame that circulates around the loop-type transmission path 50'2 to ZeikLink via the data transmission device shown in FIG. This transmission line frame includes a data portion of a plurality of words in which a synchronization pattern consisting of a fixed pattern of all 1's or all 0's and an inverted bit for inverting the value at the end of the fixed pattern is attached at the beginning. However, the length of the data portion is within a permissible range determined by the frequency stability of the oscillation circuit 5 and the memory capacity of the buffer memory circuit 7. Further, the length of the synchronization pattern is longer than one word length, and has a margin for absorbing fluctuations due to frequency differences between data transmission devices.

FIG. 3 is a system configuration diagram that does not show the connection between the loop-type transmission line shown in FIG. 1 and an external synchronous data line. show. The synchronous data line termination device 13 is slave-synchronized with the master clock of the synchronous data line 14, and the data transmission device 1 is also slave-synchronized with this mask clock to transfer data between it and the synchronous data line termination device 13. . The data transmission device 1 is connected to a synchronous data line termination device 13 via a line interface circuit 11, controls a timing extraction and comparison circuit 12, synchronizes the oscillation circuit 5, and performs data transmission. Therefore, the other data transmission devices operate in independent synchronization, and the data transmission device 1 to which the synchronous data line termination device 13 is connected becomes dependent synchronization.

〔Effect of the invention〕

As explained above, the present invention makes bit synchronization independent by attaching a synchronization pattern to the transmission line frame format and performing start-stop synchronization control for each frame, and also has a memory capacity for multiple frames of the transmission line frame format. Since the frame synchronization of received data and the frame t, synchronization of transmitted data are made independent by a buffer memory circuit with
This has the effect of preventing the spread of out-of-synchronization, properly monitoring alarm information in the fault detection layer, and reliably and quickly recovering from transmission faults. Furthermore, since the synchronization of each data transmission device is independent, it is possible to connect any data transmission device to a synchronous data line termination device such as an exchange or multiplexing device having different mask clotters.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a format diagram of a transmission path frame used in an embodiment of the present invention. FIG. 3 is a block diagram showing the connection between the loop type transmission line of FIG. 1 and an external synchronous data line. 1-4...Data transmission device, 5...Oscillation circuit, 6...
Reception timing circuit, 7... Buffer memory circuit, 9... Transmission timing circuit, 9... Frame regeneration circuit, 1
0...branch/insertion circuit, 11. line interface circuit, 12.. timing extraction comparison circuit, 13.. synchronous data line termination device, 14. synchronous data line, 50.
・Loop type transmission line. Patent Applicant: 1 Hon Denki Co., Ltd., Agent: Nao Ide, Patent Attorney: Diagram 2 of the configuration of the first transmission line

Claims (1)

[Claims] 1. A loop-shaped transmission path through which a signal string including a data portion and a synchronization pattern added to the beginning of the data portion is transmitted at a predetermined bit rate; A buffer circuit having an area for storing a plurality of data portions of the signal string; a clock signal for extracting the data portion from the incoming signal string and storing it in the buffer circuit; generated by dividing the frequency of the given clock signal; a first circuit that divides and generates a clock signal for reading out the contents stored in the buffer circuit from the given clock signal; and a second circuit that generates a clock signal that reads out the content stored in the buffer circuit; In an asynchronous data transmission system comprising a plurality of data transmission devices including a frame regeneration circuit that adds a pattern, each of the data transmission devices receives a clock signal having a bit rate that is an integral multiple of the predetermined bit rate. An asynchronous data transmission system characterized by comprising an oscillation circuit that provides the first and second circuits with: