JPH0126191B2 - - Google Patents
Info
- Publication number
- JPH0126191B2 JPH0126191B2 JP54022708A JP2270879A JPH0126191B2 JP H0126191 B2 JPH0126191 B2 JP H0126191B2 JP 54022708 A JP54022708 A JP 54022708A JP 2270879 A JP2270879 A JP 2270879A JP H0126191 B2 JPH0126191 B2 JP H0126191B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- junction
- current
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/50—Physical imperfections
- H10D62/53—Physical imperfections the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D18/00—Thyristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D18/00—Thyristors
- H10D18/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に係り、特に
ゲートカソード短絡抵抗を持たないP1N1P2N2
4層よりなるサイリスタのゲート感度を調整する
ための製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, particularly a P 1 N 1 P 2 N 2 device having no gate-cathode short circuit resistance.
The present invention relates to a manufacturing method for adjusting the gate sensitivity of a four-layer thyristor.
この種のサイリスタの動作原理は、一般に知ら
れている様にP1N1P2トランジスタとN1P2N2トラ
ンジスタの組み合わせにより説明される。すなわ
ち、P1N1P2トランジスタの電流利得をα1,
N1P2N2トランジスタの電流利得をα2とすると、
サイリスタP1N1P2はα1+α21を満足する様な
電流が内部に流れる場合に導通状態となる。これ
を得るためには外部よりN1P2N2トランジスタの
ベース領域P2にゲート電流を流して電流依存性
のあるα1,α2が大きな値となるまで導き、α1+α2
1となるようにすれば良い。 The operating principle of this type of thyristor is explained by the combination of P 1 N 1 P 2 and N 1 P 2 N 2 transistors, as is generally known. That is, the current gain of the P 1 N 1 P 2 transistor is α 1 ,
If the current gain of N 1 P 2 N 2 transistor is α 2 , then
The thyristor P 1 N 1 P 2 becomes conductive when a current that satisfies α 1 +α 2 1 flows inside. To obtain this, a gate current is applied from the outside to the base region P 2 of the N 1 P 2 N 2 transistor until α 1 and α 2 , which are dependent on the current, become large values, and α 1 + α 2
It should be set to 1.
ゲートP2に電流を流して素子を導通状態に導
くのに必要な最小のゲート電流IGTは、その素子
を利用する回路構成等の理由からある電流範囲の
値のものが要求される場合がある。この様な場
合、200μA以上のゲート電流IGTは、製造工程中
の選択拡散工程において短絡抵抗をエミツタとベ
ースの間につけることにより比較的容易に得るこ
とができる。しかしながら200μA以下の小さなゲ
ート電流IGTに対しては拡散にてシヨート抵抗を
設けることは非常にむずかしい。すなわち、一般
にエミツタN2とベースP2の間に短絡抵抗を設け
る場合にはエミツタN2中に選択的にエミツタ拡
散が行われない様にするためシリコン酸化膜の残
る領域を設け、エミツタとなるN2層を拡散して
シヨート抵抗とするのであるが、このシヨート抵
抗をフオトレジスト及び拡散の精度により300K
Ωより大きな抵抗値を再現性よく設けることはむ
ずかしいものである。又、エミツタN2とベース
間をシリコン酸化膜で表面保護を行う場合、シヨ
ート抵抗のない構造の素子においてはゲート電流
IGTは一般的に非常に小さく、この値を再現性よ
く大きくすることは困難であつた。 The minimum gate current I GT necessary to cause current to flow through the gate P2 and bring the device into a conductive state may be required to have a value within a certain current range due to the circuit configuration that uses the device. be. In such a case, a gate current I GT of 200 μA or more can be obtained relatively easily by adding a short-circuit resistor between the emitter and the base in the selective diffusion step during the manufacturing process. However, for a small gate current I GT of less than 200 μA, it is extremely difficult to provide a shot resistance by diffusion. That is, in general, when a short-circuit resistor is provided between emitter N 2 and base P 2 , a region where the silicon oxide film remains is provided to prevent selective emitter diffusion into emitter N 2 , which becomes an emitter. The shot resistance is made by diffusing the N2 layer, and the shot resistance can be reduced to 300K by using the photoresist and the precision of the diffusion.
It is difficult to provide a resistance value larger than Ω with good reproducibility. In addition, when surface protection is performed between the emitter N2 and the base with a silicon oxide film, the gate current is
I GT is generally very small, and it has been difficult to increase this value with good reproducibility.
本発明は、かかる困難を解決し拡散工程終了後
に要求されるゲート感度IGTをシヨート・パター
ン構造をとることなしに容易に調整できる半導体
装置の製造方法を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve these difficulties and easily adjust the gate sensitivity I GT required after the completion of the diffusion process without using a short pattern structure.
この為本発明は、半導体ウエハ製造工程中に電
極金属を設けて、例えばP1N1P2N2 4層のサイ
リスタのα2を下げるためにシリコン酸化膜等の絶
縁物で保護されたエミツタN2、ベースP2のP2N2
接合の上よりエネルギ密度を集中的に上げること
のできるレーザービームを当てることによりシリ
コン及びシリコン酸化膜間に熱的歪を加えてゲー
ト・トリガ電流をコントロールすることを特徴と
している。 For this reason, the present invention provides an electrode metal during the semiconductor wafer manufacturing process to reduce the α 2 of a P 1 N 1 P 2 N 2 four-layer thyristor, for example, by forming an emitter protected with an insulating material such as a silicon oxide film. N 2 , base P 2 P 2 N 2
It is characterized by controlling the gate trigger current by applying thermal strain between the silicon and silicon oxide films by applying a laser beam that can concentrate the energy density above the junction.
次に本発明の実施例について第1図を用いて説
明する。 Next, an embodiment of the present invention will be described with reference to FIG.
比抵抗30〜40Ω・cm、厚さ240μのN型のシリ
コン基板に、ガリウムを両側より6×1018アト
ム/c.c.の濃度接合深さ50μとなる様に拡散し、P1
層3―N1層1―P2層2の三層を設ける。この後、
酸化雰囲気中でシリコン基板を酸化し両側にシリ
コン酸化膜5を設け、これを従来の光学的手法を
用いエミツタN2層4となるべき部分のシリコン
酸化膜をとり除き、この部分からリンを1×1021
アトム/c.c.の濃度及び20μの深さに拡散する。こ
の様な半導体ウエハに溝10を堀りP1N1及び
N1P2接合を露出せしめ、この部分にガラス6を
つける。この様にして出来た半導体ウエハの上主
面の、エミツタ4及びゲート2の部分にアルミニ
ウム(Al)を蒸着し一方主面にはNi―Agを蒸着
する。さらにこの様にしてできた半導体ウエハの
エミツタ4とゲート2層とのP2N2接合に、主表
面からレーザ光線を0.5w〜1w程度の強度で当て
る。この様にして得られた半導体素子は、光を当
てなかつた場合と比べてゲート電流IGTの値が10
倍程度すなわち20〜50μAに増加した。 Gallium was diffused from both sides into an N-type silicon substrate with a specific resistance of 30 to 40 Ω·cm and a thickness of 240 μ to a concentration of 6×10 18 atoms/cc to a junction depth of 50 μ.
Three layers are provided: Layer 3-N 1 Layer 1-P 2 Layer 2. After this,
The silicon substrate is oxidized in an oxidizing atmosphere to form a silicon oxide film 5 on both sides, and then the silicon oxide film in the part that should become the emitter N2 layer 4 is removed using a conventional optical method, and phosphorus is removed from this part. ×10 21
Diffuse to a concentration of atoms/cc and a depth of 20μ. Grooves 10 are dug in such a semiconductor wafer and P 1 N 1 and
Expose the N 1 P 2 junction and attach glass 6 to this part. Aluminum (Al) is vapor-deposited on the emitter 4 and gate 2 portions of the upper main surface of the semiconductor wafer thus produced, while Ni--Ag is vapor-deposited on the main surface. Further, the P 2 N 2 junction between the emitter 4 and the gate 2 layer of the semiconductor wafer thus formed is irradiated with a laser beam from the main surface at an intensity of about 0.5 W to 1 W. The semiconductor device obtained in this way has a gate current I GT value of 10% compared to the case without irradiation with light.
It increased to about 2 times, that is, 20 to 50 μA.
すなわち、酸化膜の下のP2N2接合にレーザ・
ビームを当てることによりシリコンの温度が上昇
し、シリコン酸化膜との間の極部的な熱的な歪が
発生する。この熱的な歪がP2N2接合の少数キヤ
リアの寿命を短くするためにN1P2N2トランジス
タの低電流領域でのα2が低下するため、外部より
大きな電流を流さねばα1+α21とならないので
結局ゲート電流IGTが大きくなるのである。この
様に外部に電極を設けた後レーザ・ビームを当て
ることにより不可逆的な歪が残り、又ゲート電流
IGTの値はビームを当てる面積、ビームの強さ等
を変えることによりIGTをかなりの範囲に変える
こともできるのである。 In other words, a laser beam is applied to the P 2 N 2 junction under the oxide film.
By applying the beam, the temperature of the silicon increases, causing local thermal strain between the silicon and the silicon oxide film. This thermal strain shortens the life of minority carriers in the P 2 N 2 junction, reducing α 2 in the low current region of the N 1 P 2 N 2 transistor, so a larger current must be passed from the outside to reduce α 1 Since +α 2 does not become 1, the gate current I GT ends up increasing. In this way, by applying a laser beam after providing an external electrode, irreversible distortion remains, and the gate current
The value of I GT can be varied over a considerable range by changing the area to which the beam is applied, the strength of the beam, etc.
第1図は本発明の製造方法の実施例に基いて製
造したサイリスタを説明する断面図である。
なお、図において、1……シリコン基板、2…
…ゲート層、3……カソード層、4……エミツタ
層、5……シリコン酸化膜、6……ガラス、7…
…Alゲート電極、8……Alカソード電極、9…
…Ni―Agカソード電極、10……メサ溝、11
……レーザー光線、12……熱歪層を各々示す。
FIG. 1 is a sectional view illustrating a thyristor manufactured according to an embodiment of the manufacturing method of the present invention. In the figure, 1... silicon substrate, 2...
...Gate layer, 3...Cathode layer, 4...Emitter layer, 5...Silicon oxide film, 6...Glass, 7...
...Al gate electrode, 8...Al cathode electrode, 9...
...Ni-Ag cathode electrode, 10...Mesa groove, 11
. . . laser beam, 12 . . . thermally strained layer, respectively.
Claims (1)
の半導体層と、該第1の半導体層の側面および底
面に接して形成され、前記第1の半導体層の主表
面と同一平面を形成する主表面を有する逆導電型
の第2の半導体層と、該第2の半導体層に接続さ
れた制御電極と、前記第2の半導体層の底面に接
して形成された前記一導電型の第3の半導体層
と、該第3の半導体層の底面に接して、形成され
た前記逆導電型の第4の半導体層と、該第4の半
導体層の底面に形成された他の主電極と、前記第
1及び第2の半導体層の前記主表面でこれら第1
及び第2の半導体層の接合部近傍に被覆された絶
縁膜とを備えた半導体装置の製造方法において、
前記第1及び第2の半導体層の接合部にレーザー
ビームを照射して前記第1及び第2の半導体層の
接合部と前記絶縁膜との間に熱歪を与えることに
よつてゲート電流を制御することを特徴とする半
導体装置の製造方法。1 A first electrode of one conductivity type with a main electrode connected to the main surface.
a second semiconductor layer of an opposite conductivity type, which is formed in contact with the side and bottom surfaces of the first semiconductor layer and has a main surface coplanar with the main surface of the first semiconductor layer; , a control electrode connected to the second semiconductor layer, a third semiconductor layer of one conductivity type formed in contact with the bottom surface of the second semiconductor layer, and a control electrode connected to the bottom surface of the third semiconductor layer. The fourth semiconductor layer of the opposite conductivity type formed in contact with the other main electrode formed on the bottom surface of the fourth semiconductor layer, and the main surfaces of the first and second semiconductor layers. These first
and an insulating film coated near the junction of the second semiconductor layer,
A gate current is generated by applying a thermal strain between the junction between the first and second semiconductor layers and the insulating film by irradiating the junction between the first and second semiconductor layers with a laser beam. A method of manufacturing a semiconductor device characterized by controlling the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2270879A JPS55115364A (en) | 1979-02-28 | 1979-02-28 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2270879A JPS55115364A (en) | 1979-02-28 | 1979-02-28 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55115364A JPS55115364A (en) | 1980-09-05 |
JPH0126191B2 true JPH0126191B2 (en) | 1989-05-22 |
Family
ID=12090335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2270879A Granted JPS55115364A (en) | 1979-02-28 | 1979-02-28 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55115364A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IE54111B1 (en) * | 1982-03-11 | 1989-06-21 | Westinghouse Electric Corp | Laser treatment of thyristor to provide overvoltage self-protection |
US4555845A (en) * | 1982-10-13 | 1985-12-03 | Westinghouse Electric Corp. | Temperature stable self-protected thyristor and method of producing |
US5344794A (en) * | 1993-03-31 | 1994-09-06 | Siemens Components, Inc. | Method of making a semiconductor chip |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49121490A (en) * | 1973-03-05 | 1974-11-20 | ||
JPS5348457A (en) * | 1976-10-15 | 1978-05-01 | Hitachi Ltd | Production of semiconductor element |
-
1979
- 1979-02-28 JP JP2270879A patent/JPS55115364A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49121490A (en) * | 1973-03-05 | 1974-11-20 | ||
JPS5348457A (en) * | 1976-10-15 | 1978-05-01 | Hitachi Ltd | Production of semiconductor element |
Also Published As
Publication number | Publication date |
---|---|
JPS55115364A (en) | 1980-09-05 |
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