JPH01244565A - Extended memory transfer/control system - Google Patents

Abstract

PURPOSE:To access a data transfer locking flag regardless of the used condition of a main memory, and to shorten an access time by placing the data transfer locking flag of a competitive control at the time of a data transfer in a system control device. CONSTITUTION:In a system control device 1 which can be accessed by means of a central processor 6 and high-speed arithmetic processors 2-4, before the processor 6 or the high-speed arithmetic processors 2-4 send a data transfer request to a extended memory data transfer control means 12, when the other processor is under the data transfer, the sending of the data transfer request is held until the completion of the transfer. When the data is not under the transfer, the self-processor is under the data transfer, a communication locking means 13 to send the data transfer request is possessed. Thus, the data transfer locking flag can be accessed regardless of the used condition of the main memory, and the access time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an extended storage transfer method for transferring data between a main storage device and an extended storage device, and particularly to a communication locking method between multiple processors.

[Conventional technology]

Supercomputers that carry out large-scale scientific and technical calculations are capable of handling problems of almost unprecedented scale.

It is difficult to store all of the necessary data in the main memory, so an expanded storage transfer method is used that includes a main storage and a large-capacity expanded storage that is capable of high-speed transfer.

In addition, in order to execute calculations at high speed, a number of processing units are connected and jobs are executed simultaneously to improve performance.

Conventionally, in an information processing device having this type of extended storage device, d,
[Problems to be Solved by the Invention] However, the above-mentioned conventional locking means exists in the main storage device-F for controlling conflicts between data transfer requests from a plurality of data transfer requests. In the extended storage transfer control system in a supercomputer to which an extended storage device is connected, the communication lock that controls extended storage data transfer requests from multiple brokers is located on the main storage device, so the high-speed processing unit When a vector instruction is written to the main storage device y■1, the vector data row 1 or store is executed and the main memory is occupied exclusively, or when two output processing units are magnetically stored. During data transmission between disk device l and main storage device 1. The high-speed arithmetic processing unit or central processing unit does not want to transfer data between the main storage device and the expansion storage device, so it does not resist the communication lock on the device and the transfer is photon and the communication lock occurs. to l4.

4, when the main memory is deprived, the execution of the instruction is forced to wait, resulting in a drop in performance.

Therefore, 2 technical problems of the present invention are, in view of the drawbacks mentioned in 1-1, to provide an extended storage transfer control that allows access to the data transfer log regardless of the state of use of the main storage device and shortens the access time; The purpose is to provide a method.

[Means to solve the problem]

According to the present invention, an extended storage transfer control having a system control device, a central processing unit, a high-speed arithmetic processing unit, a first main storage device, a second upper storage device, and an expanded storage device According to the method, when there is a data transfer request from the central processing unit, data transfer between the first main storage device and the expansion memory 1, (5) device is performed by γ-J; If there is a data transfer request from the high-speed processing unit,
Expansion description 1: data transfer system means for transferring data between the second main storage device and the expansion storage device;
In the system control device that is accessible from the central processing unit and the high-speed arithmetic processing unit, the central processing unit or the high-speed arithmetic processing unit makes a data transfer request to the extended storage data transfer control means. before sending out the
If another processing device is in the process of transferring data, the sending of the transfer request is suspended until the transfer is completed, and if the other processing device is not in the process of data transfer, it is assumed that the own processing device is in the process of data transfer. 14t is an extended storage transfer control system characterized by having a communication lock means for sending out a data transfer request.

〔Example〕

Next, one embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, an information processing device that adopts the extended storage transfer control method according to an embodiment of the present invention includes a system control device 61 and an input/output processing device 5 connected thereto, which controls the entire system. a central processing unit 6 that performs vector division; a plurality of high-speed arithmetic processing units 2 to 4 that mainly perform vector division;
A control main memory device 9 in which the operating system functions operate in the main memory for the central processing unit 6, and a high-speed calculation unit that stores vector data for vector calculations and user programs executed by the high-speed arithmetic processing units 2 to 4. an ultra-high-speed, thick-numbered main storage device 7 for processing units 2 to 4;
Expanded storage device 8, central processing unit 6 and input/output processing unit 5
and control main memory 9. A control data transfer control circuit 11 that controls data transfer with the main storage device 7 for calculations, a plurality of high-speed calculation processing devices 2 to 4, and the main storage device 7 for calculations. A calculation data transfer control circuit 10 that controls data transfer with the control main storage device 9, an extended storage device 8, and the calculation main storage device 7. An expanded storage data transfer control circuit 12 that controls data transfer with the control main storage device 9 and a high-speed arithmetic processing device 2
4 and a communication lock circuit 13 that receives and receives lock commands and unlock commands from the central processing unit 6.

The second one is the communication lock circuit 13 as shown in .

It I When transfer is locked when 11 LL Q It
A transfer lock flag 21 indicates that the transfer is not yet being performed, and a lock r4J determines whether the lock is successful or unsuccessful based on the transfer lock flag 21 when a lock command 200 from the high-speed arithmetic processing units 2 to 4 or the central processing unit is received. constant circuit 20 and 2
The deadlock detection circuit 22 includes a count register 23 of m pino I. Note that 201 is a clear signal that sets the transfer lock flag to 1101+.

Next, the operation of this embodiment will be explained using the extended storage data transfer time chart shown in FIG.

When the high-speed arithmetic processing units 2 to 4 attempt to transfer data between the main storage device for calculations 7 and the extended storage device 8, or when the central processing unit 6 attempts to transfer data between the main storage device for control 9 and the extended storage device 8, The processing devices 2 to 4.6 send a lock command 101 to the communication lock circuit 13.

When the lock determination circuit 20 of the communication lock circuit 13 receives the lock command 101, if the transfer lock flag 21 is 0'', it sets the transfer lock flag 21 to "i" and sets the deadlock detection circuit 22 to The selector 2/I selects the input signal 207 of all pinots ``1'' by the ``select signal 205'' from the lock determination circuit 20,
Set the count register 23 to all pinot I-"l". When the transfer lock flag 21 is "]", the transfer lock flag 21 is held as 1'', and the selector 24 uses the select signal 205 to subtract the value of the count register 23 by 1 using the subtracter 25 to obtain data 210. By selecting , the value of the count register 23 is decreased by 1.

Then, the value of the transfer lock flag 21 is sent as a lock determination signal 204 together with the reply 102 to the processing device that issued the instruction.

At this time, the calculation main memory 7 is connected to the other calculation processing devices 2 to 4.
, or when the control main storage device 9 is in the middle of data transfer with a magnetic disk device (not shown) connected to the input/output processing device 5. However, the first communication lock circuit 13 can receive and receive the lock command 101.

The high-speed arithmetic processing units 2 to 4 or the central processing unit 6 are.

Upon receiving the reply 102 from the communication lock circuit 13,
When the lock judgment signal 204 is Ll I II, it is assumed that the lock is unsuccessful and the lock command 101 is sent again to the 2 communication lock circuit 13. When the lock judgment signal 204 is 0'', it is assumed that the lock is successful and the extended storage data is transferred. A data transfer command 103 is sent to the control circuit 12 with transfer information such as a transfer start address and a transfer block length.

The extended storage data transfer control circuit 12 receives the data transfer command 10.
3, the transfer information attached to the data transfer command 103 causes the expansion storage device 8 and the main storage device 7 or
Executes high-speed data transfer with the control main storage device 9. Thereafter, when all the specified data has been transferred, the processing device that issued the instruction returns a data transfer completion report 104.

The high-speed arithmetic processing units 2 to 4 or the central processing unit 6 receive a data transfer completion report 10 from the extended storage data transfer control circuit 12.
4, it sends a lock release command 105 to the 2 communication lock circuit 13. When the communication lock circuit 13 accepts the lock release command 105, the communication lock circuit 13 sets the transfer lock flag 21 to I.
IOI) and returns the lock release completion report 106 to the processing device that issued the command.

At this time, as with the lock instruction, if the main storage device 7 for calculation is exclusively used for loading/storing vector data of other high-speed processing devices 2 to 4, or the main storage device 9 for control 1 even when data is being transferred to a magnetic disk device (not shown) connected to the input/output processing device 5.
The communication lock circuit 13 can receive and receive the unlock command 105.

In addition, if the processing units 2 to 4 that have been locked are disconnected from the system due to a failure and remain locked, other processing units may issue a lock command to the system in order to transfer data. return.

At the 2rn-1st lock instruction, the count register 21 in the deadlock detection circuit 22 becomes '1'.

The output 210 of the subtracter 25 becomes “Ou” and the zero detection circuit 2
When the output 211 of 6 becomes 1" and the lock failure signal 203 from the lock judgment circuit 20 becomes 1", the 5 interrupt circuit 2
7 is a deadlock interrupt signal 212 to the instruction source processing device.
Send out.

The processing unit accepts deadlock interrupts.

After sending out a lock release command and forcibly setting the transfer lock flag 21 to "o", a lock command is executed.

〔Effect of the invention〕

As explained above, the present invention provides a system controller with a data transfer lock flag for contention control when multiple processors transfer data between the main storage device and the expanded storage device. .

The data transfer lock flag can be easily accessed regardless of the usage status of the main storage device, and the access time can be shortened compared to the conventional case where the data transfer lock flag is placed on the main storage device. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of the communication lock circuit 13 of FIG. 1. FIG. 3 is a time chart of extended storage data transfer. ■・System control device, 2 to 4 ・High-speed arithmetic processing device,
5... Input/output processing unit, 6 - Central processing unit. 7... Main memory for calculation, 8 Expansion storage, 9...
Main memory for control, 10... data transfer control circuit for calculation, 11... data transfer control circuit for use j, 12...
Extended storage data transfer control circuit, 13. Communication lock circuit, 20. Lock determination circuit, 21. Transfer lock flag, 22. Deadlock detection circuit.

Claims (1)

[Claims] 1. A system control device, a central processing unit, a high-speed arithmetic processing unit, a first main storage device, a second main storage device,
In the extended storage transfer control method having an extended storage device, when there is a data transfer request from the central processing unit, data is transferred between the first main storage device and the expanded storage device, and the high-speed When there is a data transfer request from an arithmetic processing unit, an extended storage data transfer control means for transferring data between the second main storage device and the extended storage device; In the system control device that can be accessed from the computer, before the central processing unit or the high-speed arithmetic processing unit sends a data transfer request to the expanded storage data transfer control means, another processing unit is transferring data. In this case, the device has a communication locking means that suspends the sending of the data transfer request until the transfer is completed, and when the data is not being transferred, the self-processing device sends the data transfer request as if the data is being transferred. Features an extended storage transfer control method.