JPH01233744A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH01233744A JPH01233744A JP63061626A JP6162688A JPH01233744A JP H01233744 A JPH01233744 A JP H01233744A JP 63061626 A JP63061626 A JP 63061626A JP 6162688 A JP6162688 A JP 6162688A JP H01233744 A JPH01233744 A JP H01233744A
- Authority
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- Prior art keywords
- wiring
- signal wiring
- constant potential
- signal
- substrate
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/1616—Cavity shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体チップを封止するパッケージを備えた
高速半導体装置に関し、特に、マイクロ波帯域（数ＧＨ
ｚ〜数十〇１ｌｚ）の高周波信号を伝送する半導体チッ
プを封止するパッケージに適用して有効な技術に関する
ものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a high-speed semiconductor device equipped with a package for sealing a semiconductor chip, and particularly in the microwave band (several GHz).
The present invention relates to a technique that is effective when applied to a package for sealing a semiconductor chip that transmits a high-frequency signal of 100 Hz to several tens of lz.
半導体チップは、パッケージのキャビデイの中に搭載さ
れ、ボンディングワイヤを介してパッケージの基板（ベ
ース）の中の信号配線に接続される。この信号配線は、
パッケージの中を前記半導体チップの主面と平行な方向
に延在して、アウタリードに接続される。従来の半導体
装置は、パッケージの中の半導体チップがマイクロ波帯
域で動作をする場合には、前記信号配線をマイクロスト
リップライン又はストリップラインに構成していた（日
経マグロウヒル社発行、日経マイクロデバイス、１９８
５年１１月号、ｐｐＨｌ〜１１７）。A semiconductor chip is mounted in a cavity of a package and connected to signal wiring in a substrate (base) of the package via bonding wires. This signal wiring is
It extends inside the package in a direction parallel to the main surface of the semiconductor chip and is connected to the outer leads. In conventional semiconductor devices, when the semiconductor chip in the package operates in the microwave band, the signal wiring is configured as a microstrip line or a strip line (published by Nikkei McGraw-Hill, Nikkei Micro Devices, 1988).
November 5th issue, ppHl~117).
また、前記半導体チップの搭載面は、半導体チップのポ
ンディングパッドと前記信号配線との高さをほぼ等しく
するため、信号配線が設けられている面より窪んだ構造
となっている。そして、半導体チップは、上からキャッ
プで蓋をされて封止されるが、このキャップは、前記信
号配線やボンディングワイヤ間のアイソレーション特性
を高めるために、金属で形成し、さらに接地される。Further, the mounting surface of the semiconductor chip has a structure recessed from the surface on which the signal wiring is provided so that the heights of the bonding pads of the semiconductor chip and the signal wiring are approximately equal. The semiconductor chip is then covered and sealed with a cap, which is made of metal and grounded in order to improve isolation characteristics between the signal wiring and bonding wires.
本発明者は、前記ストリップライン及びマイクロストリ
ップラインに構成された信号配線を検討した結果１次の
問題点を見出した。The inventor of the present invention discovered the first problem as a result of studying the signal wiring configured in the strip line and microstrip line.
まず、前記信号配線は、平板状をしており、しかも厚さ
が２０〜２５μｍ程度と非常に薄くなっている。このた
め、信号配線の幅を０．２ｍｍ程度に大きく取ってもそ
の断面積が小さいため、インダクタンス、配線抵抗、配
線容量が大きく、信号の伝搬速度の向上を図ることが難
しかった。これら信号配線のインダクタンス、配線抵抗
、配線容量の低減を図るためには、前記信号配線の配線
長を短くしなければならないが、前述のように、信号配
線がパッケージの中を半導体チップの主面と平行な方向
、すなわち横方向に延在しているため、配線長を短くす
ることが非常に難しかった。First, the signal wiring has a flat plate shape and is very thin, with a thickness of about 20 to 25 μm. For this reason, even if the width of the signal wiring is increased to about 0.2 mm, its cross-sectional area is small, resulting in large inductance, wiring resistance, and wiring capacitance, making it difficult to improve the signal propagation speed. In order to reduce the inductance, wiring resistance, and wiring capacitance of these signal wirings, the wiring length of the signal wiring must be shortened. Because the wires extend in a direction parallel to the wires, that is, in the lateral direction, it is extremely difficult to shorten the wire length.
また、前述のように、パッケージの半導体チップが搭載
されている窪みの部分と、信号配線が設けられている面
との間の段差部には、ストリップライン又はマイクロス
トリップラインの接地堰体が設けられていないため、こ
こから高周波信号が漏洩し、信号配線間で相互作用（ク
ロストーク）を生じる。In addition, as mentioned above, a strip line or microstrip line grounding barrier is provided at the step between the recessed part of the package where the semiconductor chip is mounted and the surface where the signal wiring is provided. Because the wires are not connected to each other, high-frequency signals leak from there, causing interaction (crosstalk) between signal wires.
一方、前記キャップは平板で、その厚さが薄いため、キ
ャップ自身のインダクタンスや抵抗が大きく、６ＧＩＩ
ｚ〜１０ＧＨｚ付近になると自己共振を起して、半導体
装置の高周波伝送特性を劣化させていた。このキャップ
のインダクタンスや抵抗を低減するためには、キャップ
の厚さを厚くすればよいが、そうするとパッケージの高
さが高くなる、という問題が生じる。また、前記のよう
にキャップが平板状をしていると、ボンディングワイヤ
までの距離が大きいため、ボンディングワイヤから出る
電気力線をシールドするのが難しくなり、ボンディング
ワイヤ間のアイソレーションが不充分になる。On the other hand, since the cap is a flat plate and its thickness is thin, the inductance and resistance of the cap itself are large, and the 6GII
When the frequency ranges from z to 10 GHz, self-resonance occurs, degrading the high frequency transmission characteristics of the semiconductor device. In order to reduce the inductance and resistance of the cap, it is sufficient to increase the thickness of the cap, but this raises the problem of increasing the height of the package. Furthermore, if the cap is flat as described above, the distance to the bonding wire is large, making it difficult to shield the electric lines of force coming out from the bonding wire, resulting in insufficient isolation between the bonding wires. Become.
これらのことから、信号配線同志が干渉し合うという問
題があった。For these reasons, there was a problem that the signal wirings interfered with each other.
本発明の目的は、高速半導体装置において、信頼性の向
上をはかることができる技術を提供することにある。An object of the present invention is to provide a technique that can improve reliability in a high-speed semiconductor device.
本発明の他の目的は、数ＧＨｚ〜数十ＧＨｚの高周波信
号を伝送する際に、信号配線間の相互作用を防止するこ
とができる半導体装置を提供することにある。Another object of the present invention is to provide a semiconductor device that can prevent interaction between signal wiring lines when transmitting high frequency signals of several GHz to several tens of GHz.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体チップを封止したパッケージの基板の
中に信号配線を備えた半導体装置において、前記信号配
線の周囲に、前記信号配線と同軸方向で同軸ケーブル状
に複数本の定電位配線を設けたものである。That is, in a semiconductor device having a signal wiring in a substrate of a package in which a semiconductor chip is sealed, a plurality of constant potential wirings are provided around the signal wiring in the form of a coaxial cable in the same direction as the signal wiring. It is something.
上述した手段によれば、前記信号配線の周囲に設けられ
た定電位配線によって１信号配線同志の間が同軸ケーブ
ルと同程度にシールドされるので、アイソレーション特
性を向上することができる。According to the above-mentioned means, the constant potential wiring provided around the signal wiring shields the signal wiring to the same extent as a coaxial cable, so that the isolation characteristics can be improved.
また、前記信号配線と定電位配線の間隔を調整すること
により、信号配線のインピーダンスを所望の値（例えば
５０Ω）に設定することができる。Further, by adjusting the interval between the signal wiring and the constant potential wiring, the impedance of the signal wiring can be set to a desired value (for example, 50Ω).
以下１本発明の一実施例の半導体装置を図面を用いて説
明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.
第１図は１本発明の一実施例の半導体装置の断面図、
第２図は、第１図に示した半導体装置の■−■切断線部
分の平面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view of the semiconductor device shown in FIG.
第３図は、第２図に示した半導体装置の破線で囲んだ部
分■の拡大平面図である。FIG. 3 is an enlarged plan view of a portion (2) of the semiconductor device shown in FIG. 2 surrounded by a broken line.
まず、半導体装置全体の概略構成を説明する。First, the general configuration of the entire semiconductor device will be explained.
第１図乃至第３図において、１００はパッケージの基板
であり、例えばセラミック（ＡＱｚｏａ）からなってい
る。この基板１００のキャビティ （凹部）１０１の底
には、単結晶シリコンやＧ ａ Ａ ｓ、等からなる半
導体チップ１が金属膜２を介して搭載されている。半導
体チップｌは、ボンディングワイヤ３を介して基板１０
０の電極４に接続されている。In FIGS. 1 to 3, reference numeral 100 denotes a substrate of the package, which is made of ceramic (AQzoa), for example. A semiconductor chip 1 made of single crystal silicon, GaAs, or the like is mounted on the bottom of a cavity (recess) 101 of this substrate 100 with a metal film 2 interposed therebetween. The semiconductor chip l is connected to the substrate 10 via the bonding wire 3.
0 electrode 4.
” ５は半導体装置の信号配線であり、基板１００の
キャビティ１０１より外側の部分に複数設けられている
。そして、それぞれの信号配線５と信号配線５の間には
内部定電位配置ｌＡ６が設けられている。” 5 is a signal wiring of the semiconductor device, and a plurality of signal wirings are provided outside the cavity 101 of the substrate 100. An internal constant potential arrangement 1A6 is provided between each signal wiring 5. ing.
また、基板１００の外側の側面には外部定電位配線７が
設けられており、この外部定電位配線７と、内部定電位
配線６と、金属膜２とで信号配線５をシールドするよう
になっている。基板１００の上には金属からなるキャッ
プ８が、金属膜９を介して設けられており、このキャッ
プ８でボンディングワイヤ３や半導体チップ１を外部電
界からシールドしている。Further, an external constant potential wiring 7 is provided on the outer side surface of the substrate 100, and the signal wiring 5 is shielded by this external constant potential wiring 7, the internal constant potential wiring 6, and the metal film 2. ing. A cap 8 made of metal is provided on the substrate 100 with a metal film 9 in between, and the cap 8 shields the bonding wires 3 and the semiconductor chip 1 from external electric fields.
次に、半導体装置の各部の構成を詳細に説明する。Next, the configuration of each part of the semiconductor device will be explained in detail.
前記金属膜２は、キャビティ１０１の底面から壁
−面のほぼ全域に設けられ、特に、キャビティ１０
１の壁面では、電極４の近くまで設けることによって、
信号配線５から出る電気力線の漏洩をできるだけ少くし
ている６信号配ｍｓは、基板１００の中を高さ方向、す
なわち半導体チップ１の主面と垂直な方向に延在して設
けられており、その上端には電極４が接続されている。The metal film 2 extends from the bottom of the cavity 101 to the wall.
- Provided on almost the entire surface, especially in the cavity 10
1, by providing it close to the electrode 4,
The six signal lines ms, which minimize the leakage of electric lines of force coming out of the signal lines 5, are provided extending in the height direction of the substrate 100, that is, in the direction perpendicular to the main surface of the semiconductor chip 1. An electrode 4 is connected to its upper end.
この電極４は、キャビティ１０１の中の金属膜２からは
絶縁されている。This electrode 4 is insulated from the metal film 2 inside the cavity 101.
信号配線５の下端は、基板１００の底面に複数設けられ
ているアウターリード１０のうちの所定のアウターリー
ドｌＯに接続されている。なお、基板１００の中には電
源配線すなわち、電源電位Ｖｃｃを給電する配線や接地
電位Ｖｓｓを給電する配線が設けられるが、この電源配
線も信号配線５と同様に、基板１００の高さ方向に延在
して設けられている。The lower end of the signal wiring 5 is connected to a predetermined outer lead IO of a plurality of outer leads 10 provided on the bottom surface of the substrate 100. Note that power supply wiring, that is, a wiring for supplying power supply potential Vcc and a wiring for supplying ground potential Vss, are provided in the substrate 100. Similar to the signal wiring 5, this power supply wiring also extends in the height direction of the substrate 100. It is extended.
信号配線５の間の内部定電位配線６は、信号配線５と平
行に、また同一方向に延在して設けられている。それぞ
れの信号配線５と内部定電位配線６は、はぼ直線的に並
ぶように配列されている。なお、前記電源電位を給電す
る配線と信号配線５の間、電源電位を給電する配線と接
地電位を給電する配線の間、接地電位を給電する配線と
信号配線５の間にも内部定電位配線６を設けている。こ
れら信号配線５や内部定電位記ＩＩＡ６は、直径が例え
ば０．２ｍｍの円柱状導体からなっている。前記外部定
電位配線フは、板状に形成してあり、基板１００の側面
の信号配線５に対応した位置に設けられている。また、
外部定電位配線フは、信号配線５より長くされて、基板
１００の下面近くから上端近くまで設けられている。た
だし、外部定電位配線７は、信号配線５が接続されてい
るアウターリード１０からは絶ｉされている。この外部
定電位配線フと、内部定電位配線６と、金属１１ｇ２と
は、第３図に示したように信号配線５に対して同軸ケー
ブル状に配列されている。The internal constant potential wiring 6 between the signal wirings 5 is provided so as to extend in parallel with the signal wirings 5 and in the same direction. The respective signal wirings 5 and internal constant potential wirings 6 are arranged almost linearly. Note that internal constant potential wiring is also provided between the wiring that supplies the power supply potential and the signal wiring 5, between the wiring that supplies the power supply potential and the wiring that supplies the ground potential, and between the wiring that supplies the ground potential and the signal wiring 5. There are 6. The signal wiring 5 and the internal potentiometer IIA6 are made of cylindrical conductors having a diameter of, for example, 0.2 mm. The external constant potential wiring is formed into a plate shape and is provided at a position corresponding to the signal wiring 5 on the side surface of the substrate 100. Also,
The external constant potential wiring line is longer than the signal wiring line 5 and is provided from near the bottom surface of the substrate 100 to near the top end. However, the external constant potential wiring 7 is isolated from the outer lead 10 to which the signal wiring 5 is connected. The external constant potential wiring, the internal constant potential wiring 6, and the metal 11g2 are arranged in the form of a coaxial cable with respect to the signal wiring 5, as shown in FIG.
ここで、金属膜２と、内部定電位配線６．外部定電位配
線フと、アウターリード１０と、キャップ８とのそれぞ
れの接続関係を第４図に示す。Here, the metal film 2 and the internal constant potential wiring 6. FIG. 4 shows the connection relationship between the external constant potential wiring, the outer lead 10, and the cap 8.
第４図は、金属ｗＸ２と、内部定電位配線６．外部定電
位配線７と、アウターリード１０と、キャップ８とのそ
れぞれの接続関係を説明するための半導体装置の模式的
な断面図である。FIG. 4 shows metal wX2 and internal constant potential wiring 6. FIG. 3 is a schematic cross-sectional view of the semiconductor device for explaining the connection relationship between an external constant potential wiring 7, an outer lead 10, and a cap 8. FIG.
前記外部定電位配線７．内部定電位配線６．金属膜２の
それぞれの間は、基板１００内の接続配線１１によって
接続され、またそれぞれの内部定電位配線６の上端は、
基板１００の上面の金属膜９を介してキャップ８に接続
されている。また、例えば何本かの内部定電位配線６は
、アウターリード１０のうちの定電位例えば接地電位Ｖ
ｓｓを給電するためのアウターリード１０に接続されて
いる。また、内部定電位配線５のうちの所定のものは、
ボンディングワイヤ３を介して、半導体チップ１上の定
電位を給電するためのポンディングパッド、例えば接地
電位Ｖｓｓを給電するためのポンディングパッドに接続
されている。前記信号配線５から外部定電位配線７．内
部定電位配線６及び金属膜２までのそれぞれの距離を調
整することにより、信号配線５のインピーダンスを種々
な値に設定することができる。The external constant potential wiring 7. Internal constant potential wiring6. Each of the metal films 2 is connected by a connection wiring 11 in the substrate 100, and the upper end of each internal constant potential wiring 6 is
It is connected to the cap 8 via the metal film 9 on the upper surface of the substrate 100. Further, for example, some of the internal constant potential wirings 6 are connected to a constant potential of the outer lead 10, for example, the ground potential V.
It is connected to the outer lead 10 for supplying power to the ss. Further, a predetermined one of the internal constant potential wirings 5 is
It is connected via a bonding wire 3 to a bonding pad for supplying a constant potential on the semiconductor chip 1, for example, a bonding pad for supplying a ground potential Vss. From the signal wiring 5 to the external constant potential wiring 7. By adjusting the respective distances to the internal constant potential wiring 6 and the metal film 2, the impedance of the signal wiring 5 can be set to various values.
前記キャップ８は、その下面の中央部がキャビティ１０
１の方へ出るように・、周辺部より中央部を厚くしであ
る。キャップ８の周辺部の厚さは、例えば１５０μｍ程
度、中央部の厚さは５００μｍ程度である。The cap 8 has a cavity 10 at the center of its lower surface.
The center part is thicker than the peripheral part so that it extends toward the 1st part. The thickness of the peripheral portion of the cap 8 is, for example, approximately 150 μm, and the thickness of the central portion is approximately 500 μm.
前記金属膜２．外部定電位配線７及び基板１００の上面
の金属膜９は、タングステン（Ｗ）膜の上にニッケル（
Ｎｉ）メツキをし、さらに金（Ａｕ）メツキをしたもの
からなっている。基板１００と信号配線５．内部定電位
配線６及び接続配線１１は、グリーンシートを積層し、
これに熱処理をして形成したものである。電極４はタン
グステン（Ｗ）膜からなり、基板１００から露出してい
る部分にはニッケル（Ｎｉ）メツキ、さらにその上に金
（ＡＵ）メツキが施しである。アウターリード１００及
びキャップ８は、例えば４２７０イで構成されている。The metal film 2. The metal film 9 on the upper surface of the external constant potential wiring 7 and the substrate 100 is made of nickel (nickel) on a tungsten (W) film.
The material is plated with Ni) and further plated with gold (Au). Substrate 100 and signal wiring 5. The internal constant potential wiring 6 and the connection wiring 11 are made by laminating green sheets,
It is formed by heat-treating this. The electrode 4 is made of a tungsten (W) film, and the portion exposed from the substrate 100 is plated with nickel (Ni), and is further plated with gold (AU). The outer lead 100 and the cap 8 are made of, for example, 4270mm.
なお１本発明の半導体装置は、第５図及び第６図に示し
たように構成することもできる。Note that the semiconductor device of the present invention can also be configured as shown in FIGS. 5 and 6.
第５図は、第１図に示した本発明の一実施例の半導体装
置と異る半導体装置の構成を説明するための図。FIG. 5 is a diagram for explaining the configuration of a semiconductor device that is different from the semiconductor device according to the embodiment of the present invention shown in FIG.
第６図は、第５図に示した半導体装置の信号配線５が設
けられている部分の拡大平面図である。FIG. 6 is an enlarged plan view of a portion of the semiconductor device shown in FIG. 5 where signal wiring 5 is provided.
第５図及び第６図に示すように、内部定電位配線６及び
外部定電位記ＩＡ７の双方を基板１００の中に設け、こ
れら内部定電位配線６．外部定電位配線７．金属膜２を
それぞれ信号配線５の周囲に同軸ケーブル状に設けて、
信号配線５のシールドを行うこともできる。As shown in FIGS. 5 and 6, both the internal constant potential wiring 6 and the external constant potential IA7 are provided in the substrate 100, and these internal constant potential wiring 6. External constant potential wiring7. A metal film 2 is provided around each signal wiring 5 in the form of a coaxial cable,
The signal wiring 5 can also be shielded.
以上、説明した本実施例の半導体装置の構成から次の効
果を得ることができる。The following effects can be obtained from the configuration of the semiconductor device of this embodiment described above.
半導体チップ１を封止したパッケージの基板１００の中
に信号配、１ｌＸ５を備えた半導体装置において。In a semiconductor device including a signal wiring, 11×5, in a substrate 100 of a package in which a semiconductor chip 1 is sealed.
前記信号配線５の周囲に、前記信号配ｔｉＡ５と同軸方
向で同軸ケーブル状に複数本の定電位配線（内部定電位
配線６．外部定電位配線）及び金属膜２からなる）をそ
れぞれ設けたことにより、この定電位配線によって信号
配線５同志の間が同軸ケーブルと同程度にシールドされ
るので、信号配線５間のアイソレーション特性を向上す
ることができる。また、前記信号配線５と定電位配線（
内部定電位配線６．外部定電位配線）、金属膜２）の間
隔を調整することにより、信号配線５のインピーダンス
を所望の値（例えば５ｏΩ）にすることができる。A plurality of constant potential wirings (consisting of internal constant potential wiring 6, external constant potential wiring) and metal film 2) are provided around the signal wiring 5 in the form of coaxial cables in the same axial direction as the signal wiring tiA5. Therefore, the constant potential wiring shields the signal wirings 5 to the same extent as a coaxial cable, so that the isolation characteristics between the signal wirings 5 can be improved. In addition, the signal wiring 5 and the constant potential wiring (
Internal constant potential wiring6. By adjusting the interval between the external constant potential wiring (external constant potential wiring) and the metal film 2), the impedance of the signal wiring 5 can be set to a desired value (for example, 50Ω).
また、信号配線５のほとんどの部分が、金属膜２、内部
定電位配線６及び外部定電位配線７でシールドされてい
るので、信号配線５からの漏洩電気力線を非常に少くす
ることができる。Furthermore, since most of the signal wiring 5 is shielded by the metal film 2, the internal constant potential wiring 6, and the external constant potential wiring 7, leakage lines of electric force from the signal wiring 5 can be extremely reduced. .
また、信号配線５が基板１００の底面から上面に向けて
高さ方向に設けられていることにより、その長さを非常
に短くすることができるので、インダクタンスＬ、配線
抵抗Ｒ２配線容量Ｃのそれぞれを低減することができる
。Furthermore, since the signal wiring 5 is provided in the height direction from the bottom surface to the top surface of the substrate 100, its length can be made very short, so that each of the inductance L, wiring resistance R2, and wiring capacitance C can be reduced.
また、信号配線５が円柱導体からなることにより、同じ
配線幅のマイクロストリップラインに較べて断面積が大
きくなるので、単位長さ（例えば１ｍｍ）当りのインダ
クタンスＬを約１７３．配線抵抗Ｒを約１／８に低減で
きる。Furthermore, since the signal wiring 5 is made of a cylindrical conductor, its cross-sectional area is larger than that of a microstrip line with the same wiring width, so the inductance L per unit length (for example, 1 mm) is approximately 173. The wiring resistance R can be reduced to about ⅛.
また、キャップ８の中央部分を厚くしたことにより、そ
の中央部がボンディングワイヤ３に近くなり、ボンディ
ングワイヤ３から出る電気力線１２を遮蔽することがで
きるので、ボンディングワイヤ３同志の間のアイソレー
ション特性を向上することができる。In addition, by making the central part of the cap 8 thicker, the central part becomes closer to the bonding wire 3 and can shield the electric lines of force 12 coming out from the bonding wire 3, thereby reducing the isolation between the bonding wires 3. Characteristics can be improved.
次に、キャップ８の中央を厚くしたことによって、キャ
ップ８自身の共振周波数を高くできることを第７図及び
第８図を用いて説明する。Next, it will be explained with reference to FIGS. 7 and 8 that by thickening the center of the cap 8, the resonance frequency of the cap 8 itself can be increased.
第７図は、平板状をしたキャップ８に分布するインダク
タンスし及び抵抗Ｒの分布状態を説明するための図。FIG. 7 is a diagram for explaining the distribution state of inductance and resistance R distributed in the flat cap 8. FIG.
第８図は、中央部を周辺部より厚くしたキャップ８のイ
ンダクタンスＬ及び抵抗Ｒの分状態を説明するための図
である。FIG. 8 is a diagram for explaining the state of the inductance L and resistance R of the cap 8 whose central portion is thicker than its peripheral portion.
第７図に示すように、キャップ８が平板状をしていると
きの周辺部のインダクタンスＬ１及び抵抗Ｒ１、中央部
のインダクタンスＬ２及び抵抗Ｒ２、前記周辺部と反対
側の周辺部のインダクタンスＬ３及び抵抗Ｒ３の大きさ
は、キャップ８の周辺部、中央部を問わず同じ大きさに
なる。しかし、第８図に示したように、中央部が厚くな
っているため、その中央部のインダクタンスＬａｌ及び
抵抗Ｒａ２は、前記平板状をしたキャップ８の中央部の
インダクタンスＬ２及び抵抗Ｒ２より小さくなる（Ｌ
２＞Ｌ ａ ２ 、 Ｒ２＞Ｒａ ２） 、これにより
、キャップ８の共振周波数を信号配線５やボンディング
ワイヤ３を流れる信号電流の周波数より高くすることが
できる。As shown in FIG. 7, when the cap 8 has a flat plate shape, inductance L1 and resistance R1 at the periphery, inductance L2 and resistance R2 at the center, and inductance L3 and resistance at the periphery opposite to the above-mentioned periphery. The size of the resistor R3 is the same regardless of whether the cap 8 is at the periphery or the center. However, as shown in FIG. 8, since the central portion is thick, the inductance Lal and resistance Ra2 at the central portion are smaller than the inductance L2 and resistance R2 at the central portion of the flat cap 8. (L
2>La 2 , R2>Ra 2), thereby making it possible to make the resonance frequency of the cap 8 higher than the frequency of the signal current flowing through the signal wiring 5 and the bonding wire 3.
これらのことから、本実施例の半導体装置は、従来のも
のに比べて、半導体装置全体で、インダクタンスＬを約
１／２〜１／３に低減し、配線間容量を約１７１０に低
減し、配線抵抗を約１７２０〜１／３０に低減できる。For these reasons, the semiconductor device of this embodiment has the inductance L reduced to about 1/2 to 1/3, and the inter-wiring capacitance to about 1710, compared to the conventional one. Wiring resistance can be reduced to about 1,720 to 1/30.
以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
定電位配線によって信号配線同志の間が同軸ケーブルと
同程度にシールドされるので、信号配線間のアイソレー
ジ１ン特性を向上することができる。また、前記信号配
線と定電位配線（内部定電位配線、外部定電位配線、金
属膜）の間隔を調整することにより、信号配線のインピ
ーダンスを所望の値（例えば５０Ω）にすることができ
る。Since the constant potential wiring provides shielding between the signal wirings to the same degree as a coaxial cable, isolation characteristics between the signal wirings can be improved. Further, by adjusting the interval between the signal wiring and the constant potential wiring (internal constant potential wiring, external constant potential wiring, metal film), the impedance of the signal wiring can be set to a desired value (for example, 50Ω).
これらのことから、高速度半導体装置の信頼性を向上す
ることができる。For these reasons, the reliability of the high-speed semiconductor device can be improved.
第１図は、本発明の一実施例の半導体装置の断面図。
第２図は、第１図に示した半導体装置を■−■切断線の
ところで切って見たときの平面図。
第３図は、第２図に示した半導体装置の破線で囲んだ部
分■の拡大平面図、
第４図は、金属膜と、内部定電位配線、外部定電位配線
と、アウターリードと、キャップとのそれぞれの接続間
系を説明するための半導体装置の模式的な断面図、
第５図は、第１図に示した本発明の一実施例の半導体装
置と異る半導体装置の構成を説明するための図、
第６図は、第５図に示した半導体装置の信号配線が設け
られている部分の拡大平面図。
第７図は、平板状をしたキャップのインダクタンスＬ及
び抵抗Ｒの部分を説明するための図、第８図は、中央部
を周辺部より厚くしたキャップのインダクタンスし及び
抵抗Ｒの部分を説明するための回である。
゛図中、Ｚｏｏ・・・基板、１０１・・・キャビティ、
１・・・半導体チップ、２，９・・・金属膜、３・・・
ボンディングワイヤ、４・・・電極、５・・・信号配線
、６・・・内部定電位配線、７・・・外部定電位配線、
８・・・キャップ、１０・・・アウターリード、１１・
・・接続配線、１２・・・電気力線である。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1, taken along the cutting line -■. FIG. 3 is an enlarged plan view of the part (2) surrounded by the broken line of the semiconductor device shown in FIG. 2. FIG. FIG. 5 is a schematic cross-sectional view of a semiconductor device for explaining the respective connection systems between the semiconductor device and the semiconductor device, and FIG. FIG. 6 is an enlarged plan view of a portion of the semiconductor device shown in FIG. 5 where signal wiring is provided. Fig. 7 is a diagram for explaining the inductance L and resistance R of a flat cap, and Fig. 8 is a diagram for explaining the inductance and resistance R of a cap whose central part is thicker than its peripheral parts. This is a special occasion.゛In the figure, Zoo... substrate, 101... cavity,
1... Semiconductor chip, 2, 9... Metal film, 3...
Bonding wire, 4... Electrode, 5... Signal wiring, 6... Internal constant potential wiring, 7... External constant potential wiring,
8...Cap, 10...Outer lead, 11.
...Connection wiring, 12... Lines of electric force.
Claims (1)
号配線を備えた半導体装置において、前記信号配線の周
囲に、前記信号配線と同軸方向で同軸ケーブル状に複数
本の定電位配線を設けたことを特徴とする半導体装置。 ２、前記信号配線及び定電位配線は、前記半導体チップ
の主面に対して垂直な方向に延在するように、前記基板
の中に設けられていることを特徴とする特許請求の範囲
第１項に記載の半導体装置。 ３、前記信号配線及び定電位配線は、円柱状をしている
ことを特徴とする特許請求の範囲第１項に記載の半導体
装置。[Claims] 1. In a semiconductor device including a signal wiring in a substrate of a package in which a semiconductor chip is sealed, a plurality of coaxial cables are arranged around the signal wiring in the same direction as the signal wiring. A semiconductor device characterized by providing constant potential wiring. 2. Claim 1, wherein the signal wiring and constant potential wiring are provided in the substrate so as to extend in a direction perpendicular to the main surface of the semiconductor chip. The semiconductor device described in . 3. The semiconductor device according to claim 1, wherein the signal wiring and the constant potential wiring have a cylindrical shape.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63061626A JPH01233744A (en) | 1988-03-14 | 1988-03-14 | semiconductor equipment |
| EP19890300973 EP0331289A3 (en) | 1988-02-26 | 1989-02-01 | Semiconductor device with impedance matching means |
| KR1019890001518A KR890013750A (en) | 1988-02-26 | 1989-02-10 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63061626A JPH01233744A (en) | 1988-03-14 | 1988-03-14 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01233744A true JPH01233744A (en) | 1989-09-19 |
Family
ID=13176580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63061626A Pending JPH01233744A (en) | 1988-02-26 | 1988-03-14 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01233744A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005019582A (en) * | 2003-06-25 | 2005-01-20 | Sony Corp | High-speed signal circuit board and method of improving signal transmission property thereof |
-
1988
- 1988-03-14 JP JP63061626A patent/JPH01233744A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005019582A (en) * | 2003-06-25 | 2005-01-20 | Sony Corp | High-speed signal circuit board and method of improving signal transmission property thereof |
| JP4496721B2 (en) * | 2003-06-25 | 2010-07-07 | ソニー株式会社 | High speed signal circuit board and method for improving signal transmission characteristics thereof. |
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