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JPS62119949A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS62119949A
JPS62119949A JP25995285A JP25995285A JPS62119949A JP S62119949 A JPS62119949 A JP S62119949A JP 25995285 A JP25995285 A JP 25995285A JP 25995285 A JP25995285 A JP 25995285A JP S62119949 A JPS62119949 A JP S62119949A
Authority
JP
Japan
Prior art keywords
package
semiconductor device
coaxial cable
internal wiring
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25995285A
Other languages
Japanese (ja)
Inventor
Tamio Tomosugi
友杉　民夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25995285A priority Critical patent/JPS62119949A/en
Publication of JPS62119949A publication Critical patent/JPS62119949A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent inter-terminal crosstalk of signals by a method wherein the line leading out of an IC in a package is a coaxial cable. CONSTITUTION:A coaxial cable is constructed of a central conductor 1, external conductor 2, and dielectric component 3. The cable runs on the wall of a package 4 and is connected to an internal wiring 6. An IC chip is installed on an island 5 and connected to the internal wiring 6. The internal wiring 6 needs to be bare for impedance matching. In a semiconductor device package designed as such, crosstalk of signals between terminals may be kept very low.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路素子などを収納するパッケージに関
し、特に高周波信号に適合する半導体装置用パッケージ
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for accommodating integrated circuit elements and the like, and particularly to a package for a semiconductor device that is compatible with high frequency signals.

〔従来の技術〕[Conventional technology]

従来、高周波集積回路用パッケージには、特願昭５８−
１５２７０２号明ａ薔（”ＩＣバクケージ」に示さ扛る
様に、パッケージ内における外部引出し用配線ヲストリ
ップラインとし、インビルダンスを一定に保つ工夫がさ
れてきた。Conventionally, packages for high frequency integrated circuits have been
As shown in No. 152702 Akira ("IC back cage"), an attempt has been made to keep the inbuilt dance constant by using a strip line for the external wiring inside the package.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のストリップラインによるパッケージは、
ストリップラインを外部に引出す際、ストリップライン
構造を保つ事が難しい。第３図（ａ）。The conventional stripline package mentioned above is
It is difficult to maintain the stripline structure when pulling the stripline outside. Figure 3(a).

φ）は従来例の断面図、平面図であり、パッケージ内線
６に対しストリップラインを構成する接地８が一定の距
離を保って始めてス）　ＩＪツブラインとなる。しかし
パッケージ縁端でパッケージ内配線６がＩＣ外部リード
端子７に接がる個所ではストリップライン上部にも誘電
体がある為ストリップラインのインピーダンスはパッケ
ージ内配線のインピーダンスと同一にならない。またＩ
Ｃ外部リード端子７は単に線が出ているのみで所定のイ
ンピーダンスには保たれていないという欠点を有してい
る。φ) is a cross-sectional view and a plan view of a conventional example, and it becomes an IJ tube line only when the ground 8 forming the strip line maintains a certain distance from the package inner line 6. However, at the edge of the package where the internal wiring 6 connects to the IC external lead terminal 7, there is also a dielectric above the stripline, so the impedance of the stripline is not the same as the impedance of the internal wiring. Also I
The C external lead terminal 7 has the disadvantage that it is only a wire coming out and is not maintained at a predetermined impedance.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の半導体装置用パッケージは、ＩＣチップと外部
回路とを結ぶｌ引出し線が、同軸構造を持ったケーブル
で構成されることを特徴とする特〔実施例〕 次に本発明について図面を参照して説明する。The semiconductor device package of the present invention is characterized in that the lead wire connecting the IC chip and the external circuit is composed of a cable having a coaxial structure. and explain.

第１図（ａ）、φ）　、　（ｅ）は本発明の一実施例の
断面図２平面図　側面図である。同軸ケーブルは中心導
体り １と外部導体２及び誘電体３で構成され、パッケージ４
の壁を通ってパッケージ内配線６に接続される。ＩＣチ
ップはアイランド５上にマウントされ、ボンディングワ
イヤでパッケージ内配線６に接続される。パッケージ内
配線６はストリップライン構造とする事がインピーダン
ス整合上必要である。FIGS. 1(a), φ), and (e) are a cross-sectional view, a plan view, and a side view of an embodiment of the present invention. A coaxial cable consists of a center conductor 1, an outer conductor 2 and a dielectric 3, and a package 4
It is connected to the internal wiring 6 through the wall of the package. The IC chip is mounted on the island 5 and connected to the in-package wiring 6 with bonding wires. It is necessary for the wiring 6 in the package to have a stripline structure for impedance matching.

第２図（ａ）　、　（ｂ）　、　（ｅ）は本発明の他の
実施例の断面図であり、第１図の実施例がパッケージの
側面よシ同軸ケーブルを実装しているのに対し、パッケ
ージ下面よシ同軸ケーブルを実装する事を特徴としてい
る。利点としては同軸構造を損う事なくボンディングワ
イヤーに結線できることである。FIGS. 2(a), (b), and (e) are cross-sectional views of other embodiments of the present invention, whereas the embodiment of FIG. 1 has a coaxial cable mounted from the side of the package. The feature is that the coaxial cable is mounted on the bottom of the package. The advantage is that it can be connected to bonding wires without damaging the coaxial structure.

〔発明の効果〕 以上説明した様に本発明は、半導体装置用パッケージの
外部への引出し線を同軸ケーブルにする事により■イン
ピーダンスの保持ができる。■端子間のクロストークを
非常に低く抑えられる等、高周波ＩＣを封入するパッケ
ージとして要求される要件を満足する事ができる効果が
ある。[Effects of the Invention] As explained above, according to the present invention, impedance can be maintained by using a coaxial cable as a lead wire to the outside of a semiconductor device package. ■It has the effect of satisfying the requirements for a package that encapsulates a high-frequency IC, such as suppressing crosstalk between terminals to a very low level.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）　、　（ｂ）　、　（ｅ）は本発明の一実
施例の断面図。 平面図、側面図、第２図（ａ）　、　（ｂ）　、　（（
りは本発明の他の実施例の断面図、平面図、側面図、第
３図（ａ）。 （ロ）は従来例の断面図、平面図である。 １・・・・・・同軸ケーブルの中心導体、２・・・・・
・同軸ケーブルの外部導体、３・・・・・・同軸ケーブ
ルの誘電体、４・・・・・・パッケージ、５・・・・・
・ＩＣをマウントするアイランド、６・・・・・・パッ
ケージ内配線、７・・・・・・ＩＣ外部リード端子、８
・−・・・・ストリップラインを構成する接地。 （ご１．ン　　　　　　　　　　　　　　　　　　　　
　　　（しン　　　　　　　　　　　　　　　　　　（
Ｃ）８１図 σ） 篤FIGS. 1(a), (b), and (e) are cross-sectional views of one embodiment of the present invention. Plan view, side view, Fig. 2 (a), (b), ((
FIG. 3(a) is a cross-sectional view, a plan view, and a side view of another embodiment of the present invention. (b) is a sectional view and a plan view of a conventional example. 1... Center conductor of coaxial cable, 2...
・Outer conductor of coaxial cable, 3... Dielectric of coaxial cable, 4... Package, 5...
・Island for mounting the IC, 6...Inner package wiring, 7...IC external lead terminal, 8
・−・・Grounding that constitutes a strip line. (1.
(Shin (
C) Figure 81 σ) Atsushi

Claims (1)

【特許請求の範囲】[Claims] ＩＣチップと外部回路とを結ぶ引出し線が、同軸構造を
持ったケーブルで構成されることを特徴とする半導体装
置用パッケージ。A semiconductor device package characterized in that a lead wire connecting an IC chip and an external circuit is composed of a cable having a coaxial structure.
JP25995285A 1985-11-19 1985-11-19 Package for semiconductor device Pending JPS62119949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25995285A JPS62119949A (en) 1985-11-19 1985-11-19 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25995285A JPS62119949A (en) 1985-11-19 1985-11-19 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS62119949A true JPS62119949A (en) 1987-06-01

Family

ID=17341197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25995285A Pending JPS62119949A (en) 1985-11-19 1985-11-19 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS62119949A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2674680A1 (en) * 1991-03-26 1992-10-02 Thomson Csf METHOD FOR MAKING COAXIAL CONNECTIONS FOR ELECTRONIC COMPONENT, AND COMPONENT HOUSING COMPRISING SUCH CONNECTIONS.
JPH04368165A (en) * 1991-06-17 1992-12-21 Nec Yamagata Ltd Package for semiconductor device
WO2008032150A2 (en) * 2006-09-15 2008-03-20 Nokia Corporation Simultaneous bidirectional cable interface
US7803017B2 (en) 2006-09-15 2010-09-28 Nokia Corporation Simultaneous bidirectional cable interface

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2674680A1 (en) * 1991-03-26 1992-10-02 Thomson Csf METHOD FOR MAKING COAXIAL CONNECTIONS FOR ELECTRONIC COMPONENT, AND COMPONENT HOUSING COMPRISING SUCH CONNECTIONS.
US5323533A (en) * 1991-03-26 1994-06-28 Thomson-Csf Method of producing coaxial connections for an electronic component, and component package
JPH04368165A (en) * 1991-06-17 1992-12-21 Nec Yamagata Ltd Package for semiconductor device
WO2008032150A2 (en) * 2006-09-15 2008-03-20 Nokia Corporation Simultaneous bidirectional cable interface
WO2008032150A3 (en) * 2006-09-15 2008-06-26 Nokia Corp Simultaneous bidirectional cable interface
US7803017B2 (en) 2006-09-15 2010-09-28 Nokia Corporation Simultaneous bidirectional cable interface

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