JPH01229352A - Storage device - Google Patents

Abstract

PURPOSE:To attain a dynamic system action by providing priority control registers, controlling the priority of request acceptance and changing the priority of request acceptance in accordance with the system action. CONSTITUTION:The priority of request acceptance in a priority circuit 3 is in the order of 5A-5E. '1' is set in the whole priority control registers 1, and when respective request devices simultaneously transfer requests 5A-5E to a storage device, the request 5A is accepted. Next, a reception signal 7A is returned, the request 5B is accepted and a reception signal 7B is returned in a subsequent period. Since 011111 are set in the registers 1A-1E in the subsequent period, an AND circuit 2A is not gated in another request 5A. Consequently, the request 5C is accepted, and a reception signal 7C is returned. This shows that the priority of 5A-5E, has changed to 5C-5E, 5A or 5B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device of an information processing device, and more particularly to priority control of request reception between each requesting device and the storage device that are connected to a common bus.

[Conventional technology]

Conventionally, in this type of system, the priority of accepting request signals from each requesting device is determined in the initial design and cannot be changed.

[Problem to be solved by the invention]

The above-described conventional system has the disadvantage that dynamic system operation is not possible because the priority of request acceptance determined in the initial design cannot be changed.

[Means to solve the problem]

In the storage device of the present invention, each requesting device such as an arithmetic processing unit or an input/output processing device that makes a memory access request is connected to the storage device via a common bus, and each requesting device returns an accept signal in response to a request. The storage device includes a priority control register corresponding to the request signal of each requesting device, a circuit for ANDing the output signal of this register and each of the request signals, and a priority control register for receiving the AND signals. and a priority circuit that returns the accept signal with a .

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a process diagram of an embodiment of the present invention, and FIG. 2 is a timing chart of FIG.

The priorities for accepting requests in the priority circuit 3 in FIG. 1 are in the order of 5A to 5E. The value set in priority control register 1 is all logical °゛1”
If each requesting device transfers requests 5A to 5E to the storage device at the same time, request 5A with the highest priority is accepted and accept 7A is returned. Then, in the next tarok cycle, request 5B
is accepted and an accept 7B is returned.

Furthermore, in the first clock cycle, request 5A is transferred again, but each of IA to IE of control register 1 is set to logic "0".
Since 1111°° is set, the highest priority request 5A is not gated by the AND circuit 2A. Therefore, request 5C is accepted and accept 7C is returned. This has a priority of 5
A to 5E has become 50 to 5E, 5A, or 5B. Similarly, the priority is 5D to 5E
, 5A or 5B or 5C, the accept 7D is returned, and the priority is 5E, 5A or 5.
B, 5C, or 5D, and an accept 7E is returned.9 [Effects of the Invention] As explained above, the present invention provides a system in which each requesting device such as an arithmetic processing unit or an input/output processing unit and a storage device are connected to a common bus. A connected storage device that returns an accept in response to a request from each requesting device has a priority control register corresponding to the request from each requesting device, and this control register controls the priority of request acceptance. By changing the priority of request acceptance according to the system operation, dynamic system operation is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The timing chart of the figure is shown. 1...Priority control register, 2A to 2E...
・AND circuit, 3...Priority circuit, 4A~4
E...priority control signal, 5A-5E...request, 7A-7E...accept.

Claims (1)

[Claims] In a storage device in which each requesting device such as an arithmetic processing unit or an input/output processing device that makes a memory access request is connected to the storage device by a common bus, and an accept signal is returned in response to a request from each requesting device, It has a priority control register corresponding to the request signal of each of the requesting devices, and the output signal of this register is ANDed with each of the request signals, and each of the AND signals is input to a priority circuit, and the output signal of this register is ANDed with each of the request signals. A storage device characterized in that an accept signal is returned to each of the requesting devices according to a priority.