JPS59142658A - Shared memory control system - Google Patents

Abstract

PURPOSE:To control effectively a shared memory, by shifting the access to the shared memory with respect to time in accordance with the number of clocks during the time from the access start point of a preceding electronic computer to that of another electronic computer to access the memory asynchronously. CONSTITUTION:Electronic computers 10a and 10b having a Wait function by which the access time to the memory can be extended with an external signal share one memory 31. Access start points of computers 10a and 10b to the memory 31 are detected by clocks of the same clock generator 20. A required wait time is generated in the computer 10b in accordance with the number of clocks during the time from the start point of the preceding computer, for example, 10a to that of the computer 10b to shift the access to the shared memory 31 with respect to time, thus accessing the memory asynchronously.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a wait (WAIT) function that can extend memory access time using an external signal.
This invention relates to a shared memory control method when two combiators share one memory.

Traditionally, two converters may share the same memory. The following methods are available as memory control methods in such cases.

■ A time-sharing access method that switches the pass line and control twin connected to the memory at a speed several times faster than the access time of the two comviators.

■ While one of the two combinators is making a series of memory accesses, the other computer suspends the access due to software monitoring (it waits until the access by one comviator is completed).

However, although the method (2) has no software limitations, it requires a high-speed memory (1), and such memories generally have the drawbacks of low integration, as well as high power consumption and heat generation.

In addition, in the method (■), it is necessary for software to monitor the status of one in use and to control switching between bus twins and control twins.
The drawback is that it imposes a heavy burden on the software, resulting in a decrease in processing speed.

The object of the present invention is to eliminate such drawbacks, to use general-purpose memory devices, and to allow two computers to access their own memories without the need for any special software. The purpose is to provide a shared memory control method that allows arbitrary read and write access.

The present invention will be described in detail below using the drawings. FIG. 1 is a block diagram of an embodiment of a circuit for implementing the method of the present invention. This circuit uses Intel's 8-bit 8085 series microcombinator (hereinafter referred to as pp).

This example shows the case where the target is This circuit consists of two sets of IPU systems 10a and 10b.
, a black and red generation section 20 , and a shared memory part 30 .

The two sets of IPU systems 10a and 20b have the same circuit configuration. In the IJPU system 10a, 11a is a weight (W) that can extend the access time by an external signal.
8085 series) IPU with AIT) function,
12a is a latch. The latch 12a is pPU
ALEa (ADDRESSLATCHENABLE) the lower byte and data of the address sent from lla.
This is for separating signals by υ. 13a is an address decoder (ADDRESS DECODER) for obtaining a decode signal of the upper address bits.
Select signal 5ELa (l
The JPU system 10b generates 5ELb).

The clock/return generator 2o is a part that generates a clock (CLOCK) signal commonly used by the two IJPUs, and is connected to IC1.
If this is generated within one μPU, this circuit can be omitted by adding this signal to the other μPU.

The shared memory part 3o is static memory 31t,
Sequence control section 32 and 3-state gate 3
3a, 33b, and bidirectional three-state gate 34a,
34b 0 static memory 31 configured in many ways
is the storage element body of the shared memory, sb, storage (5).The capacity can be set arbitrarily. This shared memory is used in the general table usage, and as in the general case, the address signal ADR8 (the number of bits depends on the memory capacity), the data signal DA
TA (8 bits for 8085 series), select signal SEL, write signal WE (Write Enable
e), read signal 0E (Output Enable
) is input.

The sequence control unit 32 has two ljPolls.
m.

For access to a part of the shared memory from 11b,
Each bus 14a, 15m, 14 to the storage element 31
b, 15b or control signal (SELa, 5ELb,
Switching signals BEa, BEb (BusE
It is used to control the generation of ready signals READYa and RBADTh for each IJPc.

Note that the sequence control unit 32 has an internal state (0
~S) is provided, and when the SEI from each) IPtT, the R signal is LOW.
Counting starts from the rising edge of the clock when the AND of the ESET L, +3EL signal and the ALE signal is HIGH, and the internal state of the IPU is Tl, T2. T
3 (4), the increment is delayed by half a lock.

The three-state gates 33a and 33b open and close data and control signals on the bus in response to switching signals BEa and BEb from the sequence control section 32.

The bidirectional three-state gates 34a and 34b allow data to flow in both directions on the data bus, and are controlled by the READ signal and WRITE No. 8 from each 1JpC.

The operation in such a configuration will be explained next.

First, the memory access operation of the 8085-based IJPH will be described with reference to FIGS. 2 and 5. Wait state (WAIT 5TATE) 0 and 1! If the READY signal is (JIG) 1 (as shown in FIG. 2), one access is completed in three clocks. On the other hand,
The READY signal goes LO at the timing shown in Figure 3.
When the voltage drops to W, an I WAIT state occurs between Ti and T2, and the memory access period is extended by one clock cycle. Therefore, the sequence is completed in 4 clocks in the IWAIT state and 5 clocks in the WAIT state.

In this case, the information for memory is T2. Everything is fixed in the T3 period, and the memory access time tac
Regarding (the time from when the address and READ signal are determined to when the memory output data is determined), ~. +t
st≦T2 + T3/2 Here, tst is T2 + if you take into account the performance that satisfies the conditions of IIPH's read data set and door turn time (the time required for lJpty to confirm data in advance when reading data). Memory access is possible only during the T3 period. The present invention takes advantage of this point.

Now, assuming that two IPUs are operating on the same clock, the six states shown in FIGS. 4 to 9 occur when each accesses the shared memory. Among these, if the accesses overlap (SELa, 5ELb
There are five cases shown in Figs. 5 to 9. Here, access f to the shared memory
T2. When T3 is reached, actual access duplication occurs in three cases as shown in FIGS. 6, 7, and 8.

The sequence control section 32 controls the output of the counter (5
TATE) is 1 and the READY signal is HIGH, it is set at the falling edge of the clock, and the counter output is 3.
BEa is reset at the falling edge of BLACK and RI.

Generate BEb. As a result, as is clear from the figure, BEa and BBb do not overlap.

On the other hand, T2. For duplicate access at T3,
In the case of Figures 6 and 8, the IP address of the one whose access was delayed
H, and in the case of FIG. 7, the priority is determined in advance (in this case, 1JPU10a is given the higher priority).
Accordingly, each lower IJPU sets its READY signal to LOW and applies WAIT to delay access and avoid collision.

This READY signal indicates that the internal state of one of the IPHs is 0.
If the state of the other μpU is 1 just before it changes from 1 to 1, the period from the falling edge of the next clock to the falling edge of the next clock, and the internal state of one l'PU. If the state of the other )' PU is 0 immediately before the change from 0 to 1, the next clock fall υ two times later for 1JpU on the predetermined lower rank (7) side. These signals are generated under the control of the sequence control unit so that they are LOW in the same way as during the period up to the falling edge.

With this operation, the two 1jPUs can apparently access the shared memory in parallel without conflicting.

In addition, if one side of the IPH is an 8085-based computer and the other is an asynchronous checker's computer, the control signal of the latter is an 8085-based computer.
By synchronizing with the system clock, the above access method can be similarly adopted.

Further, the count start condition of the internal state counter can also be obtained by using the rising edge signal of the SEL signal in place of the ALE signal p, as shown in FIG.

However, in this case, in order to prohibit generation of the SEL signal in the fetch (FETCH) cycle, it is necessary to apply a gate with the status signal So, 81 (not shown) from -PU.

As explained above, according to the present invention, two 1'PU
The shared memory can be accessed at relatively high speed, just as each pPU accesses its own memory, without the intervention of any complicated software (8).

More specifically, since the control of simultaneous access to the shared memory of the two IPHs is performed purely by hardware by manipulating the READY signal of 1 JPU, no restrictions are placed on the software. The time reduction is 1 cro.

general IJPU
At a frequency of 3 MHz, the access time is 2
This has the advantage that a very common memory element with a duration of about 50 ns can be used.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a circuit for implementing the method of the present invention,
2 and 5 are diagrams for explaining the memory access operation of the 8o85 series IPH, and FIGS. 4 to 9 are time charts for explaining the present invention in detail. 11a, llb -) IPU% 12a, 12b
-2y chi 13m, 131y=address decoder, 2
0... Clock generation section, 31... Static memory, 32... Sequence control section, 33a,
33b - 5-state gate, 34a, 34b - bidirectional 3-state gate. Σ 2 ≦ U degree,) E−t=<
Tooth z 9 S Q mouth t

Claims (1)

[Claims] Two combiators each have a WAIT function that can extend memory access time using an external signal.
In a shared memory control method when two memories are shared, the WAIT time required for the latter combiator is generated according to the number of crosses from the start point of each combiator to the start point of the other combiator. A shared memory control method characterized by performing asynchronous access to memory by temporally shifting access to the shared memory.