JPH01226220A - Analogue/digital convertor - Google Patents

Abstract

PURPOSE:To reduce the cost of a whole system by providing a low pass filter, plural low speed A/D converters and an output switch control circuit controlling an output switching circuit and controlling to limit the A/D converters to be operated based on the frequency band of an analogue signal. CONSTITUTION:The analogue signal pass through the low pass filter 2, the frequency band is limited and are inputted to the A/D converters 3a-3d. On the other hand, a clock generation circuit 4 controls a clock which is inputted to a clock input terminal 401 by mode data inputted to a data input terminal 402. Namely, the A/D converters are controlled in such a way that they operate only one, or two, three or four operate in parallel by said data. An output switching circuit 7 switches time-divisionally data outputted from the A/D converters 3a-3d so as to output them. Consequently, the inexpensive A/D converters can be generated with simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an analog/digital conversion device that performs high-speed analog/digital conversion of television video signals and image signals of facsimiles, copying machines, etc.

BACKGROUND OF THE INVENTION Recently, analog/digital conversion methods have been widely used in fields such as image processing.

The conventional analog/digital conversion method will be described below with reference to FIG.

In FIG. 10, ``■'' is an analog signal input terminal, 2 is a low-pass filter that limits the same wave number band of the analog signal, 3 is a Δ/D converter that converts the band-limited analog signal into a digital signal, and 4. id A/
1) A clock generation circuit for operating the converter 3; 8 is an output terminal;

The operation of the above configuration will be explained below. The analog signal is supplied from input terminal I, passes through low-pass filter 2 to limit the frequency band, and then
/D converter 3 input signal. The A/D converter 3 converts the input analog signal into a digital signal using the signal output from the clock generation circuit 4.

Then, the result of conversion into a digital signal is outputted from the output terminal 8.

FIG. 11 is a timing diagram for the configuration of FIG. 10. Hereinafter, FIG. 11 will be explained with reference to FIG. 10. In FIG. 11, (a) is the low-pass filter 2
is output from. These are analog signals, n-1, n,
n+1, n+2· are sampling points.

11(b) is a signal output from the conversion clock generation circuit 4, and this signal is input to the A/D converter 3 to convert the analog signals 11-1 and n shown in FIG. 11(a).
, n+], n -1-2... are sampled and converted into digital signals.

The result of conversion into a digital signal is shown in FIG. 3(C).

Problems to be Solved by the Invention However, with the above configuration, when the frequency band of the analog signal is high like a television video signal, high-speed A
, it was necessary to use a /D converter. On the other hand, since high-speed A/D converters are very expensive, there is a problem in that the entire system becomes expensive as a result.

The present invention solves the above problems of the prior art, and aims to provide an inexpensive analog/digital conversion device.

Means to Solve the Problem In general, low speed Δ/D converters are very inexpensive. Therefore, the present invention includes: a low-pass filter that limits the frequency band of an analog signal; a plurality of low-speed A/D converters that pass through the low-pass filter and convert the analog signal with a limited frequency band into a digital signal;
By providing a clock generation circuit that operates the plurality of A/D converters, an output switching circuit that switches the results output from the plurality of A/D converters, and an output switching control circuit that controls the output switching circuit. , ” = something that achieves ejection target.

Operation The present invention uses the above configuration to control the operating A/D converters to be limited based on the frequency band of the analog signal. That is, when the frequency band of the analog signal is high, multiple A/D converters are controlled to operate in parallel in a time division manner, and when the frequency band of the analog signal is low, each A/D converter is controlled to operate in parallel. In order to eliminate the influence of variations in the conversion characteristics of A/
This configuration uses only one D converter.

EXAMPLE A first example of the present invention will be described below with reference to the drawings. The explanation will be simplified from now on6 ・＼−
/ We will discuss an example in which four A/D converters are used for this purpose.

FIG. 1 is a block diagram of a first embodiment of the present invention. In FIG. 1, 1 is an analog signal input terminal, 2 is a low-pass filter that limits the frequency band of the analog signal input from the input terminal 1, and has a data input terminal 201.

3a, 3b, 3C53d are A/D converters that convert band-limited analog signals into digital signals, 4 is a clock generation circuit that operates the A/D converters 3a, 3b, 3c, 3d, and a clock input terminal 401
, data input terminal 402, output terminals 403a, 403b
, 403C1403 (with l.

5 is a mode data input terminal that inputs data that determines the operation of the A/D converters 3a, 3b, 3c, and 3d; 6 is an output switching control circuit that limits the output switching circuit 7; a clock input terminal 601; a data input terminal; 602,
It has output terminals 603a and 603b. 7 is A/D
An output switching circuit 8 is an output terminal that switches the outputs of the converters 3a, 3b, and 3C3d according to a signal output from the output switching control circuit 6. Note that the clock input terminal 401 of the clock generation circuit 4 and the clock input terminal 601 of the output switching control circuit 6 are connected so that the same clock is inputted to the data input terminal 201 of the low-pass filter 2. and the data input terminal 402 of the clock generation circuit 4 and the data input terminal 6 of the output switching control circuit 6.
02 is connected so that the same mode data is input.

The operation of the above configuration will be explained below.

First, an analog signal is input from input terminal l. After this analog signal passes through a low-pass filter 2 to limit its frequency band, it is sent to A/D converters 3a, 3b, 3C.
13d. On the other hand, in the clock generation circuit 4, the clock input to the clock input terminal 401 is controlled by the mode data input to the data input terminal 402, and a plurality of A/D converters 3a, 3b, 3c, 3d
Output terminals 403a and 403a output signals that operate in a time-division manner.
Output from 03b, 403c, 403d. and,
The A/D:I7 converters 3a, 3b, 3c, and 3d convert the input analog signal into a digital signal using the signal output from the clock generation circuit 4. In the output switching control circuit 6, the clock input to the clock input terminal 601 is controlled by the mode data input to the data input terminal 602, and a signal that allows the output switching circuit 7 to switch in a timely manner is sent to the output terminals 603a, 603a, Output from 603b, 603c, and 603d. Note that data corresponding to the frequency band of the analog signal is input to the mode data input terminal 5. This data changes the cutoff wave number of low-pass filter 2, and depending on this data, it is possible to operate only one A/D converter, or operate two, three, or four in parallel. be controlled to do something. In the output switching circuit 7, the A/D is controlled by the signal output from the output switching control circuit 6.
Co9 - Switches and outputs the data output from the inverters 3a, 3b, 3c, and 3d in a time-sharing manner. The result is then output from the output terminal 8.

FIG. 2 is a block diagram showing the clock generation circuit 4 in more detail, and is composed of a counter 4a and a decoder 4b. Further, FIG. 3 is a timing diagram in FIG. 2. Hereinafter, the operation of the configuration shown in FIG. 2 will be explained with reference to FIG. First, mode data is input to the data input terminal 402, and the frequency division ratio of the counter 4a is determined. Next, connect the clock type power terminal 401 to the clock (Fig. 3(a)).
When input, the counter 4a outputs the signals shown in FIGS. 3(b) and 3(c). The decoder 4b receives the signal and outputs the signals shown in FIGS. 3(d), (e), (f), and (g). The output of this decoder 4b is input to A/D converters 3a, 3b, 3c, and 3d, respectively.

FIG. 4 is a block diagram showing the output switching control circuit 6 in more detail, and is composed of a delay circuit 6a and a counter 6b. Further, FIG. 5 is a timing diagram in FIG. 4. Hereinafter, the operation in FIG. 4 will be explained with reference to FIG. 5. First, mode data is input to the data input terminal 602, and the counter 6
Determine the division ratio of b. Next, the delay circuit 6a slightly delays the clock shown in FIG. 5(a) input from the clock input terminal 601, and outputs the signal shown in FIG. 5(b). This delay circuit 6a is provided to extract only a stable portion from the data output from the A/D converter.

The counter 6b receives the signal and receives the signal in FIGS.
) Outputs the signal shown in The output of this counter 6b is input to the output switching circuit 7. In the output switching circuit 7, when the output value of the counter 6b is "OL", the A/D
When the output of converter 3a is II 1 H, A/D
When the output of converter 3b is "2", it is the output of A/D converter 3C, and when it is '3#, it is the output of A/D converter 3.
The outputs of d are selected respectively.

Note that FIG. 6 is a timing diagram for the configuration of FIG. 1. In FIG. 6, (a) is an analog signal output from the low-pass filter 2, and in the figure, n − ], n, n
+1, n +2, . . . are sampling points. (1)), (C), (d), and (e) are signals output from the clock generation circuit 4, that is, (d) in FIG.
It corresponds to (e), (f), and (g), and (1)
'), (C'), (d'), and (e') are A/D converters 3a, 31), and 3c.

This is the result of time-division conversion using 3d. Also (f
) is a signal output from the output switching circuit 7, and this signal is output from the output terminal 8.

As is clear from the above description, according to this embodiment, by using multiple low-speed A/D converters and processing the input analog signals in parallel in a time-sharing manner to convert them into digital signals, inexpensive analog signals can be obtained. / A digital conversion device can be provided.

Next, a second embodiment of the present invention will be described.

FIG. 7 is a block diagram of a second embodiment of the present invention. 7, the difference from the configuration in FIG. 1 is the configuration of the output switching control circuit 6. In FIG.

That is, it does not have a clock input terminal 601.

Unfortunately, the data input to the data input terminal 602 is not mode data supplied from the outside, but is output from the clock generation circuit 4.

The operation of the above configuration will be explained below.

The operation up to the signals output from the A/D converters 3a, 3b, 3c, and 3d is the same as in the first embodiment. In the output switching control circuit 6, the signal output from the clock generation circuit 4 is input to the data input terminal 602, and the output switching circuit 7 outputs a signal from the output terminals 603a, 603b to enable timing switching. The subsequent operation is the same as that of the first embodiment, and will therefore be omitted.

FIG. 8 is a block diagram showing the output switching control circuit 6 of FIG. 7 in more detail, and is composed of an encoder 6C1 and a delay circuit 6d. Further, FIG. 9 is a timing diagram in FIG. 8. Hereinafter, the operation of the configuration shown in FIG. 8 will be explained with reference to FIG. 9. The encoder 6CK receives the signals output from the clock generation circuit 4, that is, the signals shown in FIGS. output the signal f).

The delay circuit 6d outputs the current signal with a slight delay, as shown in FIG.

The subsequent operation is the same as that of the first embodiment, and will therefore be omitted.

As described above, according to this embodiment, there is no need to synchronize with the counter 4a of the clock generation circuit 4, and a plurality of low-speed A/D converters are used with a relatively simple circuit configuration, and the input analog signals are time-divided. By performing parallel processing and converting into digital signals, an inexpensive analog/digital conversion device can be provided.

Effects of the Invention As described above, the present invention includes a low-pass filter that limits the same wave number band of an analog signal, and a plurality of low-speed amplifiers that pass through the low-pass filter and convert the analog signal whose frequency band is limited into a digital signal. a D converter, a clock generation circuit that operates the plurality of A/D converters, an output switching circuit that switches the results output from the plurality of A/D converters, and an output switching control that controls the output switching circuit. A circuit is provided,
It is possible to provide an inexpensive analog/digital conversion device by processing input analog signals in parallel in a time division manner and converting them into digital signals based on the frequency band of the input analog signals. Yes, it is possible, and the effect is great.

[Brief Description of the Drawings] Fig. 1 is a block wiring diagram of an analog/digital converter according to the first embodiment of the present invention, and Fig. 2 is a detailed block wiring diagram of a clock generation circuit, which is the main part of the device. , 3rd
The figure is a timing diagram in Figure 2, Figure 4 is a detailed wiring diagram of the output switching control circuit which is the main part of the device, Figure 5 is a timing diagram in Figure 4, and Figure 6 is A timing diagram of the analog/digital converter in the first embodiment, FIG. 7 is a block wiring diagram of the analog/digital converter in the second embodiment of the present invention, and FIG. 8 is an output that is the main part of the device. A detailed block wiring diagram of the switching control circuit, Figure 9 is a timing diagram in Figure 8, and Figure 1 is a detailed block diagram of the switching control circuit.
0 is a block diagram of a conventional analog/digital converter, and FIG. 11 is a timing diagram of a conventional analog/digital converter. 1°/° input terminal, 2...Low pass filter, 3a~
3d... A/D converter, 4... Clock generation circuit, 5... Mode data input terminal, 6... Output switching control circuit, 7... Output switching circuit, 8...
・Output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 (C) Figure 4 Figure 5 Cb) 1o'', tlpIs; o', t19o'lt Figure 6) -41n--tnt- j ts47Figure 8R---11-AFigure 9(d) '=b:l', 2:3':o:t', 2', :l',
o: Figure 10K Figure 1I

Claims (5)

[Claims] (1) A low-pass filter that limits the frequency band of an analog signal, a plurality of A/D converters that convert the analog signal whose frequency band is limited by passing through the low-pass filter into a digital signal, and the plurality of A/D converters An analog/digital conversion device comprising: a clock generation circuit that operates a converter; an output switching circuit that switches results output from the plurality of A/D converters; and an output switching control circuit that controls the output switching circuit. (2) The analog/digital conversion device according to claim 1, wherein the low-pass filter has a cutoff frequency that changes based on a control signal. (3) The analog/digital conversion device according to claim 1, wherein the clock generation circuit limits the operations of the plurality of A/D converters based on the control signal. (4) The analog/digital conversion device according to claim 1, wherein the output switching control circuit performs control to time-divisionally switch the outputs of the plurality of A/D converters based on the control signal. (5) The analog/digital conversion device according to claim 1, wherein the control signal of the output switching control circuit is set based on the frequency band of the analog signal.