JPS6412414B2 - - Google Patents

Description

[Detailed description of the invention]

When implementing a device using a digital circuit, a clock signal that defines the basic operating speed of the device is essential. Furthermore, the clock signals are required to have various phases depending on the delay of the circuit. There are two methods for generating clock signals with multiple phases: one is to use an analog delay circuit, the other is to have an extremely high-speed master clock internally, and digitally shift the phase of the clock signal in units of cycles of the master clock. There is a method of generating clocks with multiple phases by generating a clock with multiple phases. The present invention relates to a digital phase variable circuit that generates clock signals of various phases through digital processing. In the conventionally known phase variable circuit, there is a method in which the amount of phase shift to be taken out is prepared as many as the necessary number of phase states and is used by switching. However, as the number of phase states increases, the circuit becomes larger. An object of the present invention is to eliminate these drawbacks and provide a circuit that can stably change the phase. According to the present invention, the input signal is output as it is at the logic level "1" of the latch pulse, and is sampled when the logic level changes from "1" to "0".
A cascade circuit that includes multiple latch circuits whose logic level is held at "0" and a signal input to the first stage is output from the final stage, and a signal that is 2 ⁿ times the input signal. a plurality of stages of binary counting circuits for counting, and means for supplying the outputs of each stage of the counting circuits as latch pulses to the cascade circuit via respective control circuits, and in the control circuit, passage of the latch pulses is controlled by a control signal. A variable phase circuit controlled by This will be explained in detail below using the drawings. FIG. 1 is a block diagram showing the configuration of a conventional phase variable circuit. A clock signal input to input terminal 101 enters cascade-connected delay circuits 102 to 108 that provide a delay of phase θ, and a switch 109 switches between eight different phases obtained at the output of each delay circuit to output the desired signal to output terminal 110. Take out the amount of phase shift.
As described above, the conventional phase variable circuit has the drawback that it is necessary to prepare delay circuits for the required number of phase states, and an increase in the number of states results in an increase in the size of the circuit. FIG. 2 is a block diagram showing an embodiment of the digital phase variable circuit according to the present invention, and FIGS. 3A to 3E are waveform diagrams for explaining the operation of FIG. 2. In this embodiment, the phase switching for switching the number of the eight phase states explained in FIG. 1 is performed by controlling three control lines. The counting circuit is a four-stage synchronous counter, and the latch circuits are three cascaded. In this embodiment, the final stage output of the counter 202, that is, the master clock signal divided by 1/16, will be described as corresponding to the clock signal input from the terminal 101 in FIG. A high-speed master clock signal that enters the input terminal 201 enters a four-stage synchronous counter 202 and generates pulses divided by 1/2, 1/4, 1/8, and 1/16 at the output of each stage. . Here, latch circuit 2 which receives the clock signal as input
03 is given a 90 degree delay by a latch pulse pulse which is obtained by dividing the master clock signal by 1/8 (waveform diagram c). The output signal C of the latch circuit 204 is delayed by 45 degrees by the latch pulse N, which is obtained by dividing the master clock signal by 1/4 (waveform diagram H). The output signal H of the latch circuit 205 is delayed by 22.5 degrees (as shown in the waveform diagram) by a latch pulse obtained by dividing the master clock signal by 1/2, and is outputted to the output terminal 210. The above operation is performed using the three control lines of the input terminal 209.
The logic levels of CONT.1 to CONT.3 are all in the "0" state, and the outputs of each stage of the counter are all passing through the logical sum circuits (OR circuits) 206 to 208. Note that each latch circuit has a function of outputting the input signal as is when the logic level of the latch pulse is "1", so by controlling the three control lines of the input terminal 209 with control signals, eight different phases can be output. It can take the number of states. If the phase is set to 0 degrees when the logic levels of the control signals are all "0", the phase changes as shown in the following table are obtained by the control signals.

[Table] 〓 〓 indicates the logic level The embodiment shown in Figure 2 can have a phase shift of up to 157.5 degrees, but the polarity of the pulse signal divided by 1/16 can be switched by a control signal. So, 16
It can take the same number of phase states and a maximum phase shift of 337.5 degrees. Although the present embodiment has been described in which the phase adjustment is performed on a clock signal, it is clear that the same adjustment can be performed on other periodic signals as well. If the input of the latch circuit 203 in FIG. 2 is a general digital signal, a delay circuit for that signal can be easily realized. As explained above, according to the present invention, 2 ^m different phase states can be achieved by controlling m (m: integer) control lines with control signals.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional phase variable circuit, Fig. 2 is a block diagram showing an embodiment of a digital phase variable circuit according to the present invention, and Fig. 3 is a waveform diagram for explaining the operation of Fig. 2. be. In the figure, 101, 201, 209 are input terminals, 102-108 are delay circuits, 109 is a switch, 202 is a counter, 203-205 are latch circuits, 206-208 are OR circuits, 110, 2
10 is an output terminal.

Claims (1)

[Claims] 1 Input signal is latch pulse logic level “1”
It includes multiple latch circuits that output the signal as is, sample it when the logic level changes from "1" to "0", and hold the logic level at "0", and add the input signal to the first stage. A cascade circuit of the latch circuits that obtains the output signal from the final stage, and 2 ⁿ (n: integer) of the frequency of the input signal.
Multiple stages (m
and means for supplying the output of each of the m stages of the counter as a latch pulse to each stage of the cascaded circuit via m control circuits, respectively. A digital phase variable circuit characterized in that phase control is performed by controlling the passage of latch pulses using m control signals in each control circuit, thereby making the phase variable.