JPH01224991A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To invert data at a high speed by activating a register means, holding the information of a bit line pair, detaching the register means from the bit line pair by a switching means, inverting the data held by a driving means, and giving the inverted data to the bit line pair. CONSTITUTION:While register means 14-17 are activated according to an activation signal outputted by an activation signal generating means 2, the register means 14-17 and bit line pairs BLi and -BLi are detached by the switching means, and the inverse data are outputted to the bit line pairs BLi and -BLi based on the data held by the register means 14-17. Thus, it becomes unnecessary to once read the data to an I/O line when the data of the bit line pairs BLi and -BLi are inverted, and the data can be inverted at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, including a dynamic type semiconductor memory cell array of one transistor and one capacitance type, and is capable of preventing errors in information read from each memory cell. The present invention relates to semiconductor memory devices that detect and correct.

[Prior Art] FIG. 5 is a block diagram showing a conventional dynamic semiconductor memory. The semiconductor memory shown in FIG. 5 is disclosed in, for example, Japanese Patent Laid-Open No. 74535/1983.

First, a conventional dynamic semiconductor memory will be explained with reference to FIG. Memory cell MCOr O'r
The MC63r 63 is composed of a memory cell array of 64 rows and 64 columns, each of which is an N-channel MO
It is a one-transistor-one-capacitor dynamic type formed by an S transistor Q and a capacitor QCs. Each memory cell MCOr 0 to MC63+63 has a word line Wo-W,
, are connected to each word line Wo-w6. is selected by row decoder 1 according to a row address signal applied from the outside. Moreover, each memory cell MC,.

o-MC63, 63 has bit line pairs BLO, B in the column direction.
L, -BL63+ BL6. is connected. Furthermore, dummy cell DMo, o”DM63.

, are connected to dummy word lines DW, , DW, and one of the dummy cells is selected by these dummy word lines DWO, DW.

Bit line pair BLo, BLo-BL63. Sense amplifiers 5AO-5A, each having a P-channel MOS transistor 6.8 and an N-channel MOS transistor 7.9 cross-connected, are connected to BL6. P-channel MOS transistor 6.8 and N-channel MOS transistor 7 included in these sense amplifiers SA, -3A6°
．． Activation signals SP and SN generated from the sense signal generation circuit 2 are applied to each of the sources 9 .

Bit line pairs BL, , BLO, BL6 . , BL63 and I1
0 bus line pair I10. N-channel MOS between Ilo
Transistors 10-13 are connected. These N
At the gates of channel MOS transistors 10 to 13,
A Y signal line YO-wY63 is connected from the column decoder 3. Then, the N-channel MO8) transistors 10 to 13 are connected to the bit line pairs BLO and B by the Y signal line yo-my63.
L.

The conduction between BL63 and BL6a is controlled.

I10 bus line pair I10. A data output main amplifier 4 and a data manual buffer 5 are connected to Ilo. The data output main amplifier 4 outputs I10 in successive cycles.
Bus line pair I10. Information from Ilo is output to the outside as data output Do.

In the write cycle, the data manual buffer 5 converts the level of the externally applied data input DI and converts it into a complementary signal from the I10 bus line pair I10. Give to Ilo.

Next, the operation of the conventional dynamic semiconductor memory shown in FIG. 5 will be explained. Assume that, for example, memory cells MC, . . . are selected in a read cycle. At this time, the row decoder 1 increases the potentials of the word line Wo and the dummy word line DW, and the bit line pairs Br, o, B0-BL63, BLI, which have been charged to the same potential in advance,
3, the charge stored in the storage capacitor Cs is transferred. For example, the bit line BLO includes memory cells MCo,
The information charges of O are transferred, and the charges of dummy cells DM, , , , are transferred to the inverted bit line BL to generate a base voltage.

Subsequently, the sense amplifier activation signal SN becomes low level, the activation signal SP becomes high level, and the sense amplifier 5
Ao-8A6. is activated.

That is, bit line pairs BLO, BL, ~BL6. .

τ〒6. A minute difference in signal voltage due to the information charges transferred to the sensor is sensed and amplified. Next, the column decoder 3 selects the Y signal line (Yo in this case) in accordance with the externally applied column address signal, and its potential rises, causing bit line pair B
The voltages of the complementary signals on I10.Lo and BLo are respectively applied to the I10 bus line pair I10. The data is transmitted to Ilo, amplified by the data output main amplifier 4, and outputted to the outside as data output Do.

In a write cycle, data is written into a desired memory cell through a path opposite to that in the read cycle.

That is, the data input signal D applied from outside the chip
I is level-converted by the data manual buffer 5, becomes a complementary signal, and is transmitted to the I10 bus line pair 10 and Ilo. The complementary data input signals of the I10 bus line pair I10 and Ilo are transferred to the bit line pair BLo and BLo by selecting, for example, the YO signal line by the column decoder 3.

At that time, for example, if word line Wo is selected, this word line Wo and bit line pair BLo.

Information is written to the memory cells MC, . . . at the intersections with BL.

[Problems to be Solved by the Invention] Conventional semiconductor memory devices are configured as described above, and error detection and correction circuits are generally connected to the outside. If you try to incorporate error detection and correction circuits on the same chip, the I10 bus line pair I10
．． The data of the memory cell is transmitted to the outside of the memory cell array via Ilo, and errors are detected and corrected there. Then, it is necessary to write the error detection and correction results into the memory cells again via the 110 bus line pair I10 and Ilo. For this reason, there is a drawback that error detection and correction requires a long time. Furthermore, if the number of I10 bus line pairs I10 and Ilo is not increased, the number of bits that can be corrected at a time will be limited. For this reason, if an attempt was made to increase the number of bits, the number of I10 bus line pairs would increase, resulting in a problem that the chip area would increase.

Therefore, the main object of the present invention is to provide a semiconductor memory device that has a built-in error correction circuit that can perform error detection and correction on the same chip as a memory cell array, and a built-in data register that can add a data clearing function. The goal is to provide the following.

[Specific Means for Solving the Problems] The present invention provides a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, each memory cell storing information; A plurality of word lines for connecting memory cells arranged in the row direction, a plurality of bit line pairs to which the memory cells arranged in the column direction are connected and each forming a folded bit line pair, and a plurality of bit lines. a sense amplifier that is connected to each of the bit line pairs and detects and amplifies the potential difference between the bit line pairs; register means that holds data on the bit line pairs; and switching means that connects and connects the register means and the bit line pairs. , an input end that receives the output of the register means holding data on the bit line pair, and has a capacitive input impedance, and an output end that outputs data opposite to the data that the bit line pair had to the bit line pair. and an activation signal generating means for rendering the switching means non-conductive and generating a signal for activating the driving means.

[Operation] In the semiconductor memory device of the present invention, the register means is activated in response to an activation signal, and the register means and the bit line pair are separated by the switching means, so that the data held by the register means is By outputting reverse data to the bit line pair based on the I
There is no need to read out to 10 lines, and data can be inverted at high speed.

[Embodiment of the Invention] FIG. 1 is a specific block diagram of an embodiment of the invention, and FIG. 2 is an electrical circuit diagram showing an example of the error detection circuit shown in FIG. 1.

First, the configuration of an embodiment of the present invention will be described with reference to FIGS. 1 and 2. The semiconductor memory device having the error correction circuit shown in FIG. 1 is constructed in the same manner as the block diagram shown in FIG. 5 above, except for the following points.

Bit line pair BLo, BLO-BL6. , B.L.

, are connected to the inputs of the inverting amplifiers 14 to 17 via N-channel MO8 transistors 41 to 44, and are also connected to the error detection circuit 30.

These N-channel MOS transistors 41 to 44 are conductive at a high level and bit line pairs BLo, BLO""BL6
3. The BL 61 is connected to the inverting amplifiers 14 to 17 and the error detection circuit 30, and is disconnected at a low level. Inverting amplifier 14 includes an N-channel MOS transistor 18 and a P-channel MOS transistor 19,
The gates of these transistors 18 , 19 constitute the input end of the inverting amplifier 14 and are connected to the source of the transistor 42 . The drains of transistors 18 and 19 are commonly connected to the source of transistor 41, the source of transistor 18 is provided with the RN signal, and the source of transistor 19 is provided with the RP signal.

Similarly, inverting amplifiers 15, 16 and 17 each include transistors 20 to 25 and are constructed in the same manner as inverting amplifier 14 described above.

Further, a control circuit 40 is provided to control the conduction of the transistors 41 to 44 described above and to control the inverting amplifiers 14 to 17. The control circuit 40 includes an odd number of inverters 31 to 33 connected in cascade, a NAND gate 34, an inverter 35, and an odd number of inverters 36 and 37, each connected in cascade. When the activation signal SP is applied from the sense signal generation circuit 2 to the inverter 31, the RP multiplied signal is output from the output of the inverter 31, and the RN signal is output from the output of the inverter 32. These RP multiplied signals RN signals are given to inverting amplifiers 14-17.

Further, a DT times signal is output from the output of the inverter 35,
Applied to the gates of transistors 41-44. Further, a control signal is applied to the error detection circuit 30 via the inverters 33, 36 and 37, and the error detection circuit 30 outputs the error detection signal SYo, 5Y63 at the timing when this control signal is applied.

Further, a bit line BLo and an inverted bit line BL.

A drive circuit 60 is provided between the bit line BL63 and the bit line BL63.
and inverted bit line BL6. A drive circuit 70 is provided between and. The drive circuit 60 detects the bit line pair BLo, BL based on the data held in the inverting amplifiers 14 and 15 in response to the error detection signal SYo output in response to the detection of an error by the error detection circuit 30. It inverts information.

For this purpose, the drive circuit 60 includes N-channel MOS transistors 61 to 64 and P-channel MOS transistors 5),
66 included.

The drains of transistors 61 and 65 are connected to bit line BLo, the sources of transistors 62 and 66 are connected to inverted bit line BLo, the source of transistor 61 and the drain of transistor 62 are connected to the source of transistor 63, and the sources of transistors 62 and 66 are connected to bit line BLo. The drain is connected to a ground line (GND). The source of the transistor 65 and the drain of the transistor 66 are connected to the source of the transistor 64, and the drain of the transistor 64 is connected to the power supply line (Vc). An error detection signal SYo is applied from the error detection circuit 30 to each gate of the transistors 63 and 64. Further, the gates of transistors 61 and 65 are connected to the source of transistor 41,
The gates of transistors 62 and 66 are connected to the source of transistor 62.

The drive circuit 70 is also configured in the same manner as the drive circuit 60, and has N
Channel MOS transistors 71 to 74 and P channel M
Including OS transistors 75 and 76, error detection circuit 30
An error detection signal SY6° is given from

Next, the configuration of the error detection circuit 30 will be explained with reference to FIG. The error detection circuit 30 includes a syndrome generation circuit 301, a register 303, and a syndrome decoder 30.
4 and an AND gate 305. Syndrome generation circuit 301 is configured by combining a plurality of exclusive OR circuits 302, and information read from each memory cell is applied to syndrome generation circuit 301 via each bit line pair. In the syndrome generation circuit 301 shown in FIG. 2, a bit line pair is represented by one line to simplify the drawing.

The signal SYI of the element of each row of the syndrome calculated by the syndrome generation circuit 301 is held by the register 303. This register 303 generates signals SY, complementary to signals SY, and these signals sY, , s
Y, is given to the syndrome decoder 304, the output of the syndrome decoder 304 is given to the AND gate 305, and the error detection signal syo
-5y6 is output. Note that since the error detection circuit 30 configured in this manner is a conventionally known technology, further detailed explanation will be omitted.

FIG. 3 is a timing diagram for explaining the operation of one embodiment of the present invention.

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. 1 to 3. The timing diagram shown in FIG. 3 shows that when the i-th word line WI is selected, j
th bit line pair BLi.

The word line W selected by the row decoder 1 and the dummy word line Dw, (k
-0, 1) rises as shown in FIGS. 3(a) and 3(b), the information charge of the memory cell is read out to each bit line pair, and the potential rises as shown in FIG. 3(c). Change occurs.

Next, the sense signal generation circuit 2 outputs a low level signal SN as shown in FIG.
) outputs a high level signal SP. In response to these signals, sense amplifier SA is activated and the voltage on the bit line pair is amplified.

On the other hand, the signal SP is delayed by inverters 31 to 33, and as shown in FIG. 3(g), a signal RP is the output of the inverter 31, and a signal RP is the output of the inverter 32 as shown in FIG. 3(h). Inverting amplifier 14~ by RN
17 is activated.

Thereby, the inverting amplifiers 14 to 17 are connected to the bit line pairs BLO, BLG3, BLl, respectively.
Holds the information of i'3. Furthermore, the signal SP and the delayed signal SP are applied to the NAND gate 34 to be pulsed, and the pulse signal is inverted by the inverter 35, so that the T signal is transmitted to the transistors 41 to 44 as shown in FIG. 3(f). given to.

As a result, transistors 41 to 44 become conductive, and bit line pairs BL, BL, -BL6 . , BL6° is transferred to the inverting amplifiers 14 to 17, and the potential state is determined.

Further, the DT double signal potential becomes low level, transistors 41 to 44 become non-conductive, and bit line pairs BL, , B
L, -BL6. , BL6. and inverting amplifiers 14-17 are electrically isolated. Next, the error detection circuit 30 detects bit line pairs BL, , BLo transferred to the inverting amplifiers 14 to 17.
, BL63. Inspect the data of 100 LG3. Here, for example, if the data on the bit line pair BLo, BL is incorrect, the error detection circuit 30 outputs an error detection signal SY.

Set to “H”. Then, when the bit line BL is at the -"H" level and the inverted bit line BLO is at the "L" level, the point a is at the "H" level and the point b is at the "L" level, so the transistor 61 Since ゜63, 64, 66 are conductive and transistors 62゜65 are non-conductive, bit line BLO is connected to ground potential via transistor 61.63, and inverted bit line BLO is connected to transistor 64.6.
6 to the power supply potential Vc. Thereby,
The bit line BLo becomes “L” level, and the inverted bit line B
LO becomes “H” level and the bit line pair BLo, BLO
data will be corrected.

On the other hand, when the bit line BLO is at the "L" level and the inverted bit line BL is at the -"H" level, the point a becomes the "L" level and the point b becomes the "H" level, so the transistor 6
2.63, 64.65 conduct, transistor 61.6
Since bit lines BL and 6 become non-conductive, bit lines BL and
becomes "H" level, the inverted bit line BL becomes "L" level, and the data on the bit line pair BL, , BLO is corrected.

Regarding other bit line pairs, error detection signals sy6. is at the "L° level," transistors 73 and 74 remain non-conductive, and the data on bit line pair BL63.BL6. does not change.

As mentioned above, according to this embodiment, the error detection circuit 30
If the error detection signal SY0 is set to H'' in response to the detection of an error, the data on the bit line pair BLO, BL can be immediately inverted, which has the advantage that data can be corrected at high speed. be.

FIG. 4 is a block diagram showing another embodiment of the invention. The embodiment shown in FIG. 4 is based on the P channel M included in each of the drive circuits 60 and 70 shown in FIG.
In place of the OS transistors 65, 66, 75, 76, N
Channel MOS transistors 67, 68 and 77, 78 are provided, and their gates are cross-connected, and the embodiment shown in FIG. 4 is similar to the embodiment shown in FIG. 1. effect can be achieved. Note that in the embodiment shown in FIG. 4, the drive circuit 60
．． Even if the N-channel MOS transistors 1, 62, 71, and 72 included in each of the transistors 70 are constructed of P-channel MOS transistors, and the ground line and power supply line are reversed, the same operation as in FIG. 1 can be performed.

Furthermore, in the embodiment shown in FIGS. 1 and 4,
The outputs of the inverting amplifiers 14 to 17 are input only to the gates of the transistors, and the bit line pairs are inverted by the transistors 65 to 17.
6'8.75 to 78, the output impedance of the inverting amplifiers 14 to 17 may be small. Therefore, bit line pairs BL, BL, BL6
．． , BL6, to the inverting amplifiers 14-17 can be easily performed. In addition, the data is inverted using a low impedance transistor 65~68°75~78
Data can be inverted at high speed.

[Effects of the Invention] As described above, according to the present invention, the register means is activated in response to an activation signal to hold information on the bit line pair, and the register means is separated from the bit line pair by the switching means. Since the data held in the register means is inverted by the driving means and applied to the bit line pair, there is no need to read the data to the I10 line once when inverting the data on the bit line pair. can be done quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a specific electrical circuit diagram of the error detection circuit shown in FIG. 1. FIG. 3 is a timing diagram for explaining the operation of one embodiment of the present invention. FIG. 4 is a detailed block diagram showing another implementation of the invention. FIG. 5 is a block diagram showing a conventional semiconductor memory. In the figure, 1 is a row decoder, 2 is a sense signal generation circuit, 3 is a column decoder, 4 is a data output main amplifier, and 5 is a data manual buffer.
25.41~44.61~64.71~74,77.7
8 is an N-channel MOS transistor, 14-17 are inverting amplifiers, 19°25.65, 66.75.76 are P-channel MOS transistors, 30 is an error detection circuit, 31-
33. 35 to 37 are inverters, 34 is a NAND gate, 40 is a control circuit, MCI, ) is a memory cell, Wl is a word line, BLt, BLt is a bit line, SAI is a sense amplifier, Ilo and Ilo are I10 lines. .

Claims (1)

[Scope of Claims] A memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, each of which stores information, each of which has a plurality of words for connecting the memory cells arranged in the row direction. a plurality of bit line pairs each forming a folded bit line pair, each connected to each of the plurality of bit line pairs, and detecting a potential difference between the bit line pairs; a sense amplifier for amplifying the data on the bit line pair; register means for holding the data on the bit line pair; switching means for connecting and disconnecting the register means and the bit line pair; a driving means including an input end having a capacitive input impedance and an output end for outputting data opposite to data possessed by the bit line pair to the bit line pair; and the switching means are rendered non-conductive. and activation signal generating means for generating a signal for activating the driving means.